/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library.
 * It's the testing facility for cell_lib_std.act
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter  
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */

import "../../dataflow_neuro/primitives.act";
import globals;

open tmpl::dataflow_neuro;


defproc fifo_demux_bit_7_fifo (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
    bool _reset_B; 
    prs {
        Reset => _reset_B-
    }
    power supply;
    supply.vdd = Vdd;
    supply.vss = GND;


    fifo<8,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);

    demux_bit<7,0> demux(.in = fifo_pre.out);
    //Low active Reset 

    demux.supply.vss = GND;
    demux.supply.vdd = Vdd;
    demux.reset_B = _reset_B;

    fifo<7,5> fifo_post1(.in = demux.out1, .out=out1, .reset_B = _reset_B, .supply = supply);
    fifo<7,5> fifo_post2(.in = demux.out2, .out=out2, .reset_B = _reset_B, .supply = supply);


}

fifo_demux_bit_7_fifo b;