/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 * 
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */


import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;

namespace tmpl {
    namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// The block has the parameters:
// log_nw -> log2(number of words), parameters you can store
// wl -> word length, length of each word 
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
//        - the first bit is write/read_B
//        - the next log_nw bits describe the location, 
//        - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint log_nw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
    bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
    pint _nw = 2<<log_nw;
    //Validation of the input 
    Mx1of2<1+log_nw+wl> _in_temp;
    (i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
    vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
    sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
    // Generation of the fake clock pulse
    delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
    // Sending back to the ackowledge
    delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
    sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
    //Reset Buffers
    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl];
    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
    sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
    // Creating the different flip flop arrays
    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
    andtree<log_nw> atree[_nw];
    AND2_X1 and_encoder[_nw];
    sigbuf<wl> clock_buffer[_nw];
    DFFQ_R_X1 ff[_nw*wl];
    pint _bitval;
    (k:_nw:atree[k].supply = supply;)
    (_word_idx:_nw:
        // Decoding the bit pattern to understand which word we are looking at
        (pin_idx:log_nw:
            _bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
            [_bitval = 1 -> 
                atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
            [] _bitval = 0 ->
                atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
            []_bitval >= 2 -> {false : "fuck"};
            ]
        )
        // Activating the fake clock for the right word
        atree[_word_idx].out = _out_encoder[_word_idx];    
        and_encoder[_word_idx].a = _out_encoder[_word_idx];
        and_encoder[_word_idx].b = _clock;
        and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
        and_encoder[_word_idx].vdd = supply.vdd;
        and_encoder[_word_idx].vss = supply.vss;
        clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
        clock_buffer[_word_idx].supply = supply;
        // Describing all the FF and their connection
        (_bit_idx:wl:
            clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
            // ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
            // ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
            // ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
            // ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
            // ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
            // ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
        )
    )
}
}}