watchall
system "echo '[0] start test'"
system "echo '----------------------------------------------------------'"

set-qdi-channel-neutral "t.in" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.out.a 0
set t.out.v 0
#set t.registers._in_write.a 0
set Reset 0
cycle
status X
#mode run
cycle

assert-qdi-channel-neutral "t.out" 4
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
system "echo '----------------------------------------------------------'"

# Set delay config lines

cycle
system "echo '[2] delay line set'"
system "echo '----------------------------------------------------------'"


set-qdi-channel-valid "t.in" 5 3
# 3 -> 00011 -> writing mode, address 00, word 11
cycle
assert t.in.a 1
assert-qdi-channel-neutral "t.out" 4
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0

system "echo '[3] first writing done'"
system "echo '----------------------------------------------------------'"

set-qdi-channel-valid "t.in" 5 16
# 16 -> 10000 -> reading mode, address 00, word 00 (word doesn't needed here)
cycle
assert-qdi-channel-valid "t.out" 4 3
set t.out.v 1
cycle
set t.out.a 1
cycle
assert t.in.a 1
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0
assert-qdi-channel-neutral "t.out" 4
system "echo '[4] reading done'"
system "echo '----------------------------------------------------------'"