module tmpl_0_0dataflow__neuro_0_0ctree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , out, vdd, vss); 
   input vdd;
   input vss;
   input Iin0 ;
   input Iin1 ;
   input Iin2 ;
   input Iin3 ;
   input Iin4 ;
   output out;

// -- signals ---
   wire Itmp5 ;
   wire Iin3 ;
   wire Iin0 ;
   wire Iin2 ;
   wire Iin4 ;
   wire out ;
   wire Itmp6 ;
   wire Iin1 ;

// --- instances
A_2C_B_X1 IC2Els0  (.y(Itmp5 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1  (.y(out), .c1(Itmp5 ), .c2(Itmp6 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0  (.y(Itmp6 ), .c1(Iin2 ), .c2(Iin3 ), .c3(Iin4 ), .vdd(vdd), .vss(vss));
endmodule