/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 * 
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;

namespace tmpl {
	namespace dataflow_neuro {

		/**
		 * 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
		 *	Nx is the x size of the decoder array
		 * 	NxC is the number of wires in the x channel.
		 * 	Thus NxC should be something like NxC = ceil(log2(Nx))
		 * 	but my guess is that we can't do logs...
		 * 	N_dly_cfg is the number of config bits in the ACK delay line,
		 * 	with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells.
		 */
		export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
		defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny], 
			dly_cfg[N_dly_cfg], reset_B; power supply) {

			// Buffer to recieve concat(x,y) address packet
			buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
			// NEED TO BUFFER OUTPUTS FROM BUFFER I RECKON

			// Validity trees
			vtree<NxC> vtree_x (.supply = supply);
			vtree<NyC> vtree_y (.supply = supply);
			(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
			(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
			(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
			(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)


			// Delay ack line. Ack line is delayed (but not the val)
			A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
			addr_buf.out.v = C2el.y;

			// delayprog<N_dly_cfg> dly(.in = tielow.y, .s = dly_cfg, .supply = supply);
			delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
			
			// ACK MAY HAVE BEEN DISCONNECTED HERE
			// FOR TESTING PURPOSES
			// !!!!!!!!!!!!!!!!
			dly.out = addr_buf.out.a;
			// ACK MAY HAVE BEEN DISCONNECTED HERE
			// FOR TESTING PURPOSES
			// !!!!!!!!!!!!!!!!

			// AND trees
			pint bitval;
			andtree<NxC> atree_x[Nx];
			(k:0..Nx-1:atree_x[k].supply = supply;)
			(i:0..Nx-1:
				(j:0..NxC-1:
					bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
					[bitval = 1 -> 
						atree_x[i].in[j] = addr_buf.out.d.d[j].t;
					[]bitval = 0 ->
						atree_x[i].in[j] = addr_buf.out.d.d[j].f;
					[]bitval >= 2 -> {false : "fuck"};
					]
					atree_x[i].out = outx[i];
					)
			)

			andtree<NyC> atree_y[Ny];
			(k:0..Ny-1:atree_y[k].supply = supply;)
			(i:0..Ny-1:
				(j:0..NyC-1:
					bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
					[bitval = 1 -> 
						atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].t;
					[]bitval = 0 ->
						atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].f;
					]
					atree_y[i].out = outy[i];
					)
			)

		}


	}

}