module tmpl_0_0dataflow__neuro_0_0delayprog_32_4(out, in, Is0 , Is1 , vdd, vss); 
   input vdd;
   input vss;
   output out;
   input in;
   input Is0 ;
   input Is1 ;

// -- signals ---
   wire Idly0_y ;
   wire Is1 ;
   wire Idly0_a ;
   wire Idly2_a ;
   wire Idly2_y ;
   wire out ;
   wire in;
   wire Is0 ;
   wire Idly1_a ;
   wire I_a1 ;

// --- instances
AND2_X1 Iand20  (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iand21  (.y(Idly1_a ), .a(I_a1 ), .b(Is1 ), .vdd(vdd), .vss(vss));
MUX2_X1 Imu20  (.y(I_a1 ), .a(in), .b(Idly0_y ), .s(Is0 ), .vdd(vdd), .vss(vss));
MUX2_X1 Imu21  (.y(out), .a(I_a1 ), .b(Idly2_y ), .s(Is1 ), .vdd(vdd), .vss(vss));
DLY4_X1 Idly0  (.y(Idly0_y ), .a(Idly0_a ), .vdd(vdd), .vss(vss));
DLY4_X1 Idly1  (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
DLY4_X1 Idly2  (.y(Idly2_y ), .a(Idly2_a ), .vdd(vdd), .vss(vss));
endmodule