module tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_d_d31_d0 , Iin_d_d31_d1 , Iin_a , Iin_v , Iout_d0 , Iout_d1 , Iout_d2 , Iout_d3 , Iout_d4 , Iout_d5 , Iout_d6 , Iout_d7 , Iout_d8 , Iout_d9 , Iout_d10 , Iout_d11 , Iout_d12 , Iout_d13 , Iout_d14 , Iout_d15 , Iout_d16 , Iout_d17 , Iout_d18 , Iout_d19 , Iout_d20 , Iout_d21 , Iout_d22 , Iout_d23 , Iout_d24 , Iout_d25 , Iout_d26 , Iout_d27 , Iout_d28 , Iout_d29 , Iout_d30 , Iout_d31 , Iout_r , Iout_a , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , reset_B, vdd, vss); 
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   input Iin_d_d5_d0 ;
   input Iin_d_d5_d1 ;
   input Iin_d_d6_d0 ;
   input Iin_d_d6_d1 ;
   input Iin_d_d7_d0 ;
   input Iin_d_d7_d1 ;
   input Iin_d_d8_d0 ;
   input Iin_d_d8_d1 ;
   input Iin_d_d9_d0 ;
   input Iin_d_d9_d1 ;
   input Iin_d_d10_d0 ;
   input Iin_d_d10_d1 ;
   input Iin_d_d11_d0 ;
   input Iin_d_d11_d1 ;
   input Iin_d_d12_d0 ;
   input Iin_d_d12_d1 ;
   input Iin_d_d13_d0 ;
   input Iin_d_d13_d1 ;
   input Iin_d_d14_d0 ;
   input Iin_d_d14_d1 ;
   input Iin_d_d15_d0 ;
   input Iin_d_d15_d1 ;
   input Iin_d_d16_d0 ;
   input Iin_d_d16_d1 ;
   input Iin_d_d17_d0 ;
   input Iin_d_d17_d1 ;
   input Iin_d_d18_d0 ;
   input Iin_d_d18_d1 ;
   input Iin_d_d19_d0 ;
   input Iin_d_d19_d1 ;
   input Iin_d_d20_d0 ;
   input Iin_d_d20_d1 ;
   input Iin_d_d21_d0 ;
   input Iin_d_d21_d1 ;
   input Iin_d_d22_d0 ;
   input Iin_d_d22_d1 ;
   input Iin_d_d23_d0 ;
   input Iin_d_d23_d1 ;
   input Iin_d_d24_d0 ;
   input Iin_d_d24_d1 ;
   input Iin_d_d25_d0 ;
   input Iin_d_d25_d1 ;
   input Iin_d_d26_d0 ;
   input Iin_d_d26_d1 ;
   input Iin_d_d27_d0 ;
   input Iin_d_d27_d1 ;
   input Iin_d_d28_d0 ;
   input Iin_d_d28_d1 ;
   input Iin_d_d29_d0 ;
   input Iin_d_d29_d1 ;
   input Iin_d_d30_d0 ;
   input Iin_d_d30_d1 ;
   input Iin_d_d31_d0 ;
   input Iin_d_d31_d1 ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Iout_a ;
   input Idly_cfg0 ;
   input Idly_cfg1 ;
   input Idly_cfg2 ;
   input Idly_cfg3 ;
   input reset_B;

// -- signals ---
   wire Iout_vtree_in_d27_d0 ;
   wire Iin_d_d5_d0 ;
   wire Iin_d_d7_d0 ;
   wire Iin_d_d13_d0 ;
   output Iout_d30 ;
   output Iout_d2 ;
   wire Iout_vtree_in_d6_d0 ;
   wire Iin_d_d16_d1 ;
   wire Iin_d_d23_d1 ;
   wire Iin_d_d29_d0 ;
   wire Iout_vtree_in_d30_d0 ;
   wire Iin_d_d8_d0 ;
   wire Iin_d_d14_d0 ;
   wire Iin_d_d17_d0 ;
   wire Iin_d_d27_d1 ;
   wire Iin_d_d9_d0 ;
   output Iout_d29 ;
   wire Iin_d_d16_d0 ;
   wire Iout_vtree_in_d7_d0 ;
   wire Iin_d_d29_d1 ;
   output Iout_d27 ;
   wire Iout_vtree_in_d31_d0 ;
   wire Iout_vtree_in_d11_d0 ;
   wire Iin_d_d28_d1 ;
   wire Iin_d_d21_d1 ;
   wire Iin_d_d22_d0 ;
   output Iout_d6 ;
   output Iout_d28 ;
   output Iout_d31 ;
   wire Idly_in ;
   wire Iin_d_d0_d1 ;
   wire Iin_d_d8_d1 ;
   wire Iin_d_d9_d1 ;
   output Iout_d9 ;
   wire Iin_d_d7_d1 ;
   output Iout_d0 ;
   wire Iout_vtree_in_d17_d0 ;
   wire Iin_d_d3_d1 ;
   wire Iin_d_d21_d0 ;
   wire Iout_vtree_in_d26_d0 ;
   wire Iout_vtree_in_d28_d0 ;
   wire Iin_d_d20_d1 ;
   output Iin_a ;
   wire Iout_vtree_in_d10_d0 ;
   wire Iin_d_d17_d1 ;
   wire Iout_vtree_in_d1_d0 ;
   output Iout_d11 ;
   wire Iin_d_d18_d0 ;
   wire Iin_d_d26_d1 ;
   output Iout_d1 ;
   output Iout_d8 ;
   output Iout_d10 ;
   wire Iout_a ;
   wire Iin_d_d4_d1 ;
   wire Iout_vtree_in_d0_d0 ;
   wire Iin_d_d27_d0 ;
   wire Iin_d_d5_d1 ;
   wire Iin_d_d10_d0 ;
   wire Iin_d_d15_d0 ;
   wire Iout_vtree_in_d3_d0 ;
   wire Iin_d_d20_d0 ;
   wire Iout_vtree_in_d25_d0 ;
   wire Iin_d_d15_d1 ;
   wire Iout_vtree_in_d29_d0 ;
   output Iout_d12 ;
   wire Iin_d_d4_d0 ;
   wire Iin_d_d13_d1 ;
   wire Iin_d_d31_d1 ;
   wire Iout_vtree_in_d5_d0 ;
   output Iout_d17 ;
   wire Iout_vtree_in_d22_d0 ;
   wire Iout_vtree_in_d23_d0 ;
   wire Idly_cfg3 ;
   wire Iout_vtree_in_d2_d0 ;
   output Iout_r ;
   wire Iin_d_d0_d0 ;
   wire Iout_vtree_in_d14_d0 ;
   wire Iout_vtree_in_d15_d0 ;
   wire Iin_d_d22_d1 ;
   wire Iout_vtree_in_d4_d0 ;
   output Iout_d19 ;
   wire Iin_d_d12_d0 ;
   wire Iin_d_d30_d0 ;
   output Iout_d20 ;
   output Iout_d24 ;
   wire Iin_d_d2_d0 ;
   wire Iin_d_d28_d0 ;
   output Iout_d3 ;
   wire Iin_d_d23_d0 ;
   wire Iin_d_d24_d0 ;
   wire Iout_vtree_in_d18_d0 ;
   output Iout_d14 ;
   wire Iin_d_d19_d1 ;
   wire Iin_d_d25_d0 ;
   wire Iout_vtree_in_d21_d0 ;
   output Iout_d13 ;
   output Iout_d26 ;
   wire Iin_d_d11_d0 ;
   wire Iin_d_d11_d1 ;
   wire reset_B;
   wire Iout_vtree_in_d12_d0 ;
   wire Iout_vtree_in_d13_d0 ;
   output Iin_v ;
   output Iout_d15 ;
   wire Iout_vtree_in_d16_d0 ;
   wire Idly_cfg2 ;
   wire Iin_d_d19_d0 ;
   output Iout_d16 ;
   wire Iin_d_d1_d1 ;
   wire Iin_d_d31_d0 ;
   output Iout_d22 ;
   output Iout_d5 ;
   wire Iin_d_d18_d1 ;
   wire Iin_d_d26_d0 ;
   wire Iout_vtree_in_d9_d0 ;
   output Iout_d25 ;
   wire Iin_d_d25_d1 ;
   output Iout_d18 ;
   output Iout_d23 ;
   wire Idly_cfg0 ;
   output Iout_d4 ;
   wire Iout_vtree_in_d20_d0 ;
   wire Iout_vtree_in_d24_d0 ;
   wire Iin_d_d12_d1 ;
   output Iout_d7 ;
   wire Iout_vtree_in_d8_d0 ;
   wire Iin_d_d2_d1 ;
   wire Iin_d_d24_d1 ;
   wire Idly_cfg1 ;
   wire Iin_d_d6_d1 ;
   wire Iin_d_d10_d1 ;
   wire Iin_d_d1_d0 ;
   wire Iin_d_d6_d0 ;
   wire Iin_d_d30_d1 ;
   wire Iin_d_d3_d0 ;
   wire Iin_d_d14_d1 ;
   wire Iout_vtree_in_d19_d0 ;
   output Iout_d21 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly  (.out(Iout_r ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_332_4 Ibuf  (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_d_d7_d0 (Iin_d_d7_d0 ), .Iin_d_d7_d1 (Iin_d_d7_d1 ), .Iin_d_d8_d0 (Iin_d_d8_d0 ), .Iin_d_d8_d1 (Iin_d_d8_d1 ), .Iin_d_d9_d0 (Iin_d_d9_d0 ), .Iin_d_d9_d1 (Iin_d_d9_d1 ), .Iin_d_d10_d0 (Iin_d_d10_d0 ), .Iin_d_d10_d1 (Iin_d_d10_d1 ), .Iin_d_d11_d0 (Iin_d_d11_d0 ), .Iin_d_d11_d1 (Iin_d_d11_d1 ), .Iin_d_d12_d0 (Iin_d_d12_d0 ), .Iin_d_d12_d1 (Iin_d_d12_d1 ), .Iin_d_d13_d0 (Iin_d_d13_d0 ), .Iin_d_d13_d1 (Iin_d_d13_d1 ), .Iin_d_d14_d0 (Iin_d_d14_d0 ), .Iin_d_d14_d1 (Iin_d_d14_d1 ), .Iin_d_d15_d0 (Iin_d_d15_d0 ), .Iin_d_d15_d1 (Iin_d_d15_d1 ), .Iin_d_d16_d0 (Iin_d_d16_d0 ), .Iin_d_d16_d1 (Iin_d_d16_d1 ), .Iin_d_d17_d0 (Iin_d_d17_d0 ), .Iin_d_d17_d1 (Iin_d_d17_d1 ), .Iin_d_d18_d0 (Iin_d_d18_d0 ), .Iin_d_d18_d1 (Iin_d_d18_d1 ), .Iin_d_d19_d0 (Iin_d_d19_d0 ), .Iin_d_d19_d1 (Iin_d_d19_d1 ), .Iin_d_d20_d0 (Iin_d_d20_d0 ), .Iin_d_d20_d1 (Iin_d_d20_d1 ), .Iin_d_d21_d0 (Iin_d_d21_d0 ), .Iin_d_d21_d1 (Iin_d_d21_d1 ), .Iin_d_d22_d0 (Iin_d_d22_d0 ), .Iin_d_d22_d1 (Iin_d_d22_d1 ), .Iin_d_d23_d0 (Iin_d_d23_d0 ), .Iin_d_d23_d1 (Iin_d_d23_d1 ), .Iin_d_d24_d0 (Iin_d_d24_d0 ), .Iin_d_d24_d1 (Iin_d_d24_d1 ), .Iin_d_d25_d0 (Iin_d_d25_d0 ), .Iin_d_d25_d1 (Iin_d_d25_d1 ), .Iin_d_d26_d0 (Iin_d_d26_d0 ), .Iin_d_d26_d1 (Iin_d_d26_d1 ), .Iin_d_d27_d0 (Iin_d_d27_d0 ), .Iin_d_d27_d1 (Iin_d_d27_d1 ), .Iin_d_d28_d0 (Iin_d_d28_d0 ), .Iin_d_d28_d1 (Iin_d_d28_d1 ), .Iin_d_d29_d0 (Iin_d_d29_d0 ), .Iin_d_d29_d1 (Iin_d_d29_d1 ), .Iin_d_d30_d0 (Iin_d_d30_d0 ), .Iin_d_d30_d1 (Iin_d_d30_d1 ), .Iin_d_d31_d0 (Iin_d_d31_d0 ), .Iin_d_d31_d1 (Iin_d_d31_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Iout_vtree_in_d0_d0 ), .Iout_d_d0_d1 (Iout_d0 ), .Iout_d_d1_d0 (Iout_vtree_in_d1_d0 ), .Iout_d_d1_d1 (Iout_d1 ), .Iout_d_d2_d0 (Iout_vtree_in_d2_d0 ), .Iout_d_d2_d1 (Iout_d2 ), .Iout_d_d3_d0 (Iout_vtree_in_d3_d0 ), .Iout_d_d3_d1 (Iout_d3 ), .Iout_d_d4_d0 (Iout_vtree_in_d4_d0 ), .Iout_d_d4_d1 (Iout_d4 ), .Iout_d_d5_d0 (Iout_vtree_in_d5_d0 ), .Iout_d_d5_d1 (Iout_d5 ), .Iout_d_d6_d0 (Iout_vtree_in_d6_d0 ), .Iout_d_d6_d1 (Iout_d6 ), .Iout_d_d7_d0 (Iout_vtree_in_d7_d0 ), .Iout_d_d7_d1 (Iout_d7 ), .Iout_d_d8_d0 (Iout_vtree_in_d8_d0 ), .Iout_d_d8_d1 (Iout_d8 ), .Iout_d_d9_d0 (Iout_vtree_in_d9_d0 ), .Iout_d_d9_d1 (Iout_d9 ), .Iout_d_d10_d0 (Iout_vtree_in_d10_d0 ), .Iout_d_d10_d1 (Iout_d10 ), .Iout_d_d11_d0 (Iout_vtree_in_d11_d0 ), .Iout_d_d11_d1 (Iout_d11 ), .Iout_d_d12_d0 (Iout_vtree_in_d12_d0 ), .Iout_d_d12_d1 (Iout_d12 ), .Iout_d_d13_d0 (Iout_vtree_in_d13_d0 ), .Iout_d_d13_d1 (Iout_d13 ), .Iout_d_d14_d0 (Iout_vtree_in_d14_d0 ), .Iout_d_d14_d1 (Iout_d14 ), .Iout_d_d15_d0 (Iout_vtree_in_d15_d0 ), .Iout_d_d15_d1 (Iout_d15 ), .Iout_d_d16_d0 (Iout_vtree_in_d16_d0 ), .Iout_d_d16_d1 (Iout_d16 ), .Iout_d_d17_d0 (Iout_vtree_in_d17_d0 ), .Iout_d_d17_d1 (Iout_d17 ), .Iout_d_d18_d0 (Iout_vtree_in_d18_d0 ), .Iout_d_d18_d1 (Iout_d18 ), .Iout_d_d19_d0 (Iout_vtree_in_d19_d0 ), .Iout_d_d19_d1 (Iout_d19 ), .Iout_d_d20_d0 (Iout_vtree_in_d20_d0 ), .Iout_d_d20_d1 (Iout_d20 ), .Iout_d_d21_d0 (Iout_vtree_in_d21_d0 ), .Iout_d_d21_d1 (Iout_d21 ), .Iout_d_d22_d0 (Iout_vtree_in_d22_d0 ), .Iout_d_d22_d1 (Iout_d22 ), .Iout_d_d23_d0 (Iout_vtree_in_d23_d0 ), .Iout_d_d23_d1 (Iout_d23 ), .Iout_d_d24_d0 (Iout_vtree_in_d24_d0 ), .Iout_d_d24_d1 (Iout_d24 ), .Iout_d_d25_d0 (Iout_vtree_in_d25_d0 ), .Iout_d_d25_d1 (Iout_d25 ), .Iout_d_d26_d0 (Iout_vtree_in_d26_d0 ), .Iout_d_d26_d1 (Iout_d26 ), .Iout_d_d27_d0 (Iout_vtree_in_d27_d0 ), .Iout_d_d27_d1 (Iout_d27 ), .Iout_d_d28_d0 (Iout_vtree_in_d28_d0 ), .Iout_d_d28_d1 (Iout_d28 ), .Iout_d_d29_d0 (Iout_vtree_in_d29_d0 ), .Iout_d_d29_d1 (Iout_d29 ), .Iout_d_d30_d0 (Iout_vtree_in_d30_d0 ), .Iout_d_d30_d1 (Iout_d30 ), .Iout_d_d31_d0 (Iout_vtree_in_d31_d0 ), .Iout_d_d31_d1 (Iout_d31 ), .Iout_a (Iout_a ), .Iout_v (Idly_in ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_332_4 Iout_vtree  (.Iin_d0_d0 (Iout_vtree_in_d0_d0 ), .Iin_d0_d1 (Iout_d0 ), .Iin_d1_d0 (Iout_vtree_in_d1_d0 ), .Iin_d1_d1 (Iout_d1 ), .Iin_d2_d0 (Iout_vtree_in_d2_d0 ), .Iin_d2_d1 (Iout_d2 ), .Iin_d3_d0 (Iout_vtree_in_d3_d0 ), .Iin_d3_d1 (Iout_d3 ), .Iin_d4_d0 (Iout_vtree_in_d4_d0 ), .Iin_d4_d1 (Iout_d4 ), .Iin_d5_d0 (Iout_vtree_in_d5_d0 ), .Iin_d5_d1 (Iout_d5 ), .Iin_d6_d0 (Iout_vtree_in_d6_d0 ), .Iin_d6_d1 (Iout_d6 ), .Iin_d7_d0 (Iout_vtree_in_d7_d0 ), .Iin_d7_d1 (Iout_d7 ), .Iin_d8_d0 (Iout_vtree_in_d8_d0 ), .Iin_d8_d1 (Iout_d8 ), .Iin_d9_d0 (Iout_vtree_in_d9_d0 ), .Iin_d9_d1 (Iout_d9 ), .Iin_d10_d0 (Iout_vtree_in_d10_d0 ), .Iin_d10_d1 (Iout_d10 ), .Iin_d11_d0 (Iout_vtree_in_d11_d0 ), .Iin_d11_d1 (Iout_d11 ), .Iin_d12_d0 (Iout_vtree_in_d12_d0 ), .Iin_d12_d1 (Iout_d12 ), .Iin_d13_d0 (Iout_vtree_in_d13_d0 ), .Iin_d13_d1 (Iout_d13 ), .Iin_d14_d0 (Iout_vtree_in_d14_d0 ), .Iin_d14_d1 (Iout_d14 ), .Iin_d15_d0 (Iout_vtree_in_d15_d0 ), .Iin_d15_d1 (Iout_d15 ), .Iin_d16_d0 (Iout_vtree_in_d16_d0 ), .Iin_d16_d1 (Iout_d16 ), .Iin_d17_d0 (Iout_vtree_in_d17_d0 ), .Iin_d17_d1 (Iout_d17 ), .Iin_d18_d0 (Iout_vtree_in_d18_d0 ), .Iin_d18_d1 (Iout_d18 ), .Iin_d19_d0 (Iout_vtree_in_d19_d0 ), .Iin_d19_d1 (Iout_d19 ), .Iin_d20_d0 (Iout_vtree_in_d20_d0 ), .Iin_d20_d1 (Iout_d20 ), .Iin_d21_d0 (Iout_vtree_in_d21_d0 ), .Iin_d21_d1 (Iout_d21 ), .Iin_d22_d0 (Iout_vtree_in_d22_d0 ), .Iin_d22_d1 (Iout_d22 ), .Iin_d23_d0 (Iout_vtree_in_d23_d0 ), .Iin_d23_d1 (Iout_d23 ), .Iin_d24_d0 (Iout_vtree_in_d24_d0 ), .Iin_d24_d1 (Iout_d24 ), .Iin_d25_d0 (Iout_vtree_in_d25_d0 ), .Iin_d25_d1 (Iout_d25 ), .Iin_d26_d0 (Iout_vtree_in_d26_d0 ), .Iin_d26_d1 (Iout_d26 ), .Iin_d27_d0 (Iout_vtree_in_d27_d0 ), .Iin_d27_d1 (Iout_d27 ), .Iin_d28_d0 (Iout_vtree_in_d28_d0 ), .Iin_d28_d1 (Iout_d28 ), .Iin_d29_d0 (Iout_vtree_in_d29_d0 ), .Iin_d29_d1 (Iout_d29 ), .Iin_d30_d0 (Iout_vtree_in_d30_d0 ), .Iin_d30_d1 (Iout_d30 ), .Iin_d31_d0 (Iout_vtree_in_d31_d0 ), .Iin_d31_d1 (Iout_d31 ), .out(Idly_in ), .vdd(vdd), .vss(vss));
endmodule