diff --git a/act/actsim_test_bench_lib.conf b/act/actsim_test_bench_lib.conf
index cd960f6..2268ed4 100644
--- a/act/actsim_test_bench_lib.conf
+++ b/act/actsim_test_bench_lib.conf
@@ -12,8 +12,8 @@ begin sim
         string sim::testbench::fcheck_next "check_next"
         string sim::testbench::fdump_to_file "dump_to_file"
         string sim::testbench::fcontrol_next "control_next"
-        string sim::testbench::fcontrol_next "control_get"
-        string sim::testbench::fcontrol_next "control_wait"
+        string sim::testbench::fcontrol_get "control_get"
+        string sim::testbench::fcontrol_wait "control_wait"
      end
    end
 end
diff --git a/act/test_bench_lib.act b/act/test_bench_lib.act
index 0497f3f..96e1aab 100644
--- a/act/test_bench_lib.act
+++ b/act/test_bench_lib.act
@@ -24,15 +24,20 @@
  */
 
 
-namespace sim::testbench {
+namespace sim{
+  namespace testbench {
 
-function fsource_init(int verbose) : int;
+function finit (int verbose) : int;
 function fsource_next(int id; int sim_step) : int;
 function fsource_get(int id; int bit_width) : int;
 function fcheck_next(int id; int sim_step) : int;
 function fcheck_in_order(int id; int data) : int;
 function fcheck_out_of_order(int id; int data) : int;
 function fdump_to_file(int id; int sim_step; int data) : int;
+function fcontrol_next(int dontcare) : int;
+function fcontrol_get(int dontcare) : int;
+function fcontrol_wait(int dontcare) : int;
+
 
 template<pint BIT_WIDTH;pint ID>
 defproc channel_source(chan!(int<BIT_WIDTH>) out; chan?(int) sim_step; chan!(int) done)
@@ -40,8 +45,8 @@ defproc channel_source(chan!(int<BIT_WIDTH>) out; chan?(int) sim_step; chan!(int
   int current_step, t,data;
   chp {
    *[ sim_step?current_step; t := 1;
-    *[ t = 1 -> t := fchannel_source_next(ID,current_step);
-      [ t = 1 -> data := fchannel_source_get(ID,BIT_WIDTH); out!data ; log("send ", data, " on source ", ID) 
+    *[ t = 1 -> t := fsource_next(ID,current_step);
+      [ t = 1 -> data := fsource_get(ID,BIT_WIDTH); out!data ; log("send ", data, " on source ", ID) 
       [] else -> done!1
       ]
     ]
@@ -88,10 +93,11 @@ defproc channel_checker_out_of_order(chan?(int<BIT_WIDTH>) in; chan?(int) sim_st
 template<pint BIT_WIDTH;pint ID>
 defproc channel_dump(chan?(int<BIT_WIDTH>) in; chan?(int) sim_step)
 {
-  int current_step, t;
+  int current_step, t,in_tmp;
   chp {
+
    *[ [ #sim_step -> sim_step?current_step
-      | #in -> t:=fdump_to_file(ID,current_step,in)
+      [] #in -> in?in_tmp; t:=fdump_to_file(ID,current_step,in_tmp) //here should be non-deterministic but it doesn't work
       ]
     ]
   }
@@ -106,13 +112,13 @@ defproc control(chan(int) sim_step_source[NUMBER_SOURCE]; chan(int) sim_step_che
     t:=1;
     failure_free:=1;
     *[ t = 1 -> current_step := fcontrol_get();
-      [ current_step = 0 -> skip; // reset here
+      [ current_step = 0 -> skip // reset here
       [] else ->
-        (,:j:1..NUMBER_SOURCE: sim_step_source[j]!current_step),
-        (,:j:1..NUMBER_CHECKER: sim_step_checker[j]!current_step),
-        (,:j:1..NUMBER_DUMP: sim_step_dump[j]!current_step);
-        (:j:1..NUMBER_SOURCE: done_source[j]?success; failure_free := failure_free & success);
-        (:j:1..NUMBER_CHECKER: done_checker[j]?success; failure_free := failure_free & success);
+        (,j:1..NUMBER_SOURCE: sim_step_source[j]!current_step),
+        (,j:1..NUMBER_CHECKER: sim_step_checker[j]!current_step),
+        (,j:1..NUMBER_DUMP: sim_step_dump[j]!current_step);
+        (;j:1..NUMBER_SOURCE: done_source[j]?success; failure_free := failure_free & success);
+        (;j:1..NUMBER_CHECKER: done_checker[j]?success; failure_free := failure_free & success)
       ];
       wait := fcontrol_wait();
       [ wait > 0 -> skip // exec cycle
@@ -125,3 +131,4 @@ defproc control(chan(int) sim_step_source[NUMBER_SOURCE]; chan(int) sim_step_che
   }
 }
 }
+}
diff --git a/act/test_bench_lib.c b/act/test_bench_lib.c
index fb92bac..069890a 100644
--- a/act/test_bench_lib.c
+++ b/act/test_bench_lib.c
@@ -234,7 +234,7 @@ struct expr_res check_in_order (int num, struct expr_res *args)
         t.v = 1;
       }
       else {
-        check_errors++
+        check_errors++;
         fprintf(logfile,"[FAILURE] expected %d got %d on check %d - %d; Error count %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,i,check_errors); fflush(logfile);
         t.v = 0;
       }
@@ -280,7 +280,7 @@ struct expr_res check_out_of_order (int num, struct expr_res *args)
   if (t.v == 0){
     check_errors++;
     fprintf(logfile,"[FAILURE] could not find %d on check %d; Error count: %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,check_errors); fflush(logfile);
-  }s
+  }
   t.width = 1;
   return t; 
 }
diff --git a/readme.md b/readme.md
index 5ee2b44..bffeed5 100644
--- a/readme.md
+++ b/readme.md
@@ -42,7 +42,10 @@ because the controller sets the time out in verilog set your simulation time in
 this unit is called **control**, it reads a file with the name `control.csv`.
 
 the csv format is, one line per simulation step:
-``` first line: <start step>, <end step> all other lines: <simulation step>, <time to wait for> ```
+
+``` 
+first line: <start step>, <end step> all other lines: <simulation step>, <time to wait for> 
+```
 
 step 0 is the test initialisation - so the reset sequence - and is always
 executed, it can not be used in the test bench.
@@ -101,6 +104,10 @@ the maximum vector width is assumed with 64 bits, as limited by actsim plugin sy
 
 currenty the files are read and searched in the excecution folder of actsim.
 
+## Installation
+- make sure you have your ACT flow installed (otherwise go here https://github.com/bics-rug/yale-asyncvlsi-actflow/releases/tag/rowling)
+- 
+
 ## running actsim 
 
 the config file has to be included to load the test bench,
diff --git a/test/examples/helloworld.act b/test/examples/helloworld.act
new file mode 100644
index 0000000..da34fad
--- /dev/null
+++ b/test/examples/helloworld.act
@@ -0,0 +1,34 @@
+
+/*************************************************************************
+ *
+ *
+ * Copyright 2022 Ole Richter - University of Groningen
+ * Copyright 2022 Michele Mastella - University of Groningen
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ *  Boston, MA  02110-1301, USA.
+ *
+ **************************************************************************
+ */
+
+import "../../act/test_bench_lib.act";
+import globals;
+
+defproc test(){
+	chan(int<5>) channel;
+	//sim::testbench::control<1,1,0,1> control;
+	//sim::testbench::channel_source<5,0> source(.out=channel,.sim_step=control.sim_step_source[0],.done=control.done_source[0]);
+	//sim::testbench::channel_checker_in_order<5,0> sink(.in=channel,.sim_step=control.sim_step_checker,.done=control.done_checker[0]);
+}
\ No newline at end of file