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actlib_dataflow_neuro
Verilog 0 0
the classic dataflow library for generating event systems
Updated 2024-09-23 08:50:41 +02:00
teensy_41_levelshift
0 0
Updated 2024-03-21 17:02:20 +01:00
smu_triaxial_converter
HTML 0 0
pcb converting traxial cables to pin headers for chip power measurements with jumper cables
Updated 2023-03-28 18:06:16 +02:00
test_bench_lib
C 0 0
This is a test bench library for use with async DUTs for both actsim CHP, actsim PRS and Cadence AMS simulations (or other verilog simulators). The test benches are supposed to be modular and are controlled by a set of CSV files.
Updated 2023-01-09 14:51:02 +01:00