68 lines
1.3 KiB
Systemverilog
68 lines
1.3 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 02:02:47 PM
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// Design Name:
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// Module Name: mem_stim_tb
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`define CLK_HALF_PERIOD 2
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module mem_stim_tb(
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);
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logic CLK;
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logic RST_N;
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logic ACK;
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logic [8:0] ADDR_T;
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logic [8:0] ADDR_F;
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wire END_SIG;
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initial begin
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CLK = 1'b0;
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forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
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end
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initial begin
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RST_N = 1'b0;
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#(4 * `CLK_HALF_PERIOD);
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RST_N = 1'b1;
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#(20 * `CLK_HALF_PERIOD);
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end
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mem_stim #(
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.DATA_WIDTH(9)
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) ut (
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.clk(CLK),
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.rst_n(RST_N),
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.restart(~RST_N),
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.ack(ACK),
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.addr_t(ADDR_T),
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.addr_f(ADDR_F),
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.done(END_SIG)
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);
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autoack auto_ack (
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.CLK(CLK),
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.RST(!RST_N),
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.OUTPUT_BITS_ONION_p(ADDR_T),
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.OUTPUT_BITS_ONION_n(ADDR_F),
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.OUTPUT_BITS_ONION_A_AO(ACK)
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);
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endmodule
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