66 lines
1.2 KiB
Systemverilog
66 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/16/2026 05:49:17 PM
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// Design Name:
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// Module Name: stimulus_gen_tb
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`define CLK_HALF_PERIOD 2
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module stimulus_gen_tb(
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);
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logic CLK;
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logic RST;
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logic ACK;
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logic REQ;
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logic [4:0] ADDR;
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wire END_SIG;
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initial begin
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CLK = 1'b0;
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forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
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end
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initial begin
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RST = 1'b1;
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#(4 * `CLK_HALF_PERIOD);
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RST = 1'b0;
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#(20 * `CLK_HALF_PERIOD);
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end
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always_ff @(posedge CLK)
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begin
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if (REQ) begin
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ACK <= 1'b1;
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end else begin
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ACK <= 1'b0;
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end
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end
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stimulus_gen #() ut (
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.CLK_I(CLK),
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.RST_I(RST),
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.REQ_O(REQ),
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.ACK_I(ACK),
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.ADDR_O(ADDR),
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.END_O(END_SIG)
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);
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endmodule
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