71 lines
1.5 KiB
Systemverilog
71 lines
1.5 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/16/2026 07:33:07 PM
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// Design Name:
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// Module Name: top_interface_tb
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`define CLK_HALF_PERIOD 2
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module top_interface_tb(
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);
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logic CLK;
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logic RSTN;
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logic AERIN_REQ;
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logic AERIN_ACK;
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logic [4:0] AERIN_ADDR;
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logic AEROUT_ACK;
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logic [8:0] AEROUT_ADDR_T;
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logic [8:0] AEROUT_ADDR_F;
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initial begin
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CLK = 1'b0;
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forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
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end
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assign RST = !RSTN;
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top_interface #() ut (
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.CLK(CLK),
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.RSTN_O(RSTN),
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.AERIN_REQ(AERIN_REQ),
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.AERIN_ADDR(AERIN_ADDR),
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.AERIN_ACK(AERIN_ACK),
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.AEROUT_ACK(AEROUT_ACK),
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.AEROUT_ADDR_T(AEROUT_ADDR_T),
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.AEROUT_ADDR_F(AEROUT_ADDR_F)
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);
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autoack auto_ack (
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.CLK(CLK),
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.RST(RST),
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.OUTPUT_BITS_ONION_p(AEROUT_ADDR_T),
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.OUTPUT_BITS_ONION_n(AEROUT_ADDR_F),
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.OUTPUT_BITS_ONION_A_AO(AEROUT_ACK)
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);
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stimulus_gen #() stim (
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.CLK_I(CLK),
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.RST_I(RST),
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.REQ_O(AERIN_REQ),
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.ACK_I(AERIN_ACK),
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.ADDR_O(AERIN_ADDR)
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);
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endmodule
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