actlib_dataflow_neuro/dataflow_neuro/primitives.act

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/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import tmpl::dataflow_neuro::cell_lib_std;
import tmpl::dataflow_neuro::cell_lib_async;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
// @ole talk to rajit, we use valid the wrong way arround according to stdlib
template<pbool reset; pint V; pint M>
defchan gen_avMx1of2 <: chan(int<M>) (std::data::Mx1of2?!<M> d; bool!? a; bool!? v)
{
{ 0 <= V & std::ceil_log2(V) < M : "Initial token value out of range" };
methods {
/*-- initialize channel, sender end --*/
send_init {
[ reset -> (,i:M: [ ((V >> i) & 1) = 0 -> d.d[i].f+ [] else -> d.d[i].t+ ]);[v]
[] else -> (,i:M: d.d[i].t-,d.d[i].f-);[~v]
]
}
/*-- set output data --*/
set {
(,i:M: [((self >> i) & 1) = 0 -> d.d[i].f+ [] else -> d.d[i].t+ ]);[v]
}
/*-- finish synchronization --*/
send_up {
[a]
}
/*-- reset part of the protocol --*/
send_rest {
(,i:M: d.d[i].t-,d.d[i].f-);[~v],[~a]
}
/*-- initialize channel, receiver end --*/
recv_init {
v-;a-
}
/*-- get value --*/
get {
[(&i:M: d.d[i].t | d.d[i].f)];
self := 0;
(;i:M: [ d.d[i].t -> self := self | (1 << i)
[] else -> skip
]
)
}
/*-- finish synchronization action --*/
recv_up {
v+,a+
}
/*-- reset part of the protocol --*/
recv_rest {
[(&i:M:~d.d[i].t & ~d.d[i].f)];v-,a-
}
/*-- probe expression on receiver --*/
// i think this deadlocks with recv_up
recv_probe = v;
// no sender probe
}
}
export defchan avMx1of2 <: gen_avMx1of2<false,0> () { }
export defchan avrMx1of2 <: gen_avMx1of2<true,0> () { }
/**
* the buffer template gives you a standart buffer of bitwidth N
*
*/
export template<pint N>
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; rsp reset; power supply) {
//control
bool _en,_en_X,_preset_X,_sreset_X;
A_3C_RB_X4 inack_ctl(c1=en_X,c2=in.v,c3=out.v,y=in.a,pr_B=_preset_X,sr_B=_sreset_X,vdd=supply.vdd,vss=supply.vss);
A_1C1P_X1 en_ctl(c1=in.a,p1=out.v,y=_en,vdd=supply.vdd,vss=supply.vss);
sigbuf en_buf<N*2>(a=_en, y=_en_X, power=supply);
sigbuf preset_buf<N*2>(a=reset.p,y=preset_X, power=supply);
sigbuf sreset_buf<N*2>(a=reset.s,y=sreset_X, power=supply);
//validity
bool _in_v;
ctree vc<N>(in=in.d,y=_in_v, power=supply);
sigbuf in_v_buf<12>(a=_in_v, y=in.v);
//function
bool _out_a_BX, _out_a_B;
A_2C1N_RB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
INV_X1 out_a_inv(a=out.a,y=_out_a_B);
sigbuf out_a_B_buf<N*2>(a=_out_a_B,y=_out_a_BX);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X;
t_buf_func[i].c1=_en_X;
f_buf_func[i].c2=_out_a_BX;
t_buf_func[i].c2=_out_a_BX;
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].pr_B=_preset_X;
t_buf_func[i].pr_B=_preset_X;
f_buf_func[i].sr_B=_sreset_X;
t_buf_func[i].sr_B=_sreset_X;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
)
}
}
}