62 lines
1.9 KiB
Plaintext
62 lines
1.9 KiB
Plaintext
|
/*************************************************************************
|
||
|
|
*
|
||
|
|
* This file is part of ACT dataflow neuro library.
|
||
|
|
* It's the testing facility for cell_lib_std.act
|
||
|
|
*
|
||
|
|
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||
|
|
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||
|
|
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||
|
|
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||
|
|
*
|
||
|
|
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||
|
|
*
|
||
|
|
* You may redistribute and modify this documentation and make products
|
||
|
|
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||
|
|
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||
|
|
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||
|
|
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||
|
|
* for applicable conditions.
|
||
|
|
*
|
||
|
|
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||
|
|
*
|
||
|
|
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||
|
|
* these sources, You must maintain the Source Location visible in its
|
||
|
|
* documentation.
|
||
|
|
*
|
||
|
|
**************************************************************************
|
||
|
|
*/
|
||
|
|
|
||
|
|
import "../../dataflow_neuro/coders.act";
|
||
|
|
import "../../dataflow_neuro/primitives.act";
|
||
|
|
|
||
|
|
import globals;
|
||
|
|
import std::data;
|
||
|
|
|
||
|
|
open std::data;
|
||
|
|
|
||
|
|
|
||
|
|
open tmpl::dataflow_neuro;
|
||
|
|
|
||
|
|
pint N = 7;
|
||
|
|
pint Nc = std::ceil_log2(N);
|
||
|
|
pint N_BUFFERS = 5;
|
||
|
|
pint N_BD_DLY_CFG = 4;
|
||
|
|
|
||
|
|
defproc _encoder1d_bd (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
|
||
|
|
|
||
|
|
bool _reset_B;
|
||
|
|
prs {
|
||
|
|
Reset => _reset_B-
|
||
|
|
}
|
||
|
|
power supply;
|
||
|
|
supply.vdd = Vdd;
|
||
|
|
supply.vss = GND;
|
||
|
|
encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
|
||
|
|
.reset_B = _reset_B, .supply = supply);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// fifo_decoder_neurons_encoder_fifo e;
|
||
|
|
_encoder1d_bd c;
|