59 lines
2.0 KiB
Plaintext
59 lines
2.0 KiB
Plaintext
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/registers.act";
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import globals;
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import std::data;
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open std::data;
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open tmpl::dataflow_neuro;
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defproc fifo_reg_fifo_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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power supply;
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supply.vdd = Vdd;
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supply.vss = GND;
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fifo<9,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
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// Make a register array with 3 bit address (-> 8 registers),
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// each register holding 5 bits.
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registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
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.reset_B = _reset_B, .supply = supply);
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fifo<8,5> fifo_post(.in = reg.out, .out = out, .reset_B = _reset_B, .supply = supply);
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}
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// fifo_decoder_neurons_encoder_fifo e;
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fifo_reg_fifo_3x5x8 b;
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