actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue_slimreg/split_modules/tmpl_0_0dataflow__neurotexel__core_331_715_76_715_7348_74_73_74_79_74_730_76_760_7348_75_73_75_73_73_72_76_723_78_4/netlist/verilog.v

module tmpl_0_0dataflow__neurotexel__core_331_715_76_715_7348_74_73_74_79_74_730_76_760_7348_75_73_75_73_73_72_76_723_78_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_a , Iout_v , Ireg_data0_d0_d0 , Ireg_data0_d0_d1 , Ireg_data0_d1_d0 , Ireg_data0_d1_d1 , Ireg_data0_d2_d0 , Ireg_data0_d2_d1 , Ireg_data0_d3_d0 , Ireg_data0_d3_d1 , Ireg_data0_d4_d0 , Ireg_data0_d4_d1 , Ireg_data0_d5_d0 , Ireg_data0_d5_d1 , Ireg_data0_d6_d0 , Ireg_data0_d6_d1 , Ireg_data0_d7_d0 , Ireg_data0_d7_d1 , Ireg_data0_d8_d0 , Ireg_data0_d8_d1 , Ireg_data0_d9_d0 , Ireg_data0_d9_d1 , Ireg_data0_d10_d0 , Ireg_data0_d10_d1 , Ireg_data0_d11_d0 , Ireg_data0_d11_d1 , Ireg_data0_d12_d0 , Ireg_data0_d12_d1 , Ireg_data0_d13_d0 , Ireg_data0_d13_d1 , Ireg_data0_d14_d0 , Ireg_data0_d14_d1 , Ireg_data0_d15_d0 , Ireg_data0_d15_d1 , Ireg_data0_d16_d0 , Ireg_data0_d16_d1 , Ireg_data0_d17_d0 , Ireg_data0_d17_d1 , Ireg_data0_d18_d0 , Ireg_data0_d18_d1 , Ireg_data0_d19_d0 , Ireg_data0_d19_d1 , Ireg_data0_d20_d0 , Ireg_data0_d20_d1 , Ireg_data0_d21_d0 , Ireg_data0_d21_d1 , Ireg_data0_d22_d0 , Ireg_data0_d22_d1 , Ireg_data1_d0_d0 , Ireg_data1_d0_d1 , Ireg_data1_d1_d0 , Ireg_data1_d1_d1 , Ireg_data1_d2_d0 , Ireg_data1_d2_d1 , Ireg_data1_d3_d0 , Ireg_data1_d3_d1 , Ireg_data1_d4_d0 , Ireg_data1_d4_d1 , Ireg_data1_d5_d0 , Ireg_data1_d5_d1 , Ireg_data1_d6_d0 , Ireg_data1_d6_d1 , Ireg_data1_d7_d0 , Ireg_data1_d7_d1 , Ireg_data1_d8_d0 , Ireg_data1_d8_d1 , Ireg_data1_d9_d0 , Ireg_data1_d9_d1 , Ireg_data1_d10_d0 , Ireg_data1_d10_d1 , Ireg_data1_d11_d0 , Ireg_data1_d11_d1 , Ireg_data1_d12_d0 , Ireg_data1_d12_d1 , Ireg_data1_d13_d0 , Ireg_data1_d13_d1 , Ireg_data1_d14_d0 , Ireg_data1_d14_d1 , Ireg_data1_d15_d0 , Ireg_data1_d15_d1 , Ireg_data1_d16_d0 , Ireg_data1_d16_d1 , Ireg_data1_d17_d0 , Ireg_data1_d17_d1 , Ireg_data1_d18_d0 , Ireg_data1_d18_d1 , Ireg_data1_d19_d0 , Ireg_data1_d19_d1 , Ireg_data1_d20_d0 , Ireg_data1_d20_d1 , Ireg_data1_d21_d0 , Ireg_data1_d21_d1 , Ireg_data1_d22_d0 , Ireg_data1_d22_d1 , Ireg_data2_d0_d0 , Ireg_data2_d0_d1 , Ireg_data2_d1_d0 , Ireg_data2_d1_d1 , Ireg_data2_d2_d0 , Ireg_data2_d2_d1 , Ireg_data2_d3_d0 , Ireg_data2_d3_d1 , Ireg_data2_d4_d0 , Ireg_data2_d4_d1 , Ireg_data2_d5_d0 , Ireg_data2_d5_d1 , Ireg_data2_d6_d0 , Ireg_data
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   input Iin_d_d5_d0 ;
   input Iin_d_d5_d1 ;
   input Iin_d_d6_d0 ;
   input Iin_d_d6_d1 ;
   input Iin_d_d7_d0 ;
   input Iin_d_d7_d1 ;
   input Iin_d_d8_d0 ;
   input Iin_d_d8_d1 ;
   input Iin_d_d9_d0 ;
   input Iin_d_d9_d1 ;
   input Iin_d_d10_d0 ;
   input Iin_d_d10_d1 ;
   input Iin_d_d11_d0 ;
   input Iin_d_d11_d1 ;
   input Iin_d_d12_d0 ;
   input Iin_d_d12_d1 ;
   input Iin_d_d13_d0 ;
   input Iin_d_d13_d1 ;
   input Iin_d_d14_d0 ;
   input Iin_d_d14_d1 ;
   input Iin_d_d15_d0 ;
   input Iin_d_d15_d1 ;
   input Iin_d_d16_d0 ;
   input Iin_d_d16_d1 ;
   input Iin_d_d17_d0 ;
   input Iin_d_d17_d1 ;
   input Iin_d_d18_d0 ;
   input Iin_d_d18_d1 ;
   input Iin_d_d19_d0 ;
   input Iin_d_d19_d1 ;
   input Iin_d_d20_d0 ;
   input Iin_d_d20_d1 ;
   input Iin_d_d21_d0 ;
   input Iin_d_d21_d1 ;
   input Iin_d_d22_d0 ;
   input Iin_d_d22_d1 ;
   input Iin_d_d23_d0 ;
   input Iin_d_d23_d1 ;
   input Iin_d_d24_d0 ;
   input Iin_d_d24_d1 ;
   input Iin_d_d25_d0 ;
   input Iin_d_d25_d1 ;
   input Iin_d_d26_d0 ;
   input Iin_d_d26_d1 ;
   input Iin_d_d27_d0 ;
   input Iin_d_d27_d1 ;
   input Iin_d_d28_d0 ;
   input Iin_d_d28_d1 ;
   input Iin_d_d29_d0 ;
   input Iin_d_d29_d1 ;
   input Iin_d_d30_d0 ;
   input Iin_d_d30_d1 ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Iout_a ;
   input Iout_v ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Idec_ackB0 ;
   input Idec_ackB1 ;
   input Idec_ackB2 ;
   input Idec_ackB3 ;
   input Idec_ackB4 ;
   input Idec_ackB5 ;
   input Idec_ackB6 ;
   input Idec_ackB7 ;
   input Idec_ackB8 ;
   input Idec_ackB9 ;
   input Idec_ackB10 ;
   input Idec_ackB11 ;
   input Idec_ackB12 ;
   input Idec_ackB13 ;
   input Idec_ackB14 ;
   input Isyn_pu0_d_d0 ;
   
   input Isyn_pu1_d_d0 ;
   
   input Isyn_pu2_d_d0 ;
   
   input Isyn_pu3_d_d0 ;
   
   input Isyn_pu4_d_d0 ;
   
   input Isyn_pu5_d_d0 ;
   
   input Isyn_pu6_d_d0 ;
   
   input Isyn_pu7_d_d0 ;
   
   input Isyn_pu8_d_d0 ;
   
   input Isyn_pu9_d_d0 ;
   
   input Isyn_pu10_d_d0 ;
   
   input Isyn_pu11_d_d0 ;
   
   input Isyn_pu12_d_d0 ;
   
   input Isyn_pu13_d_d0 ;
   
   input Isyn_pu14_d_d0 ;
   
   input Ienc_inx0_d_d0 ;
   
   input Ienc_inx1_d_d0 ;
   
   input Ienc_inx2_d_d0 ;
   
   input Ienc_inx3_d_d0 ;
   
   input Ienc_inx4_d_d0 ;
   
   input Ienc_inx5_d_d0 ;
   
   input Ienc_inx6_d_d0 ;
   
   input Ienc_inx7_d_d0 ;
   
   input Ienc_inx8_d_d0 ;
   
   input Ienc_inx9_d_d0 ;
   
   input Ienc_inx10_d_d0 ;
   
   input Ienc_inx11_d_d0 ;
   
   input Ienc_inx12_d_d0 ;
   
   input Ienc_inx13_d_d0 ;
   
   input Ienc_inx14_d_d0 ;
   
   input Ienc_iny0_d_d0 ;
   
   input Ienc_iny1_d_d0 ;
   
   input Ienc_iny2_d_d0 ;
   
   input Ienc_iny3_d_d0 ;
   
   input Ienc_iny4_d_d0 ;
   
   input Ienc_iny5_d_d0 ;
   
   
   input Inrn_pd_x0_a ;
   
   input Inrn_pd_x1_a ;
   
   input Inrn_pd_x2_a ;
   
   input Inrn_pd_x3_a ;
   
   input Inrn_pd_x4_a ;
   
   input Inrn_pd_x5_a ;
   
   input Inrn_pd_x6_a ;
   
   input Inrn_pd_x7_a ;
   
   input Inrn_pd_x8_a ;
   
   input Inrn_pd_x9_a ;
   
   input Inrn_pd_x10_a ;
   
   input Inrn_pd_x11_a ;
   
   input Inrn_pd_x12_a ;
   
   input Inrn_pd_x13_a ;
   
   input Inrn_pd_x14_a ;
   
   input Inrn_pd_y0_a ;
   
   input Inrn_pd_y1_a ;
   
   input Inrn_pd_y2_a ;
   
   input Inrn_pd_y3_a ;
   
   input Inrn_pd_y4_a ;
   
   input Inrn_pd_y5_a ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Isyn_mon_AMZI0 ;
   input Isyn_mon_AMZI1 ;
   input Isyn_mon_AMZI2 ;
   input Isyn_mon_AMZI3 ;
   input Isyn_mon_AMZI4 ;
   input Isyn_mon_AMZI5 ;
   input Isyn_mon_AMZI6 ;
   input Isyn_mon_AMZI7 ;
   input Isyn_mon_AMZI8 ;
   input Isyn_mon_AMZI9 ;
   input Isyn_mon_AMZI10 ;
   input Isyn_mon_AMZI11 ;
   input Isyn_mon_AMZI12 ;
   input Isyn_mon_AMZI13 ;
   input Isyn_mon_AMZI14 ;
   input Isyn_mon_AMZI15 ;
   input Isyn_mon_AMZI16 ;
   input Isyn_mon_AMZI17 ;
   input Isyn_mon_AMZI18 ;
   input Isyn_mon_AMZI19 ;
   input Isyn_mon_AMZI20 ;
   input Isyn_mon_AMZI21 ;
   input Isyn_mon_AMZI22 ;
   input Isyn_mon_AMZI23 ;
   input Isyn_mon_AMZI24 ;
   input Isyn_mon_AMZI25 ;
   input Isyn_mon_AMZI26 ;
   input Isyn_mon_AMZI27 ;
   input Isyn_mon_AMZI28 ;
   input Isyn_mon_AMZI29 ;
   input Isyn_mon_AMZI30 ;
   input Isyn_mon_AMZI31 ;
   input Isyn_mon_AMZI32 ;
   input Isyn_mon_AMZI33 ;
   input Isyn_mon_AMZI34 ;
   input Isyn_mon_AMZI35 ;
   input Isyn_mon_AMZI36 ;
   input Isyn_mon_AMZI37 ;
   input Isyn_mon_AMZI38 ;
   input Isyn_mon_AMZI39 ;
   input Isyn_mon_AMZI40 ;
   input Isyn_mon_AMZI41 ;
   input Isyn_mon_AMZI42 ;
   input Isyn_mon_AMZI43 ;
   input Isyn_mon_AMZI44 ;
   input Isyn_mon_AMZI45 ;
   input Isyn_mon_AMZI46 ;
   input Isyn_mon_AMZI47 ;
   input Isyn_mon_AMZI48 ;
   input Isyn_mon_AMZI49 ;
   input Isyn_mon_AMZI50 ;
   input Isyn_mon_AMZI51 ;
   input Isyn_mon_AMZI52 ;
   input Isyn_mon_AMZI53 ;
   input Isyn_mon_AMZI54 ;
   input Isyn_mon_AMZI55 ;
   input Isyn_mon_AMZI56 ;
   input Isyn_mon_AMZI57 ;
   input Isyn_mon_AMZI58 ;
   input Isyn_mon_AMZI59 ;
   input Isyn_mon_AMZI60 ;
   input Isyn_mon_AMZI61 ;
   input Isyn_mon_AMZI62 ;
   input Isyn_mon_AMZI63 ;
   input Isyn_mon_AMZI64 ;
   input Isyn_mon_AMZI65 ;
   input Isyn_mon_AMZI66 ;
   input Isyn_mon_AMZI67 ;
   input Isyn_mon_AMZI68 ;
   input Isyn_mon_AMZI69 ;
   input Isyn_mon_AMZI70 ;
   input Isyn_mon_AMZI71 ;
   input Isyn_mon_AMZI72 ;
   input Isyn_mon_AMZI73 ;
   input Isyn_mon_AMZI74 ;
   input Inrn_mon_AMZI0 ;
   input Inrn_mon_AMZI1 ;
   input Inrn_mon_AMZI2 ;
   input Inrn_mon_AMZI3 ;
   input Inrn_mon_AMZI4 ;
   input Inrn_mon_AMZI5 ;
   input Inrn_mon_AMZI6 ;
   input Inrn_mon_AMZI7 ;
   input Inrn_mon_AMZI8 ;
   input Inrn_mon_AMZI9 ;
   input Inrn_mon_AMZI10 ;
   input Inrn_mon_AMZI11 ;
   input Inrn_mon_AMZI12 ;
   input Inrn_mon_AMZI13 ;
   input Inrn_mon_AMZI14 ;
   input Inrn_mon_AMZI15 ;
   input Inrn_mon_AMZI16 ;
   input Inrn_mon_AMZI17 ;
   input Inrn_mon_AMZI18 ;
   input Inrn_mon_AMZI19 ;
   input Inrn_mon_AMZI20 ;
   input Inrn_mon_AMZI21 ;
   input Inrn_mon_AMZI22 ;
   input Inrn_mon_AMZI23 ;
   input Inrn_mon_AMZI24 ;
   input Inrn_mon_AMZI25 ;
   input Inrn_mon_AMZI26 ;
   input Inrn_mon_AMZI27 ;
   input Inrn_mon_AMZI28 ;
   input Inrn_mon_AMZI29 ;
   input Inrn_mon_AMZI30 ;
   input Inrn_mon_AMZI31 ;
   input Inrn_mon_AMZI32 ;
   input Inrn_mon_AMZI33 ;
   input Inrn_mon_AMZI34 ;
   input Inrn_mon_AMZI35 ;
   input Inrn_mon_AMZI36 ;
   input Inrn_mon_AMZI37 ;
   input Inrn_mon_AMZI38 ;
   input Inrn_mon_AMZI39 ;
   input Inrn_mon_AMZI40 ;
   input Inrn_mon_AMZI41 ;
   input Inrn_mon_AMZI42 ;
   input Inrn_mon_AMZI43 ;
   input Inrn_mon_AMZI44 ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Isupply_vdd ;
   input Isupply_vss ;
   input reset_B;
   input reset_reg_B;
   input reset_syn_stge_BI;
   
   
   
   

// -- signals ---
   output Idec_req_y315 ;
   output Isyn_pu7_a ;
   output Ireg_data2_d12_d1 ;
   output Inrn_mon_x4 ;
   wire Isyn_mon_dec_y_out40 ;
   wire Iappend_enc_in_d_d6_d0 ;
   output Idec_req_y220 ;
   output Idec_req_y317 ;
   output Ireg_data6_d1_d0 ;
   wire Iin_d_d20_d0 ;
   output Isyn_mon_y73 ;
   output Ireg_data0_d17_d1 ;
   wire Inrn_mon_AMZI44 ;
   wire I_demux_in_d_d21_d1 ;
   output Idec_req_y271 ;
   wire Iappend_reg_in_d_d16_d0 ;
   output Idec_req_y282 ;
   wire Idec_ackB8 ;
   wire Iin_d_d3_d0 ;
   output Isyn_mon_y158 ;
   wire I_demux_in_d_d22_d0 ;
   output Idec_req_y125 ;
   wire Isyn_mon_dec_y_out106 ;
   wire Isyn_mon_dec_y_out332 ;
   wire Isyn_mon_dec_y_out338 ;
   wire Iregister_in_d_d29_d0 ;
   wire I_demux_out2_d_d16_d0 ;
   wire Iregister_in_d_d7_d1 ;
   wire Iregister_in_d_d23_d1 ;
   wire Isyn_mon_dec_y_out51 ;
   output Ireg_data4_d17_d1 ;
   wire Isyn_mon_dec_y_out204 ;
   wire Isyn_mon_dec_x_out7 ;
   output Ireg_data1_d11_d1 ;
   output Ireg_data2_d12_d0 ;
   wire Isyn_mon_dec_y_out181 ;
   wire Isyn_mon_dec_y_out260 ;
   output Isyn_mon_y240 ;
   wire Ififo_out_in_d_d11_d0 ;
   wire I_demux_out1_d_d13_d1 ;
   output Idec_req_y192 ;
   wire Isyn_mon_AMZI51 ;
   wire Iregister_in_d_d12_d0 ;
   output Ireg_data3_d13_d1 ;
   output Isyn_mon_y133 ;
   wire Ififo_out_in_d_d22_d1 ;
   wire Iappend_reg_in_d_d25_d1 ;
   wire Inrn_mon_AMZI18 ;
   wire Isyn_mon_dec_y_out331 ;
   wire Iands_devmon9_a ;
   wire I_demux_in_d_d17_d0 ;
   output Isyn_mon_x19 ;
   output Idec_req_y35 ;
   wire Isyn_pu2_d_d0 ;
   wire Inrn_mon_AMZI28 ;
   wire Isyn_mon_dec_y_out64 ;
   output Isyn_mon_y81 ;
   wire Inrn_mon_dec_x_out16 ;
   output Idec_req_y32 ;
   output Idec_req_y288 ;
   output Iout_d_d29_d1 ;
   output Ireg_data1_d15_d0 ;
   wire Ienc_inx6_d_d0 ;
   wire Isyn_mon_dec_x_out39 ;
   wire Iregister_in_d_d25_d1 ;
   output Ireg_data5_d18_d0 ;
   wire Iands_devmon0_y ;
   output Idec_req_y248 ;
   wire Isyn_mon_dec_y_out188 ;
   output Isyn_mon_y85 ;
   wire Isyn_mon_dec_y_out53 ;
   wire Isyn_mon_dec_y_out251 ;
   wire Irsb_nrn_storage_in ;
   wire Iappend_enc_in_d_d5_d0 ;
   output Ireg_data1_d19_d0 ;
   output Ireg_data2_d20_d1 ;
   output Isyn_mon_y66 ;
   wire I_demux_out2_d_d22_d0 ;
   wire Isyn_mon_dec_x_out32 ;
   wire Isyn_mon_dec_y_out32 ;
   output Idec_req_y153 ;
   wire Isyn_mon_AMZI4 ;
   wire Iin_d_d2_d0 ;
   wire I_demux_out2_d_d16_d1 ;
   output Ireg_data4_d6_d0 ;
   wire Iappend_reg_in_d_d22_d1 ;
   wire Iappend_enc_in_d_d4_d0 ;
   wire Isyn_mon_dec_y_out4 ;
   output Isyn_mon_y95 ;
   output Ireg_data1_d21_d1 ;
   output Ireg_data6_d15_d1 ;
   wire Isyn_mon_dec_y_out293 ;
   output Isyn_mon_y142 ;
   wire I_demux_out2_d_d2_d0 ;
   wire I_demux_in_d_d11_d1 ;
   output Isyn_mon_y315 ;
   wire I_demux_out2_d_d9_d0 ;
   output Ireg_data1_d1_d0 ;
   output Isyn_mon_x27 ;
   wire Isyn_mon_AMZI61 ;
   wire Isyn_mon_AMZI60 ;
   wire Isyn_AMZO_keeps4_y ;
   output Inrn_flags_EFO2 ;
   output Isyn_mon_x46 ;
   output Idec_req_y201 ;
   output Idec_req_y52 ;
   wire Iin_d_d19_d0 ;
   wire Isyn_mon_AMZI71 ;
   wire Isyn_mon_dec_y_out227 ;
   output Isyn_mon_y67 ;
   wire I_demux_out1_d_d5_d0 ;
   output Isyn_mon_x6 ;
   output Ireg_data5_d3_d0 ;
   wire Iregister_out_d_d12_d1 ;
   wire Isyn_mon_dec_y_out133 ;
   output Iout_d_d16_d1 ;
   wire I_demux_out1_d_d6_d1 ;
   output Idec_req_y31 ;
   output Ireg_data3_d17_d0 ;
   output Ireg_data4_d12_d1 ;
   wire Isyn_mon_dec_y_out263 ;
   output Idec_req_y269 ;
   wire Isyn_mon_dec_y_out140 ;
   output Inrn_pd_x6_d_d0 ;
   wire Iappend_enc_out_d_d14_d1 ;
   wire Isyn_mon_AMZI74 ;
   wire Isyn_mon_dec_y_out43 ;
   wire Isyn_mon_dec_y_out102 ;
   output Inrn_mon_x23 ;
   output Isyn_mon_y241 ;
   output Idec_req_y42 ;
   wire Iappend_reg_in_d_d16_d1 ;
   wire Iin_d_d26_d1 ;
   wire Iregister_in_d_d28_d0 ;
   wire Inrn_mon_dec_y_out2 ;
   output Idec_req_y287 ;
   wire I_demux_out1_d_d8_d1 ;
   wire Iappend_enc_in_d_d6_d1 ;
   output Isyn_mon_x33 ;
   wire Isyn_mon_dec_y_out326 ;
   wire Iregister_in_d_d24_d1 ;
   output Isyn_mon_y56 ;
   wire Isyn_mon_dec_x_out42 ;
   wire Idecoder_in_d_d10_d0 ;
   output Ireg_data1_d0_d1 ;
   output Idec_req_y274 ;
   wire Iappend_reg_in_d_d11_d1 ;
   output Isyn_mon_y48 ;
   wire I_demux_out1_d_d22_d0 ;
   wire Iregister_in_d_d17_d0 ;
   wire Isyn_mon_dec_x_out27 ;
   wire I_demux_out2_d_d29_d0 ;
   output Idec_req_y300 ;
   wire Idec_ackB0 ;
   output Ireg_data7_d5_d1 ;
   wire Isyn_mon_dec_y_out87 ;
   output Ireg_data3_d9_d0 ;
   output Isyn_mon_y329 ;
   wire Inrn_mon_dec_x_out18 ;
   output Idec_req_y302 ;
   wire Isyn_mon_dec_y_out317 ;
   output Ienc_inx14_a ;
   output Inrn_mon_AMZO0 ;
   wire Isyn_mon_AMZI58 ;
   output Idec_req_y171 ;
   wire Inrn_pd_x7_a ;
   output Idec_req_y215 ;
   output Ireg_data7_d15_d0 ;
   wire Isyn_mon_dec_y_out219 ;
   output Idec_req_y126 ;
   wire I_demux_out2_d_d1_d0 ;
   output Isyn_mon_x35 ;
   wire Idecoder_in_d_d8_d1 ;
   wire Iregister_in_d_d10_d0 ;
   output Ireg_data7_d13_d0 ;
   wire Iappend_enc_in_a ;
   output Idec_req_y109 ;
   output Isyn_mon_y50 ;
   wire Inrn_mon_dec_x_out25 ;
   wire Isyn_mon_dec_x_out52 ;
   output Idec_req_y170 ;
   wire Iregister_out_d_d17_d0 ;
   output Isyn_mon_y196 ;
   output Ireg_data1_d17_d1 ;
   output Ireg_data2_d13_d1 ;
   wire Iappend_reg_in_d_d18_d1 ;
   wire Iregister_out_d_d20_d1 ;
   wire I_demux_out2_a ;
   output Idec_req_y183 ;
   output Idec_req_y256 ;
   output Ireg_data3_d15_d0 ;
   wire Isyn_mon_dec_y_out95 ;
   output Isyn_mon_y223 ;
   output Isyn_mon_y114 ;
   output Iout_d_d17_d0 ;
   wire Iencoder_out_d_d4_d0 ;
   output Inrn_pd_x14_d_d0 ;
   output Ireg_data3_d8_d1 ;
   output Idec_req_y264 ;
   output Ireg_data7_d11_d0 ;
   wire Isyn_mon_dec_y_out333 ;
   output Isyn_mon_y136 ;
   output Idec_req_y335 ;
   output Ireg_data7_d14_d0 ;
   wire Iencoder_out_a ;
   wire Isyn_mon_dec_x_out43 ;
   wire Isyn_mon_AMZI26 ;
   wire Isyn_mon_dec_y_out212 ;
   output Isyn_mon_y266 ;
   wire I_demux_out2_d_d12_d1 ;
   output Isyn_mon_y278 ;
   output Iout_d_d0_d0 ;
   wire Inrn_mon_dec_x_out2 ;
   wire Isyn_mon_dec_x_out16 ;
   output Idec_req_y286 ;
   wire Iin_d_d7_d0 ;
   wire Isyn_mon_dec_y_out310 ;
   output Isyn_mon_x23 ;
   wire Iappend_reg_in_d_d2_d1 ;
   wire Iencoder_out_d_d3_d0 ;
   output Ireg_data5_d11_d0 ;
   wire Idecoder_in_d_d7_d0 ;
   wire Inrn_mon_AMZI1 ;
   wire Isyn_mon_dec_y_out100 ;
   output Idec_req_y18 ;
   output Ireg_data0_d13_d0 ;
   output Ireg_data3_d21_d0 ;
   output Isyn_mon_y173 ;
   wire Ififo_out_in_d_d6_d0 ;
   output Idec_req_y36 ;
   output Ireg_data5_d20_d0 ;
   wire Isyn_mon_dec_y_out217 ;
   wire I_demux_in_d_d16_d1 ;
   wire Isyn_mon_dec_y_out346 ;
   wire Ififo_out_in_d_d21_d1 ;
   wire Inrn_mon_dec_x_out8 ;
   wire Isyn_mon_AMZI73 ;
   output Idec_req_y37 ;
   wire Ienc_iny3_d_d0 ;
   output Isyn_mon_y101 ;
   wire Isyn_mon_dec_y_out299 ;
   wire I_demux_out2_d_d25_d0 ;
   wire Isyn_mon_x_buf_in27 ;
   wire Isyn_mon_AMZI10 ;
   output Isyn_mon_y236 ;
   output Ireg_data3_d18_d1 ;
   wire Isyn_mon_dec_y_out162 ;
   output Iout_d_d30_d0 ;
   wire Iencoder_out_d_d5_d1 ;
   wire I_demux_out2_d_d26_d1 ;
   wire I_demux_out1_d_d27_d0 ;
   wire Iappend_enc_in_d_d1_d0 ;
   output Ireg_data0_d16_d1 ;
   wire Isyn_mon_dec_y_out201 ;
   wire Inrn_pd_y3_a ;
   wire Isyn_mon_dec_y_out329 ;
   output Isyn_mon_y109 ;
   output Ireset_nrn_hs_BO0 ;
   output Isyn_mon_y341 ;
   output Iout_d_d1_d1 ;
   output Ireg_data2_d18_d1 ;
   wire Iregister_out_d_d25_d0 ;
   wire Isyn_pu3_d_d0 ;
   output Ireg_data5_d8_d1 ;
   output Idec_req_y311 ;
   wire Isyn_mon_AMZI44 ;
   output Ireg_data1_d3_d1 ;
   output Isyn_mon_y2 ;
   wire Iappend_enc_out_d_d16_d1 ;
   output Idec_req_y58 ;
   output Isyn_mon_y317 ;
   output Idec_req_y118 ;
   output Isyn_mon_y308 ;
   output Isyn_mon_y31 ;
   output Iout_d_d7_d1 ;
   wire Isyn_mon_dec_y_out208 ;
   output Idec_req_y65 ;
   output Iout_d_d13_d0 ;
   output Ienc_iny0_a ;
   output Isyn_mon_y63 ;
   output Inrn_pd_x11_d_d0 ;
   wire Inrn_pd_x10_a ;
   output Isyn_mon_y149 ;
   output Idec_req_y333 ;
   output Isyn_mon_y125 ;
   output Ireg_data2_d4_d1 ;
   wire Isyn_mon_dec_y_out63 ;
   output Ireg_data4_d18_d1 ;
   wire I_demux_out2_d_d27_d0 ;
   output Idec_req_y80 ;
   wire Inrn_AMZO_keeps1_y ;
   output Ireg_data0_d4_d0 ;
   output Isyn_mon_y88 ;
   output Iout_d_d17_d1 ;
   wire I_demux_out2_d_d26_d0 ;
   output Ireg_data1_d18_d0 ;
   wire Iappend_enc_in_d_d0_d0 ;
   wire Inrn_mon_AMZI12 ;
   wire I_demux_out1_d_d0_d0 ;
   output Isyn_pu9_a ;
   wire Isyn_mon_dec_y_out223 ;
   wire Isyn_mon_dec_y_out291 ;
   wire I_demux_in_a ;
   output Ireg_data5_d17_d1 ;
   output Ireg_data6_d17_d1 ;
   wire Inrn_mon_AMZI43 ;
   output Isyn_mon_y75 ;
   output Iout_d_d26_d0 ;
   wire Iands_devmon0_a ;
   wire Isyn_mon_dec_x_out22 ;
   wire Inrn_mon_AMZI13 ;
   wire Isyn_mon_dec_y_out42 ;
   output Ireg_data0_d22_d0 ;
   wire Isyn_mon_dec_y_out303 ;
   output Ienc_iny1_a ;
   output Ireg_data0_d5_d1 ;
   wire Iin_d_d7_d1 ;
   output Isyn_mon_y306 ;
   output Isyn_mon_AMZO0 ;
   wire Isyn_mon_dec_x_out35 ;
   wire I_demux_in_d_d12_d0 ;
   output Inrn_mon_x6 ;
   wire Iappend_reg_in_d_d27_d1 ;
   output Isyn_mon_y86 ;
   wire Isyn_mon_dec_x_out47 ;
   output Isyn_pu5_a ;
   wire Isyn_mon_dec_y_out10 ;
   wire Isyn_mon_dec_y_out225 ;
   output Iout_d_d15_d0 ;
   output Idec_req_y34 ;
   output Ireg_data7_d7_d0 ;
   output Isyn_mon_y190 ;
   output Ireg_data4_d15_d0 ;
   wire Iin_d_d1_d0 ;
   wire I_demux_out2_d_d28_d0 ;
   output Idec_req_y119 ;
   output Idec_req_x2 ;
   output Ireg_data5_d21_d1 ;
   output Ireg_data7_d18_d1 ;
   wire Isyn_mon_dec_y_out108 ;
   wire Inrn_pd_x1_a ;
   wire I_demux_in_d_d16_d0 ;
   output Ireg_data4_d11_d1 ;
   wire Isyn_mon_dec_y_out232 ;
   wire Isyn_mon_dec_y_out307 ;
   wire Isyn_mon_AMZI67 ;
   wire Iregister_in_d_d10_d1 ;
   wire Iappend_reg_in_d_d15_d1 ;
   wire Isyn_mon_AMZI68 ;
   output Isyn_pu6_a ;
   wire Iregister_out_d_d8_d0 ;
   output Idec_req_y149 ;
   output Ireg_data5_d4_d0 ;
   wire Isyn_mon_dec_y_out3 ;
   wire I_demux_out2_d_d6_d1 ;
   wire Isyn_pu12_d_d0 ;
   wire Isyn_mon_dec_y_out155 ;
   output Inrn_mon_x16 ;
   output Idec_req_y252 ;
   output Isyn_mon_y25 ;
   wire Inrn_mon_dec_x_out17 ;
   output Idec_req_y115 ;
   output Idec_req_y331 ;
   wire Isyn_mon_dec_y_out16 ;
   output Inrn_pd_x10_d_d0 ;
   wire I_demux_out1_d_d23_d0 ;
   output Inrn_mon_x21 ;
   wire Isyn_mon_AMZI19 ;
   output Isyn_mon_x28 ;
   wire Iregister_out_d_d7_d0 ;
   output Isyn_mon_y302 ;
   output Isyn_mon_y98 ;
   output Ireg_data2_d5_d0 ;
   output Idec_req_y74 ;
   wire Iregister_in_d_d4_d0 ;
   wire Iin_d_d3_d1 ;
   output Isyn_mon_y226 ;
   wire Isyn_mon_dec_y_out248 ;
   output Isyn_mon_y17 ;
   wire Inrn_pd_x4_a ;
   wire Isyn_mon_dec_x_out44 ;
   wire Isyn_mon_AMZI38 ;
   wire Iregister_in_d_d9_d0 ;
   output Ireg_data5_d21_d0 ;
   wire I_demux_out1_d_d21_d1 ;
   wire I_demux_out2_d_d7_d1 ;
   output Idec_req_y4 ;
   output Ireg_data6_d15_d0 ;
   wire Isyn_mon_dec_y_out91 ;
   wire Isyn_mon_dec_y_out253 ;
   output Isyn_mon_y284 ;
   output Isyn_mon_y199 ;
   output Inrn_mon_AMZO2 ;
   output Idec_req_y124 ;
   output Isyn_mon_y269 ;
   output Inrn_pd_y1_d_d0 ;
   output Idec_req_y73 ;
   wire Isyn_mon_AMZI15 ;
   output Ireg_data5_d12_d0 ;
   output Iout_d_d7_d0 ;
   wire Ififo_out_in_d_d6_d1 ;
   wire I_demux_out1_d_d17_d1 ;
   output Ireg_data7_d6_d1 ;
   output Isyn_mon_y21 ;
   wire I_demux_in_d_d23_d1 ;
   output Idec_req_y284 ;
   wire Idec_ackB14 ;
   output Ireg_data2_d0_d1 ;
   output Ireg_data4_d9_d1 ;
   output Isyn_mon_y335 ;
   wire I_demux_out2_d_d8_d1 ;
   wire Isyn_mon_dec_x_out40 ;
   output Idec_req_y63 ;
   wire Isyn_mon_dec_x_out19 ;
   output Idec_req_x4 ;
   output Idec_req_y325 ;
   wire Isyn_pu9_d_d0 ;
   wire Iregister_out_d_d16_d0 ;
   wire Isyn_mon_dec_x_out59 ;
   wire Isyn_mon_AMZI52 ;
   wire Isyn_mon_dec_y_out132 ;
   wire Iencoder_out_d_d0_d1 ;
   wire I_demux_out1_d_d14_d1 ;
   output Ireg_data1_d10_d1 ;
   output Isyn_mon_y235 ;
   output Idec_req_y27 ;
   output Ireg_data4_d5_d0 ;
   output Isyn_mon_y116 ;
   wire Iands_devmon5_a ;
   output Inrn_mon_y1 ;
   output Ireg_data4_d17_d0 ;
   wire Iregister_out_d_d21_d0 ;
   output Isyn_mon_y201 ;
   wire Isyn_mon_dec_y_out167 ;
   output Idec_req_y49 ;
   wire Isyn_mon_dec_y_out82 ;
   wire Iin_d_d18_d1 ;
   wire Isyn_mon_dec_x_out55 ;
   wire Iappend_enc_out_d_d13_d1 ;
   output Ireg_data5_d5_d1 ;
   output Iout_d_d21_d0 ;
   wire Isyn_mon_dec_y_out277 ;
   wire Isyn_pu11_d_d0 ;
   output Ireg_data2_d11_d0 ;
   wire Isyn_mon_dec_y_out278 ;
   output Isyn_mon_y162 ;
   output Ireg_data2_d3_d1 ;
   wire Isyn_mon_dec_y_out166 ;
   wire Isyn_mon_dec_y_out320 ;
   wire Iregister_out_d_d12_d0 ;
   wire Iands_devmon11_y ;
   output Ienc_inx10_a ;
   wire I_demux_out2_d_d25_d1 ;
   wire Isyn_mon_dec_x_out6 ;
   wire Inrn_mon_AMZI36 ;
   output Idec_req_y176 ;
   wire Iregister_out_d_d20_d0 ;
   output Inrn_mon_x11 ;
   output Idec_req_y306 ;
   output Isyn_mon_y200 ;
   output Isyn_mon_y104 ;
   wire Isyn_mon_dec_y_out246 ;
   output Ienc_inx2_a ;
   output Idec_req_y56 ;
   wire Iregister_out_d_d19_d0 ;
   output Isyn_mon_x30 ;
   wire Isyn_mon_dec_x_out8 ;
   output Isyn_mon_y221 ;
   output Iout_d_d16_d0 ;
   wire Iappend_reg_in_d_d4_d1 ;
   output Isyn_mon_y34 ;
   wire Ififo_out_in_d_d30_d1 ;
   wire Idecoder_in_d_d1_d0 ;
   wire Isyn_mon_x_buf_in11 ;
   wire Isyn_mon_AMZI65 ;
   output Idec_req_y285 ;
   wire Isyn_mon_AMZI42 ;
   output Ireg_data6_d21_d1 ;
   output Ireg_data0_d3_d0 ;
   output Ireg_data1_d12_d0 ;
   wire Isyn_mon_dec_y_out84 ;
   wire Ienc_inx11_d_d0 ;
   wire Iin_d_d1_d1 ;
   wire Iin_d_d18_d0 ;
   wire Isyn_mon_dec_y_out14 ;
   wire Isyn_mon_dec_y_out134 ;
   output Ireg_data0_d4_d1 ;
   wire Isyn_mon_dec_x_out18 ;
   wire Iappend_reg_in_d_d26_d0 ;
   wire Isyn_mon_dec_y_out273 ;
   output Idec_req_y322 ;
   output Ireg_data2_d1_d0 ;
   wire Iappend_reg_in_d_d20_d0 ;
   wire Ienc_iny5_d_d0 ;
   output Isyn_mon_y296 ;
   output Isyn_mon_y145 ;
   output Isyn_mon_x26 ;
   output Ireg_data4_d16_d1 ;
   output Isyn_mon_y79 ;
   wire Inrn_mon_AMZI15 ;
   wire Isyn_mon_dec_y_out131 ;
   wire I_demux_in_d_d9_d1 ;
   output Idec_req_y141 ;
   wire Isyn_mon_AMZI37 ;
   wire I_demux_in_d_d1_d0 ;
   output Idec_req_y122 ;
   output Ireg_data4_d6_d1 ;
   wire Isyn_mon_dec_y_out160 ;
   wire Isyn_mon_dec_y_out289 ;
   output Idec_req_y96 ;
   wire Isyn_pu14_d_d0 ;
   wire Inrn_mon_AMZI19 ;
   wire I_demux_out2_d_d17_d0 ;
   wire Iregister_in_d_d13_d1 ;
   output Ireg_data0_d7_d0 ;
   output Idec_req_y270 ;
   wire Isyn_mon_dec_y_out298 ;
   wire Ififo_out_in_d_d9_d0 ;
   output Ireg_data6_d13_d1 ;
   output Isyn_mon_y38 ;
   wire I_demux_out1_d_d20_d0 ;
   wire I_demux_out1_d_d6_d0 ;
   output Idec_req_y90 ;
   wire Idecoder_in_d_d6_d0 ;
   output Ireg_data5_d15_d0 ;
   wire Isupply_vdd ;
   output Idec_req_y61 ;
   output Idec_req_y345 ;
   output Isyn_mon_y331 ;
   output Inrn_pd_y4_d_d0 ;
   output Idec_req_y316 ;
   output Ireg_data7_d17_d0 ;
   output Inrn_mon_x7 ;
   wire Iregister_out_d_d10_d0 ;
   output Isyn_mon_y246 ;
   wire Isyn_pu13_d_d0 ;
   wire Isyn_mon_dec_y_out15 ;
   output Isyn_mon_y160 ;
   output Ireg_data7_d5_d0 ;
   wire Isyn_mon_dec_x_out11 ;
   output Idec_req_y276 ;
   output Ireg_data7_d22_d1 ;
   output Isyn_mon_y123 ;
   output Iout_d_d27_d1 ;
   wire Isyn_mon_dec_x_out26 ;
   output Isyn_mon_x50 ;
   output Idec_req_y228 ;
   output Ireg_data6_d11_d1 ;
   wire Iappend_reg_in_d_d11_d0 ;
   output Isyn_mon_y87 ;
   output Idec_req_y186 ;
   output Idec_req_x8 ;
   output Idec_req_y338 ;
   wire Isyn_mon_dec_y_out23 ;
   wire Isyn_mon_dec_y_out258 ;
   wire Iands_devmon4_a ;
   output Idec_req_y95 ;
   output Idec_req_y303 ;
   output Ireg_data1_d16_d1 ;
   output Ireg_data3_d16_d0 ;
   output Ireg_data7_d22_d0 ;
   wire Inrn_mon_AMZI4 ;
   wire Isyn_mon_dec_y_out176 ;
   output Isyn_mon_y243 ;
   wire Iregister_out_d_d9_d0 ;
   output Ireg_data0_d3_d1 ;
   wire Inrn_mon_AMZI40 ;
   output Isyn_mon_y112 ;
   wire Isyn_mon_AMZI23 ;
   wire Isyn_mon_dec_y_out238 ;
   wire Isyn_mon_dec_y_out139 ;
   wire Ienc_inx10_d_d0 ;
   wire Isyn_mon_dec_y_out173 ;
   wire Ienc_iny0_d_d0 ;
   wire I_demux_out1_d_d7_d1 ;
   wire Iin_d_d22_d1 ;
   wire Isyn_mon_dec_y_out192 ;
   output Iout_d_d22_d0 ;
   wire Isyn_mon_dec_y_out21 ;
   output Isyn_mon_y183 ;
   output Isyn_mon_y40 ;
   wire Isyn_mon_AMZI30 ;
   wire Iappend_reg_in_v ;
   output Inrn_mon_x17 ;
   output Isyn_mon_y214 ;
   wire Ififo_out_in_d_d26_d0 ;
   wire I_demux_in_d_d14_d0 ;
   wire Iregister_out_d_d2_d1 ;
   output Isyn_mon_y188 ;
   output Inrn_flags_EFO1 ;
   wire Ififo_out_in_d_d18_d0 ;
   wire I_demux_out2_d_d5_d1 ;
   output Ireg_data2_d2_d1 ;
   output Isyn_mon_y184 ;
   output Idec_req_y217 ;
   wire Inrn_mon_dec_x_out28 ;
   output Isyn_mon_y51 ;
   output Idec_req_y30 ;
   output Ireg_data6_d18_d0 ;
   wire Iregister_out_d_d0_d1 ;
   wire Iregister_out_d_d3_d1 ;
   wire Iregister_out_d_d4_d1 ;
   wire Ififo_out_in_d_d23_d0 ;
   wire Isyn_mon_dec_y_out20 ;
   output Isyn_mon_y78 ;
   output Ireg_data2_d6_d0 ;
   wire Iin_d_d19_d1 ;
   output Isyn_mon_x0 ;
   wire Iands_devmon7_y ;
   output Isyn_mon_y273 ;
   output Isyn_mon_y46 ;
   output Inrn_mon_x3 ;
   wire I_demux_out2_d_d18_d1 ;
   output Isyn_mon_y43 ;
   wire Iregister_in_d_d26_d0 ;
   wire Idec_ackB3 ;
   wire Isyn_mon_dec_y_out24 ;
   output Isyn_mon_y286 ;
   wire Iregister_in_d_d22_d0 ;
   output Ireg_data4_d19_d0 ;
   wire Isyn_mon_dec_y_out104 ;
   output Iout_d_d10_d1 ;
   wire Isyn_mon_AMZI57 ;
   wire Iappend_reg_in_d_d21_d1 ;
   output Isyn_mon_x13 ;
   output Isyn_mon_y4 ;
   wire Iappend_enc_in_d_d0_d1 ;
   wire Isyn_mon_dec_y_out324 ;
   output Isyn_mon_y161 ;
   wire I_demux_out1_d_d9_d0 ;
   output Idec_req_y213 ;
   output Inrn_pd_y5_d_d0 ;
   output Inrn_mon_x18 ;
   wire Isyn_mon_dec_x_out58 ;
   output Idec_req_y258 ;
   wire Isyn_mon_AMZI53 ;
   wire Iregister_in_d_d20_d0 ;
   wire Isyn_mon_dec_y_out182 ;
   wire I_demux_in_d_d20_d0 ;
   wire Inrn_mon_dec_x_out12 ;
   output Idec_req_y292 ;
   output Isyn_mon_y52 ;
   wire Iencoder_out_d_d1_d1 ;
   output Idec_req_y127 ;
   wire Iin_d_d5_d1 ;
   wire Inrn_pd_y2_a ;
   wire Isyn_mon_dec_y_out177 ;
   wire Iands_devmon6_y ;
   wire Isyn_mon_dec_y_out77 ;
   output Isyn_mon_y232 ;
   output Ireg_data6_d12_d1 ;
   wire Ienc_inx0_d_d0 ;
   wire Isyn_mon_dec_x_out3 ;
   wire Isyn_mon_dec_y_out235 ;
   output Ireg_data7_d11_d1 ;
   wire Idecoder_in_d_d3_d1 ;
   output Idec_req_y321 ;
   output Iout_d_d2_d1 ;
   wire Idecoder_in_d_d7_d1 ;
   wire Isyn_mon_dec_y_out30 ;
   wire Isyn_mon_dec_y_out221 ;
   output Idec_req_y121 ;
   wire I_demux_out1_d_d18_d1 ;
   output Idec_req_y138 ;
   output Isyn_mon_y191 ;
   wire I_demux_in_d_d19_d0 ;
   output Ireg_data3_d15_d1 ;
   output Ireg_data4_d14_d0 ;
   output Ireg_data5_d19_d1 ;
   wire Isyn_mon_dec_y_out27 ;
   wire Iencoder_out_d_d0_d0 ;
   output Idec_req_y206 ;
   wire Isyn_mon_dec_y_out37 ;
   wire Isyn_mon_dec_y_out99 ;
   output Isyn_mon_y59 ;
   wire Iappend_enc_out_d_d20_d1 ;
   wire Isyn_mon_dec_y_out257 ;
   wire I_demux_out2_d_d10_d0 ;
   wire Inrn_mon_dec_x_out3 ;
   wire Iin_d_d8_d1 ;
   wire Isyn_mon_dec_y_out229 ;
   wire I_demux_out1_d_d2_d0 ;
   output Idec_req_y247 ;
   output Isyn_mon_y192 ;
   output Ireg_data0_d10_d0 ;
   wire Isyn_mon_AMZI36 ;
   output Ireg_data0_d6_d1 ;
   wire Inrn_mon_dec_x_out6 ;
   wire Isyn_mon_dec_y_out126 ;
   output Isyn_mon_y263 ;
   output Inrn_pd_x7_d_d0 ;
   wire I_demux_out2_d_d29_d1 ;
   wire Inrn_pd_x14_a ;
   output Ireg_data1_d13_d1 ;
   output Isyn_mon_y276 ;
   output Isyn_mon_y185 ;
   output Isyn_mon_y156 ;
   output Isyn_mon_y16 ;
   wire Ififo_out_in_d_d7_d0 ;
   wire Iands_devmon6_a ;
   wire I_demux_out1_d_d21_d0 ;
   wire I_demux_out1_d_d8_d0 ;
   wire I_demux_in_d_d3_d0 ;
   output Idec_req_y26 ;
   wire Ififo_out_in_d_d15_d1 ;
   wire Iregister_out_d_d27_d0 ;
   wire Isyn_mon_dec_y_out39 ;
   output Isyn_mon_y49 ;
   output Ireg_data0_d19_d0 ;
   output Ireg_data7_d10_d1 ;
   wire Ififo_out_in_d_d14_d1 ;
   output Idec_req_y146 ;
   output Ireg_data4_d14_d1 ;
   output Inrn_pd_x3_d_d0 ;
   wire Inrn_mon_dec_y_out3 ;
   wire Isyn_mon_dec_y_out123 ;
   wire I_demux_out1_d_d12_d0 ;
   output Isyn_mon_x29 ;
   output Idec_req_y10 ;
   output Idec_req_y244 ;
   output Ireg_data7_d21_d0 ;
   wire Iappend_reg_in_d_d5_d0 ;
   output Ireg_data5_d1_d1 ;
   wire Ififo_out_in_d_d17_d0 ;
   output Isyn_mon_y230 ;
   output Isyn_mon_y181 ;
   output Idec_req_y158 ;
   wire Isyn_mon_dec_y_out347 ;
   output Isyn_mon_y53 ;
   wire Iregister_in_d_d20_d1 ;
   output Idec_req_y167 ;
   output Isyn_pu11_a ;
   wire Iin_d_d30_d0 ;
   wire Iregister_out_d_d4_d0 ;
   wire Isyn_mon_dec_y_out325 ;
   output Inrn_mon_x26 ;
   output Idec_req_y318 ;
   wire Ififo_out_in_d_d3_d1 ;
   output Idec_req_y234 ;
   wire Isyn_mon_dec_y_out17 ;
   wire Isyn_mon_dec_y_out93 ;
   output Ireg_data0_d2_d0 ;
   wire Ienc_inx5_d_d0 ;
   output Ienc_iny5_a ;
   wire Iin_d_d10_d0 ;
   output Ireg_data4_d13_d1 ;
   wire Iappend_enc_out_d_d8_d1 ;
   wire Iappend_enc_in_d_d1_d1 ;
   wire Iregister_out_d_d1_d0 ;
   wire I_demux_out1_d_d22_d1 ;
   output Idec_req_y84 ;
   wire Idecoder_in_d_d3_d0 ;
   wire Isyn_mon_dec_x_out20 ;
   wire Isyn_mon_dec_y_out92 ;
   output Isyn_mon_y216 ;
   output Idec_req_y29 ;
   wire Iencoder_out_v ;
   output Ireg_data6_d7_d0 ;
   wire Isyn_mon_dec_x_out46 ;
   wire Ififo_out_in_d_d16_d0 ;
   wire Iregister_out_d_d3_d0 ;
   output Isyn_mon_y334 ;
   output Isyn_mon_y58 ;
   output Isyn_mon_y6 ;
   wire Inrn_mon_AMZI29 ;
   output Isyn_mon_y151 ;
   wire Isyn_mon_dec_x_out30 ;
   output Idec_req_y175 ;
   wire Iregister_in_d_d18_d1 ;
   output Idec_req_y91 ;
   output Idec_req_y233 ;
   output Isyn_mon_y11 ;
   output Iout_d_d28_d0 ;
   wire I_demux_in_d_d14_d1 ;
   wire I_demux_in_d_d6_d0 ;
   output Ireset_syn_stge_BO0 ;
   output Iout_d_d19_d1 ;
   output Isyn_mon_y247 ;
   output Idec_req_y123 ;
   wire Isyn_mon_AMZI25 ;
   wire Isyn_mon_dec_y_out65 ;
   output Inrn_mon_x8 ;
   wire Isyn_mon_dec_x_out56 ;
   output Idec_req_y305 ;
   wire I_demux_out1_d_d9_d1 ;
   wire Isyn_pu6_d_d0 ;
   output Isyn_mon_y165 ;
   wire I_demux_out2_d_d3_d1 ;
   output Idec_req_y188 ;
   output Idec_req_y250 ;
   wire Iin_d_d17_d1 ;
   output Isyn_mon_y35 ;
   wire Isyn_mon_dec_y_out117 ;
   output Isyn_mon_x3 ;
   wire Idecoder_in_d_d4_d1 ;
   wire Isyn_mon_dec_y_out269 ;
   output Isyn_mon_y257 ;
   output Isyn_mon_y170 ;
   output Idec_req_y103 ;
   output Ireg_data2_d21_d0 ;
   wire Isyn_mon_dec_y_out312 ;
   output Idec_req_y105 ;
   wire Ienc_inx9_d_d0 ;
   wire Isyn_mon_dec_y_out90 ;
   output Idec_req_y78 ;
   output Idec_req_y313 ;
   wire Isyn_mon_AMZI63 ;
   output Ireg_data3_d19_d0 ;
   wire Ififo_out_in_d_d0_d0 ;
   wire Isyn_mon_x_buf_in43 ;
   wire I_demux_in_d_d15_d1 ;
   wire Isyn_mon_AMZI9 ;
   wire Iregister_in_d_d13_d0 ;
   wire Isyn_mon_dec_y_out230 ;
   output Idec_req_x3 ;
   wire Iappend_reg_in_d_d13_d0 ;
   wire Iappend_reg_in_d_d24_d1 ;
   wire Isb_syn_EFO_in0 ;
   wire Isyn_mon_dec_y_out112 ;
   output Isyn_mon_y69 ;
   wire Ififo_out_in_a ;
   output Isyn_mon_x31 ;
   output Idec_req_y246 ;
   output Isyn_mon_x49 ;
   output Idec_req_y203 ;
   wire Isyn_mon_AMZI31 ;
   output Ireg_data1_d19_d1 ;
   wire Inrn_pd_y4_a ;
   wire Isyn_mon_dec_y_out337 ;
   output Idec_req_y77 ;
   output Isyn_mon_y124 ;
   wire Ififo_out_in_d_d5_d0 ;
   output Idec_req_y299 ;
   wire Ififo_out_in_d_d24_d1 ;
   wire Iregister_in_d_d8_d0 ;
   wire Isyn_mon_dec_y_out220 ;
   output Iout_d_d27_d0 ;
   output Iout_d_d13_d1 ;
   output Idec_req_y23 ;
   output Idec_req_y251 ;
   output Ireg_data3_d14_d1 ;
   wire Iappend_reg_in_d_d15_d0 ;
   output Isyn_mon_y307 ;
   output Ireg_data6_d5_d1 ;
   wire Isyn_mon_dec_y_out153 ;
   output Isyn_mon_y195 ;
   wire I_demux_out2_d_d13_d0 ;
   wire Iregister_in_d_d11_d0 ;
   output Ireg_data6_d9_d1 ;
   output Isyn_mon_y174 ;
   output Iout_d_d9_d1 ;
   output Ireg_data4_d8_d1 ;
   wire Isyn_mon_dec_y_out316 ;
   wire I_demux_out1_d_d5_d1 ;
   output Idec_req_y24 ;
   output Ireg_data1_d17_d0 ;
   output Iout_d_d29_d0 ;
   output Iout_d_d5_d0 ;
   output Isyn_mon_y193 ;
   output Isyn_mon_x59 ;
   wire Isyn_mon_dec_x_out48 ;
   wire Inrn_mon_AMZI11 ;
   output Isyn_mon_y167 ;
   output Isyn_pu2_a ;
   wire Iregister_in_d_d19_d1 ;
   output Ireg_data2_d18_d0 ;
   output Inrn_mon_x5 ;
   wire Isyn_mon_dec_y_out209 ;
   output Isyn_mon_y271 ;
   output Isyn_mon_AMZO1 ;
   output Idec_req_y41 ;
   wire Inrn_pd_x2_a ;
   wire Idecoder_dly_cfg3 ;
   wire Iappend_reg_in_d_d18_d0 ;
   output Isyn_mon_y328 ;
   output Isyn_mon_x57 ;
   output Ireg_data5_d10_d1 ;
   wire I_demux_out1_d_d24_d0 ;
   wire I_demux_out1_a ;
   wire I_demux_out1_d_d13_d0 ;
   output Isyn_pu13_a ;
   output Isyn_mon_y140 ;
   output Idec_req_y280 ;
   wire Idec_ackB10 ;
   wire Ififo_out_in_d_d20_d0 ;
   wire Iregister_in_d_d29_d1 ;
   wire Iappend_reg_in_d_d7_d0 ;
   wire Iregister_in_d_d16_d1 ;
   output Isyn_mon_y105 ;
   output Iout_d_d25_d1 ;
   wire Iands_devmon5_y ;
   output Idec_req_y204 ;
   wire Isyn_mon_dec_y_out50 ;
   wire Isyn_mon_dec_x_out31 ;
   wire I_demux_in_d_d7_d1 ;
   wire Iappend_enc_in_d_d5_d1 ;
   wire Iands_devmon1_y ;
   output Ireg_data0_d18_d0 ;
   output Ireg_data7_d8_d1 ;
   output Iout_d_d0_d1 ;
   wire I_demux_out2_d_d4_d0 ;
   output Ireg_data2_d21_d1 ;
   output Ireg_data3_d22_d1 ;
   output Ireg_data0_d21_d0 ;
   output Ireg_data7_d19_d1 ;
   wire Isyn_mon_dec_y_out5 ;
   wire Isyn_mon_dec_y_out275 ;
   output Ireg_data3_d20_d1 ;
   output Idec_req_y177 ;
   output Isyn_mon_y84 ;
   wire Isyn_mon_AMZI0 ;
   wire Isyn_mon_dec_y_out231 ;
   wire Inrn_mon_dec_x_out5 ;
   output Idec_req_y181 ;
   output Isyn_mon_y26 ;
   wire Iappend_enc_out_d_d17_d1 ;
   output Isyn_mon_y130 ;
   wire Isyn_mon_dec_y_out151 ;
   output Idec_req_y343 ;
   wire I_demux_in_d_d25_d1 ;
   output Inrn_mon_y0 ;
   output Ireg_data2_d4_d0 ;
   output Inrn_pd_x4_d_d0 ;
   wire Iappend_enc_out_d_d7_d0 ;
   output Inrn_mon_y2 ;
   output Idec_req_y75 ;
   wire Isyn_mon_dec_y_out48 ;
   output Isyn_mon_y194 ;
   wire Isyn_mon_dec_y_out261 ;
   output Ireg_data2_d5_d1 ;
   wire Iappend_enc_out_d_d21_d1 ;
   wire Inrn_mon_dec_x_out19 ;
   output Ireg_data2_d6_d1 ;
   wire Isyn_mon_dec_y_out323 ;
   output Isyn_mon_y292 ;
   wire Inrn_pd_x8_a ;
   output Idec_req_y47 ;
   wire Isyn_mon_AMZI17 ;
   wire Ififo_out_in_d_d20_d1 ;
   wire Iappend_enc_in_d_d2_d0 ;
   output Idec_req_y229 ;
   wire Iregister_in_d_d6_d0 ;
   wire Inrn_mon_AMZI35 ;
   wire Isyn_mon_dec_y_out175 ;
   wire Ienc_inx12_d_d0 ;
   output Isyn_mon_y294 ;
   wire Iappend_enc_out_d_d11_d1 ;
   output Idec_req_y168 ;
   output Idec_req_y235 ;
   output Ireg_data5_d2_d0 ;
   wire Isyn_mon_dec_y_out287 ;
   output Isyn_mon_y242 ;
   output Idec_req_y336 ;
   output Isyn_mon_x4 ;
   wire Iregister_in_d_d3_d1 ;
   output Ireg_data2_d15_d0 ;
   wire Ienc_iny1_d_d0 ;
   output Ireg_data2_d19_d0 ;
   output Ireg_data3_d22_d0 ;
   wire Iregister_out_d_d26_d1 ;
   wire Iregister_in_d_d15_d0 ;
   output Isyn_mon_y261 ;
   wire Isyn_mon_dec_y_out249 ;
   output Ireg_data4_d20_d0 ;
   output Isyn_mon_y252 ;
   output Idec_req_y114 ;
   output Isyn_mon_y231 ;
   wire I_demux_out1_d_d20_d1 ;
   wire Isyn_mon_dec_y_out62 ;
   output Isyn_mon_y0 ;
   wire Ififo_out_in_d_d8_d1 ;
   output Isyn_mon_x55 ;
   output Idec_req_y193 ;
   wire Isyn_mon_AMZI22 ;
   wire Iregister_out_d_d23_d1 ;
   output Idec_req_y102 ;
   output Ireg_data1_d3_d0 ;
   wire Iin_d_d4_d1 ;
   wire Isyn_mon_dec_y_out276 ;
   output Ireg_data0_d14_d0 ;
   output Ireg_data0_d15_d0 ;
   output Ienc_iny3_a ;
   output Idec_req_y166 ;
   wire Isyn_mon_AMZI34 ;
   output Ireg_data6_d18_d1 ;
   wire Isyn_mon_dec_y_out94 ;
   wire Iout_v ;
   output Idec_req_y267 ;
   wire Idec_ackB13 ;
   wire Iin_d_d30_d1 ;
   output Ireg_data3_d16_d1 ;
   output Isyn_mon_y323 ;
   wire Isyn_mon_dec_y_out211 ;
   output Isyn_mon_y138 ;
   output Isyn_mon_y3 ;
   wire Idecoder_in_d_d4_d0 ;
   output Idec_req_y224 ;
   output Ireg_data7_d8_d0 ;
   output Isyn_mon_y281 ;
   wire I_demux_out2_d_d5_d0 ;
   wire Isyn_mon_AMZI69 ;
   wire Isyn_pu1_d_d0 ;
   wire Ififo_out_in_d_d27_d1 ;
   output Ireg_data3_d2_d1 ;
   output Ireg_data5_d0_d0 ;
   output Idec_req_y143 ;
   output Ireg_data6_d8_d0 ;
   wire Iin_d_d22_d0 ;
   wire Isyn_mon_dec_y_out135 ;
   output Isyn_mon_y154 ;
   wire I_demux_out2_d_d24_d0 ;
   output Idec_req_y238 ;
   output Ireg_data0_d8_d1 ;
   wire Iappend_reg_in_d_d0_d1 ;
   wire Isyn_mon_dec_y_out109 ;
   output Iout_d_d19_d0 ;
   wire I_demux_in_d_d26_d0 ;
   output Idec_req_y107 ;
   output Ireg_data2_d11_d1 ;
   wire Iappend_reg_in_d_d19_d0 ;
   wire Isyn_mon_dec_y_out79 ;
   wire I_demux_out2_d_d11_d1 ;
   wire Ififo_out_in_d_d28_d1 ;
   output Idec_req_y25 ;
   output Idec_req_y301 ;
   wire Inrn_mon_AMZI25 ;
   output Isyn_mon_x54 ;
   wire Isyn_mon_dec_x_out4 ;
   output Idec_req_y38 ;
   output Ireg_data6_d17_d0 ;
   wire Iappend_reg_in_d_d10_d1 ;
   output Isyn_mon_y55 ;
   wire I_demux_out2_d_d21_d1 ;
   output Ireg_data4_d11_d0 ;
   wire Iands_devmon8_a ;
   output Ireg_data7_d21_d1 ;
   wire Isyn_mon_dec_y_out124 ;
   wire Iregister_in_d_d3_d0 ;
   output Isyn_mon_y62 ;
   output Isyn_mon_y110 ;
   output Iout_d_d26_d1 ;
   wire Ififo_out_in_d_d29_d1 ;
   output Idec_req_y112 ;
   output Idec_req_y88 ;
   output Ireg_data7_d13_d1 ;
   output Idec_req_y116 ;
   output Isyn_mon_y30 ;
   wire Inrn_pd_x3_a ;
   output Inrn_mon_x1 ;
   wire Isyn_mon_x_buf_in15 ;
   output Ireg_data6_d10_d0 ;
   output Isyn_mon_y80 ;
   wire Inrn_mon_AMZI31 ;
   wire Isyn_mon_dec_y_out270 ;
   output Isyn_mon_y5 ;
   wire Isyn_mon_AMZI49 ;
   output Iout_d_d9_d0 ;
   output Ireg_data3_d0_d0 ;
   output Ireg_data5_d2_d1 ;
   wire Isyn_mon_dec_x_out34 ;
   wire Isyn_mon_AMZI7 ;
   output Ireg_data7_d18_d0 ;
   wire Inrn_mon_AMZI30 ;
   wire Iappend_reg_in_d_d3_d0 ;
   output Isyn_mon_y312 ;
   output Idec_req_y239 ;
   wire Isyn_mon_dec_y_out147 ;
   output Ireg_data3_d3_d0 ;
   output Idec_req_y155 ;
   output Ienc_inx4_a ;
   output Isyn_mon_y96 ;
   wire Iencoder_out_d_d3_d1 ;
   output Idec_req_y243 ;
   output Ireg_data7_d1_d1 ;
   wire Iin_d_d13_d0 ;
   output Ireg_data2_d0_d0 ;
   output Ireg_data5_d1_d0 ;
   wire Isyn_mon_dec_y_out297 ;
   output Isyn_mon_x18 ;
   wire Isyn_mon_dec_y_out185 ;
   wire Isyn_mon_dec_y_out345 ;
   wire Isyn_mon_x_buf_in7 ;
   output Idec_req_y128 ;
   output Isyn_mon_y327 ;
   output Idec_req_y113 ;
   output Idec_req_y334 ;
   wire Iin_d_d20_d1 ;
   wire Isyn_mon_dec_y_out216 ;
   wire Isyn_mon_dec_x_out51 ;
   output Ireg_data4_d0_d0 ;
   output Isyn_mon_y27 ;
   output Idec_req_y70 ;
   output Ireg_data0_d8_d0 ;
   wire Iappend_enc_out_d_d22_d1 ;
   wire Isyn_mon_dec_x_out14 ;
   wire Idec_ackB2 ;
   output Ireg_data3_d4_d1 ;
   wire Isyn_AMZO_keeps0_y ;
   output Ireg_data6_d10_d1 ;
   wire Iin_d_d23_d0 ;
   wire Inrn_mon_AMZI17 ;
   output Ireg_data1_d6_d1 ;
   wire Isyn_mon_dec_y_out127 ;
   output Ireg_data3_d2_d0 ;
   wire Isyn_mon_dec_y_out164 ;
   output Ireg_data1_d2_d0 ;
   output Iout_d_d14_d1 ;
   output Idec_req_y199 ;
   output Isyn_mon_y9 ;
   wire Ififo_out_in_d_d1_d1 ;
   wire Iregister_in_d_d5_d0 ;
   wire Inrn_mon_AMZI6 ;
   wire Iappend_enc_out_d_d15_d1 ;
   wire Isyn_mon_AMZI8 ;
   wire Isyn_mon_AMZI70 ;
   output Idec_req_y57 ;
   wire Isyn_mon_dec_y_out286 ;
   output Isyn_mon_y204 ;
   output Inrn_pd_x1_d_d0 ;
   wire I_demux_out2_d_d15_d1 ;
   output Ireg_data1_d10_d0 ;
   output Isyn_mon_y342 ;
   wire I_demux_in_d_d8_d0 ;
   output Inrn_mon_x28 ;
   output Ireg_data0_d0_d1 ;
   output Ireg_data2_d14_d0 ;
   output Isyn_mon_y169 ;
   wire Inrn_pd_y0_a ;
   wire Iands_devmon1_a ;
   output Inrn_mon_x2 ;
   output Ireg_data7_d16_d0 ;
   output Isyn_mon_y108 ;
   wire Inrn_mon_dec_x_out13 ;
   output Ireg_data7_d0_d1 ;
   output Isyn_mon_AMZO4 ;
   output Isyn_mon_x20 ;
   wire Isyn_mon_dec_y_out60 ;
   output Isyn_mon_y298 ;
   output Iout_d_d4_d0 ;
   output Ireg_data4_d3_d1 ;
   wire I_demux_out2_d_d19_d1 ;
   output Idec_req_y346 ;
   output Ireg_data5_d22_d1 ;
   output Idec_req_y99 ;
   output Idec_req_y242 ;
   output Ireg_data2_d3_d0 ;
   output Ireg_data7_d9_d1 ;
   wire Iregister_out_d_d14_d0 ;
   output Isyn_mon_y175 ;
   output Iout_d_d20_d1 ;
   wire Isyn_mon_AMZI50 ;
   output Ireg_data6_d3_d1 ;
   output Ireg_data7_d0_d0 ;
   wire Isyn_mon_dec_y_out18 ;
   wire Ienc_inx13_d_d0 ;
   output Ireg_data1_d0_d0 ;
   wire Isyn_mon_AMZI11 ;
   output Ireg_data1_d9_d1 ;
   output Isyn_mon_x45 ;
   output Idec_req_y44 ;
   output Ireg_data0_d6_d0 ;
   wire Isyn_mon_dec_y_out70 ;
   wire Isyn_mon_dec_y_out200 ;
   output Isyn_mon_y299 ;
   output Isyn_mon_y60 ;
   output Isyn_mon_y14 ;
   output Inrn_pd_x13_d_d0 ;
   wire Idecoder_in_d_d12_d1 ;
   output Ireg_data0_d21_d1 ;
   output Ireg_data2_d22_d0 ;
   output Isyn_mon_y297 ;
   output Isyn_mon_y23 ;
   output Idec_req_y172 ;
   wire Isyn_mon_dec_y_out83 ;
   wire I_demux_out2_d_d19_d0 ;
   wire Iappend_enc_out_d_d10_d1 ;
   output Idec_req_x5 ;
   output Ienc_inx9_a ;
   wire Iencoder_out_d_d6_d0 ;
   wire Isyn_mon_dec_y_out165 ;
   output Isyn_mon_y205 ;
   wire I_demux_out2_d_d0_d0 ;
   output Idec_req_y15 ;
   wire Iappend_reg_in_d_d12_d1 ;
   wire Isyn_mon_dec_y_out318 ;
   wire I_demux_in_d_d28_d0 ;
   output Ireg_data2_d8_d1 ;
   wire Iappend_enc_in_d_d4_d1 ;
   output Idec_req_y265 ;
   output Isyn_mon_y126 ;
   output Idec_req_y253 ;
   wire Iregister_out_d_d10_d1 ;
   wire Iin_d_d16_d1 ;
   wire Isyn_mon_AMZI47 ;
   wire Isyn_mon_dec_y_out96 ;
   output Isyn_mon_y100 ;
   output Ireg_data3_d6_d0 ;
   wire Iin_d_d9_d0 ;
   wire I_demux_in_d_d25_d0 ;
   wire Inrn_mon_AMZI7 ;
   wire Isyn_mon_dec_y_out150 ;
   output Isyn_mon_y36 ;
   wire I_demux_in_d_d12_d1 ;
   wire Isyn_mon_dec_y_out340 ;
   output Idec_req_y137 ;
   wire Isyn_AMZO_keeps2_y ;
   wire Iregister_in_d_d14_d0 ;
   wire Inrn_mon_AMZI32 ;
   output Isyn_mon_y346 ;
   output Isyn_mon_y182 ;
   wire Isyn_mon_x_buf_in35 ;
   output Idec_req_y100 ;
   output Isyn_mon_y320 ;
   wire Inrn_mon_dec_x_out9 ;
   output Idec_req_y323 ;
   output Ireg_data2_d10_d1 ;
   wire Isb_syn_EFO_in1 ;
   output Isyn_mon_y70 ;
   output Ireg_data2_d7_d1 ;
   wire Idecoder_dly_cfg0 ;
   wire Isyn_mon_dec_y_out292 ;
   wire Iin_d_d25_d0 ;
   output Idec_req_y294 ;
   wire Iappend_reg_in_d_d4_d0 ;
   output Isyn_mon_y325 ;
   wire Isyn_mon_dec_y_out122 ;
   wire Iout_a ;
   output Idec_req_y210 ;
   output Ireg_data7_d4_d1 ;
   output Ienc_inx8_a ;
   wire Iappend_enc_out_d_d27_d1 ;
   output Idec_req_y136 ;
   wire Iregister_in_d_d5_d1 ;
   output Ireg_data4_d18_d0 ;
   wire Isyn_mon_dec_y_out28 ;
   output Isyn_mon_y147 ;
   output Isyn_mon_x44 ;
   wire Isyn_mon_dec_y_out161 ;
   wire Idecoder_dly_cfg1 ;
   output Ireg_data4_d20_d1 ;
   wire Isyn_mon_dec_y_out236 ;
   output Inrn_pd_y0_d_d0 ;
   wire I_demux_out1_d_d19_d1 ;
   output Idec_req_y64 ;
   output Ireg_data4_d15_d1 ;
   wire Isyn_mon_dec_y_out187 ;
   output Isyn_mon_y220 ;
   wire Iregister_in_d_d18_d0 ;
   output Ireg_data0_d0_d0 ;
   wire I_demux_out2_d_d20_d1 ;
   wire Idecoder_in_v ;
   wire Iappend_reg_in_d_d20_d1 ;
   wire Isyn_mon_dec_y_out280 ;
   wire I_demux_out1_d_d17_d0 ;
   output Idec_req_y261 ;
   wire Iin_d_d2_d1 ;
   wire Iands_devmon2_a ;
   wire I_demux_out1_d_d7_d0 ;
   output Idec_req_y196 ;
   wire Idecoder_in_d_d11_d0 ;
   output Idec_req_x6 ;
   wire Isyn_mon_dec_y_out22 ;
   wire Isyn_mon_dec_y_out290 ;
   wire Inrn_pd_y1_a ;
   output Idec_req_y133 ;
   wire Iregister_in_d_d15_d1 ;
   output Ireg_data5_d7_d1 ;
   wire Iin_d_d12_d1 ;
   output Idec_req_y7 ;
   wire Isyn_mon_dec_y_out148 ;
   output Idec_req_x10 ;
   output Iout_d_d14_d0 ;
   output Idec_req_y86 ;
   output Idec_req_y255 ;
   output Ireg_data3_d19_d1 ;
   wire Isyn_mon_dec_y_out12 ;
   output Idec_req_y283 ;
   output Ireg_data1_d22_d0 ;
   wire Iappend_enc_out_d_d18_d1 ;
   output Ireg_data4_d21_d1 ;
   output Ireg_data5_d15_d1 ;
   wire Isyn_mon_AMZI29 ;
   output Isyn_mon_y258 ;
   wire Iregister_in_d_d11_d1 ;
   wire Inrn_mon_AMZI23 ;
   output Isyn_mon_y166 ;
   output Ireg_data6_d5_d0 ;
   output Iout_d_d8_d0 ;
   output Inrn_pd_x9_d_d0 ;
   wire Inrn_mon_dec_x_out1 ;
   wire Isyn_mon_dec_y_out146 ;
   output Isyn_mon_x41 ;
   wire Iregister_in_d_d8_d1 ;
   wire Iin_d_d6_d0 ;
   wire Isyn_mon_dec_y_out244 ;
   wire I_demux_out1_d_d28_d0 ;
   wire I_demux_in_d_d5_d1 ;
   wire Ififo_out_in_d_d5_d1 ;
   output Idec_req_y332 ;
   output Isyn_mon_y92 ;
   wire Isyn_mon_AMZI45 ;
   wire I_demux_in_d_d2_d0 ;
   output Idec_req_y154 ;
   wire Isyn_mon_dec_y_out54 ;
   output Ireg_data4_d9_d0 ;
   wire Isyn_mon_dec_y_out295 ;
   output Ienc_inx11_a ;
   output Isyn_mon_y277 ;
   wire Iencoder_out_d_d5_d0 ;
   output Idec_req_y111 ;
   wire Isyn_mon_dec_y_out193 ;
   output Idec_req_y262 ;
   output Ireg_data5_d13_d0 ;
   output Isyn_mon_y134 ;
   wire Iands_devmon14_a ;
   wire Isyn_mon_AMZI2 ;
   output Isyn_mon_y29 ;
   wire I_demux_out2_d_d17_d1 ;
   output Idec_req_y169 ;
   output Iin_v ;
   wire Isyn_mon_dec_y_out59 ;
   output Isyn_mon_y289 ;
   wire Isyn_mon_AMZI56 ;
   output Idec_req_y216 ;
   output Ireg_data7_d3_d0 ;
   wire Isyn_mon_dec_y_out25 ;
   wire Isyn_mon_dec_y_out180 ;
   wire Ififo_out_in_d_d12_d1 ;
   output Idec_req_y22 ;
   output Isyn_pu0_a ;
   output Ireg_data6_d0_d0 ;
   wire Iappend_reg_in_d_d1_d1 ;
   output Ireg_data5_d0_d1 ;
   wire Isyn_mon_dec_y_out283 ;
   wire Ienc_inx2_d_d0 ;
   output Isyn_mon_y113 ;
   output Idec_req_x12 ;
   wire Isyn_mon_dec_y_out279 ;
   wire Isyn_mon_AMZI43 ;
   wire I_demux_in_d_d11_d0 ;
   output Inrn_mon_x13 ;
   wire Iregister_in_d_d6_d1 ;
   wire Isyn_mon_dec_y_out170 ;
   output Isyn_mon_y293 ;
   output Ireg_data5_d7_d0 ;
   wire Iappend_reg_in_d_d2_d0 ;
   output Idec_req_y156 ;
   wire I_demux_out1_d_d24_d1 ;
   wire Idecoder_in_d_d0_d0 ;
   wire Inrn_mon_dec_x_out21 ;
   wire Idecoder_in_d_d5_d0 ;
   wire Ienc_iny4_d_d0 ;
   output Isyn_mon_y71 ;
   wire Isyn_mon_dec_y_out237 ;
   output Ireg_data2_d2_d0 ;
   output Isyn_mon_x40 ;
   wire Isyn_mon_dec_y_out98 ;
   wire Ififo_dmx2dec_in_a ;
   output Ireg_data6_d16_d1 ;
   output Isyn_flags_EFO3 ;
   wire Isyn_mon_dec_y_out330 ;
   wire Iregister_out_d_d26_d0 ;
   output Isyn_mon_y267 ;
   output Idec_req_y214 ;
   output Isyn_mon_y209 ;
   wire Inrn_mon_dec_x_out27 ;
   output Isyn_mon_y102 ;
   wire Idec_ackB9 ;
   wire Isyn_mon_AMZI13 ;
   wire Isyn_mon_dec_y_out11 ;
   output Isyn_mon_y248 ;
   output Isyn_mon_y326 ;
   wire Iappend_enc_in_d_d2_d1 ;
   wire Iappend_reg_in_d_d9_d1 ;
   output Isyn_mon_y215 ;
   output Isyn_mon_y32 ;
   wire Inrn_pd_x5_a ;
   wire Iregister_in_d_d24_d0 ;
   output Idec_req_y6 ;
   output Idec_req_y263 ;
   output Isyn_mon_y159 ;
   output Ireg_data0_d13_d1 ;
   output Ireg_data5_d11_d1 ;
   output Idec_req_y67 ;
   output Isyn_mon_y225 ;
   wire Ififo_out_in_d_d13_d0 ;
   wire I_demux_out1_d_d28_d1 ;
   output Idec_req_y208 ;
   output Idec_req_y71 ;
   wire Isyn_mon_dec_y_out118 ;
   output Isyn_mon_y203 ;
   wire Isyn_mon_dec_y_out288 ;
   wire Isyn_mon_dec_y_out322 ;
   output Isyn_mon_y82 ;
   wire Iands_devmon12_a ;
   wire Isyn_mon_dec_y_out272 ;
   wire I_demux_out1_d_d10_d1 ;
   output Idec_req_y160 ;
   output Idec_req_y241 ;
   wire Inrn_mon_AMZI22 ;
   wire Iregister_in_d_d2_d0 ;
   wire Idecoder_in_d_d9_d1 ;
   output Ireg_data0_d12_d1 ;
   output Idec_req_y197 ;
   output Idec_req_y272 ;
   output Ireg_data2_d17_d1 ;
   output Isyn_mon_y12 ;
   wire Ififo_out_in_d_d23_d1 ;
   output Ireg_data4_d0_d1 ;
   wire Isyn_mon_dec_y_out46 ;
   wire Inrn_AMZO_keeps0_y ;
   output Idec_req_y110 ;
   wire Iin_d_d10_d1 ;
   wire Isyn_mon_dec_y_out296 ;
   output Iout_d_d24_d1 ;
   wire I_demux_out1_d_d16_d0 ;
   wire Iregister_in_d_d28_d1 ;
   output Ireg_data0_d11_d0 ;
   wire Iregister_out_d_d5_d0 ;
   wire Iappend_reg_in_d_d10_d0 ;
   output Isyn_mon_y265 ;
   wire Iregister_in_d_d21_d0 ;
   wire Iappend_reg_in_d_d26_d1 ;
   wire Isyn_mon_dec_y_out265 ;
   output Idec_req_y195 ;
   output Isyn_mon_y324 ;
   wire I_demux_out2_d_d0_d1 ;
   wire Iands_devmon4_y ;
   output Idec_req_y295 ;
   output Isyn_mon_y65 ;
   wire Iregister_out_d_d1_d1 ;
   wire Isyn_mon_dec_y_out107 ;
   wire Iappend_enc_out_d_d24_d1 ;
   wire Isyn_mon_dec_y_out336 ;
   output Isyn_mon_y260 ;
   wire Isyn_mon_AMZI39 ;
   output Ireg_data4_d22_d1 ;
   wire Iregister_out_d_d5_d1 ;
   wire Iregister_out_d_d24_d0 ;
   wire Isyn_mon_dec_y_out2 ;
   output Isyn_mon_y103 ;
   wire Isyn_mon_AMZI5 ;
   output Isyn_mon_y152 ;
   wire I_demux_in_d_d28_d1 ;
   wire Iregister_in_d_d9_d1 ;
   output Ireg_data0_d19_d1 ;
   output Ireg_data3_d12_d1 ;
   output Ireg_data7_d17_d1 ;
   output Isyn_mon_y291 ;
   wire I_demux_out1_d_d11_d0 ;
   wire I_demux_in_d_d6_d1 ;
   output Ireg_data3_d7_d1 ;
   wire Iin_d_d16_d0 ;
   output Ienc_inx0_a ;
   output Isyn_mon_y206 ;
   output Ireg_data2_d7_d0 ;
   wire Iappend_reg_in_d_d28_d1 ;
   wire Isyn_mon_dec_x_out2 ;
   wire Inrn_mon_AMZI14 ;
   wire Isyn_mon_dec_y_out186 ;
   wire Inrn_mon_dec_x_out20 ;
   wire Iregister_in_d_d14_d1 ;
   output Ireg_data3_d12_d0 ;
   wire Iregister_out_d_d22_d0 ;
   wire I_demux_in_d_d26_d1 ;
   output Inrn_mon_x0 ;
   output Idec_req_y139 ;
   output Ireg_data4_d10_d0 ;
   wire Isyn_mon_dec_y_out105 ;
   output Isyn_mon_y119 ;
   output Ireg_data7_d19_d0 ;
   wire I_demux_out2_d_d2_d1 ;
   wire Isyn_mon_AMZI64 ;
   output Idec_req_y60 ;
   output Ireg_data6_d8_d1 ;
   wire I_demux_in_d_d18_d0 ;
   wire Inrn_mon_AMZI42 ;
   wire Isyn_mon_dec_y_out267 ;
   output Isyn_mon_y287 ;
   output Isyn_mon_y171 ;
   output Ireg_data6_d0_d1 ;
   wire Isyn_mon_dec_y_out71 ;
   wire Iregister_out_d_d6_d1 ;
   wire Inrn_mon_AMZI27 ;
   wire Isyn_mon_AMZI20 ;
   wire Iands_devmon3_a ;
   wire Isyn_pu0_d_d0 ;
   output Isyn_mon_y259 ;
   wire I_demux_out1_d_d18_d0 ;
   wire I_demux_in_d_d24_d0 ;
   wire Inrn_mon_dec_y_out0 ;
   output Iout_d_d3_d0 ;
   output Ireg_data4_d5_d1 ;
   output Idec_req_y189 ;
   output Isyn_pu10_a ;
   output Idec_req_x0 ;
   output Ireg_data6_d2_d1 ;
   wire Iregister_out_d_d15_d0 ;
   wire Isyn_mon_dec_y_out38 ;
   output Ireg_data5_d17_d0 ;
   output Idec_req_y190 ;
   output Ireg_data5_d14_d1 ;
   wire Isyn_mon_dec_y_out67 ;
   wire Isyn_mon_dec_y_out174 ;
   wire I_demux_out1_d_d14_d0 ;
   output Idec_req_y179 ;
   wire Isyn_pu7_d_d0 ;
   output Isyn_mon_y44 ;
   wire Ififo_out_in_d_d15_d0 ;
   wire I_demux_out1_d_d25_d0 ;
   wire Iappend_enc_out_d_d30_d1 ;
   wire Ififo_out_in_d_d4_d1 ;
   wire I_demux_in_v ;
   output Isyn_mon_x34 ;
   output Idec_req_y232 ;
   wire Isyn_mon_dec_y_out158 ;
   output Isyn_mon_y168 ;
   wire Ififo_out_in_d_d9_d1 ;
   output Idec_req_y164 ;
   wire Ififo_out_in_d_d0_d1 ;
   wire Isyn_mon_AMZI72 ;
   output Ireg_data6_d14_d0 ;
   wire Iappend_reg_in_a ;
   wire Isyn_mon_dec_y_out159 ;
   output Idec_req_y98 ;
   output Isyn_mon_x16 ;
   output Idec_req_y104 ;
   wire Isyn_mon_dec_y_out190 ;
   wire I_demux_out1_d_d23_d1 ;
   wire Isyn_mon_dec_x_out50 ;
   wire Inrn_mon_dec_y_out1 ;
   output Isyn_mon_y309 ;
   wire Inrn_mon_dec_y_out4 ;
   wire Iin_d_d0_d0 ;
   wire Inrn_mon_AMZI10 ;
   wire Isyn_mon_dec_y_out6 ;
   wire Isyn_mon_dec_y_out121 ;
   output Isyn_mon_y233 ;
   wire Iappend_enc_out_d_d25_d1 ;
   output Idec_req_y94 ;
   wire Iregister_out_d_d27_d1 ;
   wire Isyn_mon_dec_y_out199 ;
   wire I_demux_in_d_d30_d1 ;
   wire Isyn_pu10_d_d0 ;
   output Ienc_inx12_a ;
   wire I_demux_in_d_d5_d0 ;
   wire Iregister_out_d_d13_d0 ;
   wire Isyn_mon_dec_y_out271 ;
   wire Iregister_out_d_d24_d1 ;
   output Isyn_mon_y345 ;
   output Inrn_pd_x8_d_d0 ;
   wire I_demux_out2_d_d8_d0 ;
   output Idec_req_y185 ;
   wire Isyn_mon_dec_y_out72 ;
   wire Isyn_mon_dec_y_out189 ;
   output Isyn_mon_y264 ;
   output Idec_req_y129 ;
   output Idec_req_y277 ;
   output Ireg_data1_d20_d0 ;
   output Ireg_data5_d5_d0 ;
   wire Isyn_AMZO_keeps3_y ;
   output Idec_req_y245 ;
   output Isyn_mon_y15 ;
   output Isyn_mon_x38 ;
   output Idec_req_y198 ;
   wire Iappend_reg_in_d_d0_d0 ;
   wire Ififo_out_in_d_d29_d0 ;
   output Ireg_data5_d20_d1 ;
   wire Iregister_out_d_d14_d1 ;
   wire Iappend_reg_in_d_d6_d0 ;
   output Isyn_mon_y176 ;
   wire Isyn_mon_dec_y_out302 ;
   output Ireg_data3_d9_d1 ;
   output Idec_req_y87 ;
   wire Isyn_mon_dec_y_out0 ;
   output Idec_req_y46 ;
   wire Inrn_mon_AMZI2 ;
   wire Isyn_mon_dec_y_out315 ;
   output Isyn_mon_y37 ;
   output Isyn_mon_y54 ;
   output Idec_req_y324 ;
   output Isyn_mon_y89 ;
   wire Ififo_out_in_d_d16_d1 ;
   wire Isyn_mon_dec_y_out47 ;
   output Isyn_mon_x32 ;
   wire Isyn_mon_dec_y_out183 ;
   wire Isyn_mon_dec_y_out262 ;
   wire I_demux_in_d_d4_d1 ;
   output Idec_req_y9 ;
   output Isyn_pu1_a ;
   output Ireg_data1_d8_d1 ;
   output Isyn_mon_y93 ;
   output Inrn_pd_x12_d_d0 ;
   output Idec_req_y268 ;
   output Ireg_data1_d20_d1 ;
   output Inrn_mon_y4 ;
   output Idec_req_y131 ;
   output Idec_req_y344 ;
   wire Isyn_mon_dec_y_out58 ;
   wire Isyn_mon_dec_y_out143 ;
   output Isyn_mon_y83 ;
   output Isyn_mon_x25 ;
   output Ireg_data2_d14_d1 ;
   wire Iregister_out_d_d8_d1 ;
   wire Isyn_mon_dec_x_out10 ;
   wire Isyn_mon_AMZI40 ;
   wire Isyn_mon_dec_y_out241 ;
   output Iout_d_d12_d1 ;
   output Idec_req_y273 ;
   wire I_demux_out2_d_d9_d1 ;
   wire I_demux_in_d_d29_d0 ;
   output Idec_req_y180 ;
   wire Iappend_enc_in_v ;
   output Isyn_mon_y322 ;
   output Ireg_data1_d11_d0 ;
   output Ireg_data5_d3_d1 ;
   output Idec_req_y293 ;
   wire Isyn_mon_dec_y_out80 ;
   output Isyn_mon_AMZO3 ;
   output Isyn_mon_x15 ;
   output Ireg_data0_d9_d1 ;
   wire Iin_d_d29_d0 ;
   wire Isyn_mon_dec_y_out282 ;
   output Inrn_pd_y2_d_d0 ;
   output Isyn_mon_x1 ;
   wire Isyn_mon_dec_y_out33 ;
   output Isyn_mon_y268 ;
   wire Ififo_out_in_d_d10_d1 ;
   wire Inrn_mon_dec_y_out5 ;
   output Idec_req_y159 ;
   output Ireg_data3_d10_d1 ;
   output Ireg_data7_d16_d1 ;
   output Isyn_mon_y189 ;
   output Idec_req_y130 ;
   wire Idec_ackB1 ;
   wire Iin_d_d13_d1 ;
   wire Isyn_mon_dec_y_out226 ;
   output Isyn_mon_y275 ;
   wire I_demux_in_d_d27_d1 ;
   output Ireg_data0_d14_d1 ;
   wire Isyn_mon_dec_y_out255 ;
   output Idec_req_y202 ;
   wire Isyn_mon_dec_y_out344 ;
   output Idec_req_x14 ;
   output Ireg_data5_d19_d0 ;
   output Ireg_data7_d9_d0 ;
   wire Ififo_out_in_d_d26_d1 ;
   output Isyn_mon_x10 ;
   wire Isyn_mon_AMZI3 ;
   output Ireg_data7_d7_d1 ;
   wire Isyn_mon_dec_y_out256 ;
   wire Ififo_out_in_d_d25_d0 ;
   output Ireg_data0_d1_d1 ;
   output Isyn_mon_x42 ;
   output Ireg_data0_d18_d1 ;
   output Isyn_mon_y106 ;
   wire I_demux_in_d_d23_d0 ;
   output Idec_req_y330 ;
   output Isyn_mon_y238 ;
   wire Iregister_in_d_d0_d1 ;
   wire Iands_devmon3_y ;
   output Idec_req_y68 ;
   wire Iregister_in_d_d23_d0 ;
   output Isyn_mon_y47 ;
   wire Iregister_in_d_d4_d1 ;
   output Isyn_mon_y295 ;
   output Isyn_pu8_a ;
   output Isyn_mon_x36 ;
   wire Iregister_out_d_d0_d0 ;
   output Inrn_mon_x29 ;
   output Idec_req_y212 ;
   wire Iappend_reg_in_d_d12_d0 ;
   output Inrn_mon_x15 ;
   output Ireg_data6_d11_d0 ;
   wire Iappend_reg_in_d_d7_d1 ;
   wire Isyn_mon_dec_y_out224 ;
   wire Ienc_inx8_d_d0 ;
   wire Iappend_enc_out_d_d29_d1 ;
   wire Isyn_mon_dec_y_out300 ;
   wire Ienc_inx7_d_d0 ;
   output Isyn_mon_y197 ;
   output Ireg_data1_d1_d1 ;
   output Isyn_mon_y282 ;
   output Isyn_mon_x2 ;
   wire Isyn_mon_dec_y_out215 ;
   wire I_demux_in_d_d1_d1 ;
   wire I_demux_out2_d_d23_d0 ;
   wire Iands_devmon14_y ;
   output Isyn_mon_y42 ;
   wire Inrn_mon_dec_x_out11 ;
   wire Isyn_mon_dec_y_out119 ;
   wire Isyn_mon_dec_x_out24 ;
   wire Isyn_mon_dec_y_out309 ;
   wire Isyn_mon_dec_y_out110 ;
   output Idec_req_y97 ;
   output Isyn_mon_y90 ;
   output Iout_d_d21_d1 ;
   wire Isyn_pu4_d_d0 ;
   output Ireg_data4_d3_d0 ;
   wire Iregister_out_d_d7_d1 ;
   output Isyn_mon_y245 ;
   output Isyn_mon_y153 ;
   wire Ififo_out_in_d_d4_d0 ;
   output Idec_req_y53 ;
   wire Inrn_mon_AMZI34 ;
   output Ireg_data1_d2_d1 ;
   wire Isyn_mon_dec_y_out44 ;
   wire Isyn_mon_dec_y_out78 ;
   output Idec_req_y13 ;
   output Ireg_data6_d2_d0 ;
   wire Isyn_mon_dec_y_out254 ;
   output Isyn_mon_y99 ;
   output Idec_req_x1 ;
   output Idec_req_y278 ;
   output Isyn_mon_y336 ;
   output Isyn_mon_y179 ;
   output Idec_req_y144 ;
   output Ireg_data6_d16_d0 ;
   wire Iappend_reg_in_d_d8_d0 ;
   wire Iin_d_d15_d0 ;
   wire Idecoder_in_d_d6_d1 ;
   wire I_demux_out2_d_d1_d1 ;
   wire I_demux_in_d_d10_d1 ;
   output Ireg_data2_d15_d1 ;
   wire Iin_d_d26_d0 ;
   wire Isyn_mon_dec_y_out169 ;
   output Isyn_mon_y111 ;
   wire Iands_devmon10_y ;
   wire Inrn_AMZO_keeps2_y ;
   output Ireg_data4_d10_d1 ;
   output Isyn_mon_y186 ;
   wire Isyn_mon_dec_y_out222 ;
   output Isyn_pu14_a ;
   wire Isyn_mon_dec_y_out228 ;
   output Isyn_mon_y77 ;
   wire I_demux_out1_d_d19_d0 ;
   wire Isyn_mon_dec_y_out243 ;
   wire Iin_d_d24_d0 ;
   wire Inrn_mon_AMZI38 ;
   wire Isyn_mon_dec_y_out52 ;
   wire Ififo_out_in_d_d7_d1 ;
   output Idec_req_y1 ;
   wire Isyn_mon_dec_y_out213 ;
   output Idec_req_y223 ;
   output Ireg_data0_d17_d0 ;
   output Iout_d_d12_d0 ;
   output Ireg_data3_d4_d0 ;
   output Isyn_mon_x56 ;
   wire Iregister_in_d_d21_d1 ;
   output Ireg_data4_d16_d0 ;
   wire Inrn_mon_AMZI0 ;
   wire Isyn_mon_dec_y_out101 ;
   wire Ififo_dmx2dec_in_v ;
   output Isyn_mon_y1 ;
   output Inrn_mon_x22 ;
   output Idec_req_y14 ;
   wire Iin_d_d29_d1 ;
   wire Iappend_reg_in_d_d3_d1 ;
   wire Inrn_pd_x12_a ;
   wire I_demux_out2_d_d11_d0 ;
   wire Idecoder_in_d_d11_d1 ;
   output Idec_req_y249 ;
   wire Isyn_mon_AMZI32 ;
   output Ireg_data1_d4_d1 ;
   output Idec_req_y40 ;
   wire Isyn_mon_dec_y_out335 ;
   output Isyn_mon_y262 ;
   wire Isyn_mon_dec_y_out250 ;
   output Idec_req_y28 ;
   output Ireg_data0_d5_d0 ;
   wire Iin_d_d25_d1 ;
   wire Isyn_mon_dec_y_out116 ;
   output Idec_req_y108 ;
   wire I_demux_out1_d_d1_d1 ;
   wire Iin_d_d8_d0 ;
   wire Isyn_mon_dec_y_out1 ;
   wire Isyn_mon_dec_y_out311 ;
   output Isyn_mon_y229 ;
   output Iout_d_d1_d0 ;
   output Isyn_mon_x52 ;
   output Idec_req_y81 ;
   wire Inrn_mon_AMZI20 ;
   wire Isyn_mon_dec_y_out245 ;
   wire I_demux_in_d_d24_d1 ;
   output Isyn_mon_y212 ;
   output Isyn_mon_y91 ;
   output Iout_d_d25_d0 ;
   wire Isyn_mon_AMZI12 ;
   output Ireg_data0_d22_d1 ;
   output Ireg_data5_d6_d1 ;
   output Isyn_mon_y272 ;
   wire Inrn_mon_dec_x_out22 ;
   wire Idecoder_in_d_d2_d0 ;
   wire Isyn_mon_dec_y_out137 ;
   output Isyn_mon_y94 ;
   wire Iregister_in_a ;
   output Ireg_data5_d18_d1 ;
   output Isyn_flags_EFO1 ;
   output Isyn_mon_y155 ;
   output Idec_req_y221 ;
   wire Isyn_mon_dec_y_out29 ;
   output Idec_req_x9 ;
   output Isyn_mon_x24 ;
   output Ireg_data7_d2_d1 ;
   output Idec_req_y226 ;
   output Iout_d_d18_d1 ;
   output Idec_req_y151 ;
   output Ireg_data4_d7_d1 ;
   output Ienc_inx5_a ;
   wire I_demux_in_d_d27_d0 ;
   output Isyn_mon_x8 ;
   wire Inrn_mon_AMZI24 ;
   wire Isyn_mon_dec_y_out141 ;
   wire I_demux_out1_d_d26_d0 ;
   output Idec_req_y132 ;
   output Ireg_data2_d22_d1 ;
   wire Iin_d_d27_d0 ;
   output Ireg_data1_d5_d1 ;
   wire Iin_d_d6_d1 ;
   wire Isyn_mon_dec_y_out171 ;
   wire Idecoder_in_d_d1_d1 ;
   wire Isyn_mon_AMZI21 ;
   output Isyn_pu4_a ;
   output Ireg_data4_d22_d0 ;
   wire I_demux_in_d_d21_d0 ;
   output Ireg_data6_d6_d0 ;
   wire I_demux_in_d_d20_d1 ;
   output Ireg_data5_d6_d0 ;
   wire Isyn_mon_dec_x_out23 ;
   output Idec_req_y45 ;
   output Iout_d_d2_d0 ;
   wire I_demux_in_d_d22_d1 ;
   wire I_demux_in_d_d9_d0 ;
   output Isyn_mon_x51 ;
   wire Iands_devmon9_y ;
   output Idec_req_y205 ;
   output Ireg_data1_d14_d0 ;
   output Isyn_mon_y340 ;
   output Ireg_data2_d16_d1 ;
   wire Isyn_mon_dec_y_out111 ;
   output Inrn_pd_y3_d_d0 ;
   output Idec_req_y92 ;
   wire Ienc_inx1_d_d0 ;
   output Iout_d_d3_d1 ;
   wire Isyn_mon_dec_y_out120 ;
   output Isyn_mon_x14 ;
   wire Isyn_mon_dec_y_out308 ;
   output Isyn_mon_y330 ;
   output Idec_req_y66 ;
   output Ireg_data2_d16_d0 ;
   output Iout_d_d10_d0 ;
   wire Ififo_out_in_d_d28_d0 ;
   output Idec_req_y72 ;
   output Isyn_flags_EFO0 ;
   output Iout_d_d15_d1 ;
   output Isyn_mon_x17 ;
   wire reset_syn_stge_BI;
   output Idec_req_y69 ;
   output Iout_d_d5_d1 ;
   wire Isyn_mon_dec_y_out203 ;
   wire Isyn_mon_AMZI46 ;
   wire Isyn_mon_dec_y_out66 ;
   wire Isyn_mon_dec_y_out281 ;
   wire I_demux_out2_d_d13_d1 ;
   wire Inrn_mon_AMZI33 ;
   output Isyn_mon_y227 ;
   wire I_demux_out1_d_d26_d1 ;
   wire Isyn_mon_dec_y_out76 ;
   output Ireg_data2_d13_d0 ;
   output Isyn_mon_x48 ;
   output Idec_req_y257 ;
   wire I_demux_out2_d_d23_d1 ;
   wire Iappend_reg_out_d_d30_d0 ;
   wire Idec_ackB6 ;
   output Ireg_data3_d14_d0 ;
   output Inrn_mon_x10 ;
   wire Inrn_mon_dec_x_out0 ;
   output Isyn_mon_y311 ;
   wire I_demux_out1_d_d11_d1 ;
   output Ireg_data1_d5_d0 ;
   wire Ififo_out_in_d_d19_d1 ;
   output Idec_req_y117 ;
   output Ireg_data3_d20_d0 ;
   wire Isyn_mon_dec_y_out284 ;
   output Inrn_mon_x9 ;
   output Idec_req_y93 ;
   output Ireg_data5_d12_d1 ;
   wire Isyn_mon_dec_y_out196 ;
   output Isyn_mon_y68 ;
   output Ireg_data1_d8_d0 ;
   wire Iregister_out_d_d19_d1 ;
   wire Ififo_out_in_d_d27_d0 ;
   output Idec_req_y51 ;
   output Ireg_data6_d13_d0 ;
   wire Isyn_mon_dec_y_out214 ;
   wire Isyn_mon_dec_y_out41 ;
   output Isyn_mon_y253 ;
   wire Iregister_in_d_d1_d1 ;
   output Isyn_mon_y18 ;
   output Inrn_mon_x14 ;
   output Inrn_mon_x24 ;
   wire Iregister_in_d_d1_d0 ;
   output Idec_req_y150 ;
   wire Ififo_out_in_d_d2_d0 ;
   wire Isyn_mon_x_buf_in23 ;
   output Idec_req_y85 ;
   wire Iappend_reg_in_d_d13_d1 ;
   wire Isyn_mon_dec_y_out195 ;
   output Isyn_mon_y211 ;
   output Ireg_data3_d7_d0 ;
   wire Isyn_mon_dec_y_out103 ;
   output Isyn_mon_y218 ;
   output Isyn_mon_y8 ;
   wire I_demux_in_d_d19_d1 ;
   wire DEV_DEBUG ;
   wire Isyn_mon_dec_y_out233 ;
   wire I_demux_in_d_d0_d1 ;
   wire Iappend_reg_in_d_d22_d0 ;
   output Isyn_mon_y256 ;
   wire I_demux_out2_d_d18_d0 ;
   output Idec_req_y182 ;
   output Isyn_mon_y187 ;
   output Isyn_mon_y177 ;
   output Idec_req_y39 ;
   wire Iregister_out_d_d23_d0 ;
   wire Isyn_mon_dec_y_out343 ;
   output Ireg_data1_d13_d0 ;
   wire Iregister_out_d_d22_d1 ;
   output Isyn_mon_y239 ;
   wire I_demux_out2_d_d27_d1 ;
   output Ireg_data5_d10_d0 ;
   wire Isb_syn_EFO_in2 ;
   output Isyn_mon_y97 ;
   output Iout_d_d22_d1 ;
   output Isyn_mon_y305 ;
   output Isyn_mon_x21 ;
   wire I_demux_in_d_d13_d1 ;
   output Isyn_mon_x58 ;
   wire Isyn_mon_dec_y_out19 ;
   output Ireg_data3_d0_d1 ;
   wire Isyn_mon_AMZI66 ;
   wire Isyn_mon_AMZI41 ;
   output Ireg_data5_d9_d1 ;
   wire Iappend_reg_in_d_d27_d0 ;
   wire Inrn_mon_dec_x_out15 ;
   wire Idecoder_in_d_d9_d0 ;
   wire Isyn_mon_AMZI18 ;
   output Ireg_data6_d3_d0 ;
   output Isyn_mon_x7 ;
   wire Isyn_mon_dec_y_out13 ;
   output Isyn_mon_y249 ;
   wire Inrn_pd_x13_a ;
   output Isyn_mon_y333 ;
   output Isyn_mon_y178 ;
   output Inrn_pd_x5_d_d0 ;
   wire Isyn_mon_dec_y_out115 ;
   wire Isyn_mon_dec_y_out304 ;
   wire Isyn_mon_x_buf_in47 ;
   output Isyn_mon_y180 ;
   wire Isyn_mon_dec_y_out306 ;
   output Isyn_mon_y254 ;
   wire Isyn_mon_dec_y_out49 ;
   wire Isyn_mon_dec_y_out239 ;
   output Isyn_mon_y144 ;
   wire Iregister_in_d_d26_d1 ;
   output Ireg_data6_d1_d1 ;
   wire Isyn_mon_dec_y_out334 ;
   output Idec_req_y327 ;
   wire Iands_devmon7_a ;
   output Idec_req_y120 ;
   output Ireg_data0_d9_d0 ;
   output Ireg_data1_d7_d1 ;
   output Idec_req_y275 ;
   output Ireg_data4_d1_d1 ;
   output Isyn_mon_y217 ;
   wire I_demux_in_d_d7_d0 ;
   wire Isyn_mon_dec_x_out38 ;
   output Idec_req_y211 ;
   output Isyn_mon_y148 ;
   output Idec_req_y184 ;
   output Ireg_data2_d8_d0 ;
   wire Iappend_enc_in_d_d3_d1 ;
   wire Isyn_mon_x_buf_in59 ;
   output Inrn_mon_x25 ;
   wire Isyn_mon_AMZI55 ;
   wire Isyn_mon_dec_y_out144 ;
   output Idec_req_y163 ;
   output Idec_req_y341 ;
   wire Inrn_mon_AMZI16 ;
   output Isyn_mon_y318 ;
   output Ireg_data3_d13_d0 ;
   output Isyn_mon_y41 ;
   wire Idec_ackB7 ;
   output Ireg_data7_d4_d0 ;
   wire Isyn_mon_dec_y_out198 ;
   output Isyn_mon_y39 ;
   wire Ififo_out_in_v ;
   output Idec_req_y54 ;
   output Ireg_data3_d1_d0 ;
   wire Isyn_mon_AMZI54 ;
   output Ireg_data4_d2_d0 ;
   wire Iin_d_d14_d0 ;
   output Ienc_inx1_a ;
   wire Iappend_reg_in_d_d14_d0 ;
   wire Isyn_mon_dec_y_out247 ;
   output Ireg_data3_d17_d1 ;
   wire Inrn_mon_AMZI9 ;
   output Isyn_mon_y314 ;
   wire Isyn_mon_dec_y_out157 ;
   wire Ififo_out_in_d_d13_d1 ;
   output Idec_req_y314 ;
   output Isyn_flags_EFO4 ;
   output Isyn_mon_y127 ;
   wire Isyn_mon_AMZI14 ;
   wire Iregister_out_d_d25_d1 ;
   wire I_demux_out2_d_d4_d1 ;
   output Isyn_mon_x37 ;
   wire Ienc_inx14_d_d0 ;
   wire Isyn_mon_dec_y_out206 ;
   output Isyn_mon_y13 ;
   output Ireg_data7_d3_d1 ;
   wire I_demux_in_d_d13_d0 ;
   output Isyn_mon_y164 ;
   output Idec_req_y309 ;
   wire Isyn_mon_dec_y_out129 ;
   wire Isyn_mon_AMZI6 ;
   wire I_demux_in_d_d3_d1 ;
   output Ireg_data1_d7_d0 ;
   output Iout_d_d23_d0 ;
   output Idec_req_y0 ;
   output Idec_req_y279 ;
   output Ireg_data2_d20_d0 ;
   wire I_demux_out1_d_d16_d1 ;
   output Idec_req_y218 ;
   output Idec_req_y266 ;
   output Isyn_mon_y20 ;
   wire Isyn_mon_dec_y_out9 ;
   wire Isyn_mon_dec_y_out125 ;
   output Ireg_data3_d5_d0 ;
   wire I_demux_out1_d_d29_d0 ;
   wire Iregister_in_d_d17_d1 ;
   output Isyn_mon_y7 ;
   output Isyn_mon_y128 ;
   output Iout_d_d18_d0 ;
   wire Isyn_mon_dec_y_out36 ;
   output Idec_req_y297 ;
   output Ireg_data7_d6_d0 ;
   wire Ififo_out_in_d_d8_d0 ;
   wire Iin_d_d12_d0 ;
   wire I_demux_out2_d_d24_d1 ;
   output Ireg_data1_d15_d1 ;
   output Ireg_data6_d21_d0 ;
   wire Iregister_out_d_d11_d1 ;
   wire Iregister_out_d_d28_d0 ;
   output Isyn_mon_y300 ;
   output Isyn_mon_y146 ;
   output Iout_d_d30_d1 ;
   wire Iappend_enc_out_d_d23_d1 ;
   output Idec_req_y16 ;
   output Ireg_data4_d1_d0 ;
   output Isyn_mon_y313 ;
   output Iout_d_d8_d1 ;
   wire Iencoder_out_d_d2_d0 ;
   wire Iregister_in_v ;
   output Isyn_mon_y129 ;
   wire Isyn_mon_dec_y_out327 ;
   output Ireg_data1_d18_d1 ;
   output Ireg_data7_d20_d0 ;
   wire Isyn_mon_dec_y_out142 ;
   output Idec_req_y135 ;
   output Ireg_data0_d20_d1 ;
   wire Inrn_mon_dec_x_out7 ;
   wire Idecoder_in_d_d2_d1 ;
   wire Iregister_out_v ;
   wire Isyn_mon_dec_y_out294 ;
   wire I_demux_out1_d_d12_d1 ;
   wire I_demux_out1_d_d4_d0 ;
   output Inrn_mon_x27 ;
   wire Iappend_reg_in_d_d25_d0 ;
   output Isyn_mon_y283 ;
   wire Inrn_mon_dec_x_out14 ;
   output Idec_req_y290 ;
   wire Iregister_out_d_d21_d1 ;
   wire Iregister_out_d_d6_d0 ;
   wire Iin_d_d21_d0 ;
   output Isyn_mon_y198 ;
   wire Iencoder_out_d_d1_d0 ;
   wire Iappend_reg_in_d_d23_d1 ;
   output Isyn_mon_y347 ;
   wire Isyn_mon_AMZI48 ;
   wire Isyn_mon_dec_y_out34 ;
   output Ireg_data3_d11_d1 ;
   wire Idec_ackB5 ;
   output Isyn_mon_y207 ;
   wire I_demux_out2_d_d15_d0 ;
   output Ireg_data7_d2_d0 ;
   wire Iappend_reg_in_d_d17_d0 ;
   output Isyn_mon_y210 ;
   output Idec_req_y339 ;
   output Ireg_data2_d9_d0 ;
   wire Iregister_out_d_d16_d1 ;
   output Ireg_data6_d19_d0 ;
   output Ireg_data4_d13_d0 ;
   wire Isyn_mon_dec_y_out136 ;
   output Idec_req_y162 ;
   output Isyn_mon_x9 ;
   wire Isyn_mon_dec_y_out172 ;
   wire Iregister_in_d_d27_d1 ;
   output Iout_d_d4_d1 ;
   wire Iands_devmon12_y ;
   output Ireg_data0_d7_d1 ;
   wire Isyn_mon_dec_y_out240 ;
   wire Isyn_mon_dec_y_out184 ;
   output Isyn_mon_y338 ;
   wire I_demux_out1_d_d3_d0 ;
   wire Inrn_mon_dec_x_out29 ;
   wire Isyn_mon_dec_y_out342 ;
   output Idec_req_y17 ;
   wire Iregister_out_d_d15_d1 ;
   wire Isyn_mon_dec_y_out26 ;
   wire Isyn_mon_dec_y_out35 ;
   wire Idec_ackB12 ;
   wire Isyn_pu5_d_d0 ;
   output Isyn_mon_y255 ;
   output Idec_req_y240 ;
   output Isyn_mon_y285 ;
   wire Inrn_mon_dec_x_out26 ;
   output Idec_req_y310 ;
   wire Idec_ackB4 ;
   wire Iin_d_d24_d1 ;
   wire Idecoder_in_d_d8_d0 ;
   output Ireg_data2_d9_d1 ;
   output Isyn_mon_y303 ;
   wire I_demux_in_d_d29_d1 ;
   wire Inrn_mon_AMZI21 ;
   output Isyn_mon_y202 ;
   output Inrn_flags_EFO0 ;
   wire Isyn_mon_dec_y_out339 ;
   wire Isyn_mon_dec_y_out163 ;
   output Isyn_mon_y237 ;
   wire Ififo_out_in_d_d10_d0 ;
   wire Iappend_reg_in_d_d8_d1 ;
   wire Iappend_reg_in_d_d9_d0 ;
   wire Isyn_mon_dec_y_out114 ;
   output Isyn_mon_y208 ;
   wire Ififo_out_in_d_d11_d1 ;
   output Idec_req_y289 ;
   output Idec_req_y21 ;
   output Ireg_data3_d18_d0 ;
   wire Iregister_out_d_d17_d1 ;
   wire Iregister_out_d_d28_d1 ;
   output Iout_d_d6_d1 ;
   wire Iin_d_d27_d1 ;
   wire Iappend_reg_out_d_d29_d0 ;
   wire Iregister_in_d_d27_d0 ;
   output Ireg_data5_d16_d1 ;
   output Isyn_mon_y10 ;
   output Iout_d_d23_d1 ;
   output Ireg_data1_d21_d0 ;
   wire Isyn_mon_dec_y_out179 ;
   wire Idecoder_in_d_d12_d0 ;
   output Ireg_data1_d14_d1 ;
   wire Iregister_out_d_d2_d0 ;
   wire Iin_d_d5_d0 ;
   wire I_demux_out2_d_d22_d1 ;
   wire Idecoder_in_d_d0_d1 ;
   output Ireg_data0_d15_d1 ;
   output Ienc_inx13_a ;
   output Isyn_mon_y222 ;
   output Isyn_mon_y131 ;
   wire Ififo_out_in_d_d24_d0 ;
   wire Iappend_enc_out_d_d28_d1 ;
   wire Inrn_mon_dec_x_out23 ;
   output Idec_req_y148 ;
   output Idec_req_y329 ;
   output Ireg_data7_d12_d1 ;
   wire I_demux_out1_d_d1_d0 ;
   output Idec_req_y174 ;
   wire Isyn_mon_dec_y_out97 ;
   wire Iands_devmon13_y ;
   output Idec_req_y79 ;
   wire _reset_BX ;
   output Isyn_mon_y61 ;
   wire Isyn_mon_dec_y_out152 ;
   wire Isyn_mon_dec_y_out259 ;
   wire Inrn_pd_x11_a ;
   wire Iregister_in_d_d19_d0 ;
   wire Isyn_mon_dec_y_out274 ;
   output Isyn_mon_y319 ;
   wire Isyn_mon_AMZI33 ;
   wire Iappend_enc_out_d_d19_d1 ;
   output Ireg_data0_d11_d1 ;
   output Ienc_inx3_a ;
   output Idec_req_y142 ;
   output Isyn_flags_EFO2 ;
   wire Iappend_enc_out_d_d9_d1 ;
   output Idec_req_y3 ;
   output Idec_req_y291 ;
   wire Isyn_mon_dec_y_out85 ;
   output Isyn_mon_y280 ;
   output Idec_req_x7 ;
   wire Iregister_in_d_d16_d0 ;
   output Ireg_data1_d22_d1 ;
   wire Iin_d_d17_d0 ;
   wire Ififo_out_in_d_d30_d0 ;
   wire Iappend_enc_out_d_d12_d1 ;
   output Ireg_data6_d7_d1 ;
   output Isyn_mon_y344 ;
   output Idec_req_y191 ;
   wire Isyn_mon_dec_y_out7 ;
   wire I_demux_out1_d_d25_d1 ;
   wire Isyn_mon_dec_y_out191 ;
   output Isyn_mon_y45 ;
   output Idec_req_y222 ;
   output Isyn_mon_x12 ;
   wire Isyn_mon_dec_y_out194 ;
   output Iout_d_d11_d1 ;
   wire Iregister_out_a ;
   output Ireg_data4_d8_d0 ;
   output Isyn_mon_y219 ;
   wire Isyn_mon_dec_y_out234 ;
   output Isyn_mon_y244 ;
   output Idec_req_y140 ;
   wire Iregister_in_d_d12_d1 ;
   wire Iappend_reg_in_d_d19_d1 ;
   output Idec_req_y161 ;
   wire Isyn_mon_dec_y_out61 ;
   output Isyn_mon_x39 ;
   wire Iands_devmon8_y ;
   output Idec_req_y219 ;
   output Idec_req_y236 ;
   output Isyn_mon_y137 ;
   wire Isyn_mon_dec_y_out154 ;
   wire Isyn_mon_dec_x_out54 ;
   wire Isyn_mon_AMZI28 ;
   output Ienc_inx7_a ;
   output Ireg_data3_d21_d1 ;
   output Ireg_data1_d4_d0 ;
   output Ireg_data6_d20_d0 ;
   output Isyn_mon_AMZO2 ;
   output Idec_req_y337 ;
   wire Inrn_mon_AMZI37 ;
   wire Isyn_mon_dec_y_out128 ;
   output Isyn_mon_y76 ;
   wire Ififo_out_in_d_d22_d0 ;
   wire Iappend_reg_in_d_d5_d1 ;
   output Isyn_mon_y141 ;
   wire Iands_devmon10_a ;
   output Ireg_data6_d22_d0 ;
   wire Ififo_out_in_d_d18_d1 ;
   wire Inrn_pd_x6_a ;
   output Isyn_mon_y57 ;
   output Idec_req_y328 ;
   wire I_demux_out2_d_d3_d0 ;
   output Ireg_data5_d22_d0 ;
   output Isyn_mon_y321 ;
   output Idec_req_y76 ;
   output Idec_req_y194 ;
   output Ireg_data3_d10_d0 ;
   output Ireg_data6_d4_d1 ;
   wire Iin_d_d0_d1 ;
   wire Iin_d_d9_d1 ;
   output Inrn_pd_x0_d_d0 ;
   wire Isyn_mon_dec_y_out328 ;
   wire Iappend_reg_in_d_d1_d0 ;
   output Isyn_mon_y339 ;
   wire Isyn_mon_AMZI59 ;
   output Ireg_data1_d16_d0 ;
   wire Isyn_mon_dec_y_out168 ;
   output Ireg_data0_d2_d1 ;
   output Idec_req_y207 ;
   wire Isyn_mon_dec_y_out207 ;
   wire Inrn_pd_x0_a ;
   output Ireg_data3_d8_d0 ;
   output Ireset_syn_hs_BO0 ;
   output Iout_d_d6_d0 ;
   wire Inrn_pd_y5_a ;
   wire Iregister_in_d_d0_d0 ;
   output Isyn_mon_x22 ;
   output Ireg_data1_d6_d0 ;
   wire I_demux_out1_d_d27_d1 ;
   wire Inrn_mon_dec_x_out24 ;
   output Idec_req_y296 ;
   output Isyn_mon_x5 ;
   output Idec_req_y187 ;
   wire Iregister_in_d_d2_d1 ;
   wire Isyn_mon_dec_y_out252 ;
   wire I_demux_out2_v ;
   wire Isyn_mon_dec_x_out36 ;
   wire Isyn_mon_AMZI27 ;
   output Isyn_mon_y270 ;
   wire Iands_devmon11_a ;
   wire Inrn_mon_dec_x_out4 ;
   wire reset_B;
   wire Isyn_mon_dec_y_out197 ;
   wire I_demux_out2_d_d6_d0 ;
   output Ireg_data4_d21_d0 ;
   output Isyn_mon_y224 ;
   wire Isyn_mon_AMZI24 ;
   output Ireg_data7_d15_d1 ;
   wire Iregister_out_d_d13_d1 ;
   wire Iappend_reg_in_d_d28_d0 ;
   output Isyn_mon_y213 ;
   output Isyn_mon_y143 ;
   output Idec_req_y157 ;
   output Idec_req_y227 ;
   wire Iin_d_d15_d1 ;
   output Ireg_data6_d6_d1 ;
   output Iout_d_d28_d1 ;
   output Ireg_data6_d20_d1 ;
   output Ireg_data2_d1_d1 ;
   wire Iin_d_d11_d1 ;
   wire Isyn_mon_dec_y_out138 ;
   wire Isyn_mon_dec_y_out264 ;
   wire Iregister_in_d_d22_d1 ;
   wire Iencoder_out_d_d2_d1 ;
   wire Iappend_enc_out_d_d26_d1 ;
   output Isyn_mon_y304 ;
   wire I_demux_out1_d_d15_d0 ;
   output Idec_req_y225 ;
   wire Idec_ackB11 ;
   output Ireg_data0_d10_d1 ;
   output Ireg_data6_d9_d0 ;
   wire Iappend_reg_in_d_d14_d1 ;
   wire Isyn_mon_dec_y_out242 ;
   output Ireg_data3_d6_d1 ;
   output Isyn_mon_y228 ;
   output Ireg_data3_d1_d1 ;
   wire I_demux_in_d_d30_d0 ;
   output Ireg_data4_d4_d1 ;
   wire Isyn_mon_dec_y_out69 ;
   output Isyn_mon_y121 ;
   output Ireg_data1_d12_d1 ;
   wire Iin_d_d11_d0 ;
   wire Isyn_mon_dec_y_out319 ;
   output Isyn_mon_y172 ;
   wire I_demux_out1_d_d15_d1 ;
   output Isyn_mon_x53 ;
   output Idec_req_y145 ;
   output Idec_req_y230 ;
   wire Isyn_mon_dec_y_out314 ;
   output Isyn_mon_y72 ;
   output Ireg_data5_d13_d1 ;
   output Isyn_mon_y310 ;
   wire Iin_d_d21_d1 ;
   wire Ienc_inx4_d_d0 ;
   wire I_demux_out1_v ;
   output Idec_req_y209 ;
   output Ireg_data4_d4_d0 ;
   wire Idecoder_in_a ;
   output Idec_req_y8 ;
   wire Isyn_mon_dec_y_out8 ;
   wire Isyn_mon_dec_y_out178 ;
   wire I_demux_in_d_d15_d0 ;
   output Ireset_nrn_stge_BO0 ;
   output Idec_req_y101 ;
   wire Isyn_AMZO_keeps1_y ;
   output Ireg_data7_d1_d0 ;
   wire Iencoder_out_d_d4_d1 ;
   wire Isyn_mon_AMZI35 ;
   wire Iappend_reg_in_d_d6_d1 ;
   output Idec_req_y48 ;
   output Ireg_data2_d17_d0 ;
   output Isyn_mon_x43 ;
   wire Isyn_mon_dec_y_out45 ;
   wire Isyn_mon_dec_y_out113 ;
   output Isyn_mon_y250 ;
   output Idec_req_y254 ;
   wire Iregister_out_d_d18_d0 ;
   output Ireg_data3_d5_d1 ;
   wire I_demux_out2_d_d10_d1 ;
   wire Isyn_mon_dec_y_out81 ;
   output Isyn_mon_y64 ;
   wire Isyn_mon_dec_y_out88 ;
   wire Isyn_mon_dec_x_out15 ;
   output Idec_req_y50 ;
   wire Ififo_out_in_d_d25_d1 ;
   wire I_demux_out2_d_d7_d0 ;
   output Idec_req_y83 ;
   output Ireg_data4_d12_d0 ;
   wire Iregister_out_d_d18_d1 ;
   wire I_demux_out1_d_d2_d1 ;
   output Idec_req_y319 ;
   output Ireg_data3_d11_d0 ;
   output Isyn_mon_y107 ;
   wire Ififo_out_in_d_d1_d0 ;
   output Isyn_mon_y157 ;
   wire Ififo_out_in_d_d21_d0 ;
   wire I_demux_in_d_d0_d0 ;
   wire Iappend_reg_in_d_d24_d0 ;
   output Inrn_mon_AMZO1 ;
   wire Isyn_mon_x_buf_in19 ;
   wire Iands_devmon2_y ;
   wire I_demux_out1_d_d4_d1 ;
   output Ireg_data4_d2_d1 ;
   wire Isyn_mon_dec_y_out57 ;
   wire Iregister_out_d_d11_d0 ;
   wire Isyn_mon_dec_y_out341 ;
   wire Iappend_enc_in_d_d3_d0 ;
   output Idec_req_y2 ;
   output Idec_req_y326 ;
   wire Isyn_mon_AMZI1 ;
   wire Idecoder_in_d_d10_d1 ;
   output Idec_req_y298 ;
   output Isyn_mon_y343 ;
   wire Ififo_out_in_d_d17_d1 ;
   wire Isyn_mon_dec_y_out268 ;
   output Ireg_data4_d19_d1 ;
   wire I_demux_in_d_d17_d1 ;
   output Idec_req_y340 ;
   output Ireg_data5_d14_d0 ;
   wire Iappend_reg_in_d_d21_d0 ;
   wire Isyn_mon_dec_y_out205 ;
   wire Idecoder_in_d_d5_d1 ;
   output Idec_req_y20 ;
   wire Iregister_in_d_d7_d0 ;
   wire Isyn_mon_dec_y_out55 ;
   output Isyn_mon_y274 ;
   output Iout_d_d11_d0 ;
   output Isyn_pu12_a ;
   output Idec_req_y106 ;
   wire Isyn_mon_dec_y_out130 ;
   output Isyn_mon_x47 ;
   output Isyn_mon_y120 ;
   wire Isyn_mon_x_buf_in55 ;
   output Idec_req_y312 ;
   output Inrn_mon_x12 ;
   output Isyn_mon_y139 ;
   wire Isyn_mon_dec_x_out12 ;
   output Ireg_data5_d16_d0 ;
   output Ireg_data7_d10_d0 ;
   wire Isyn_mon_dec_y_out305 ;
   output Isyn_mon_y316 ;
   wire I_demux_in_d_d18_d1 ;
   output Idec_req_y12 ;
   wire Isyn_mon_dec_y_out321 ;
   output Isyn_mon_y337 ;
   wire I_demux_in_d_d4_d0 ;
   output Idec_req_y55 ;
   wire I_demux_out1_d_d0_d1 ;
   output Idec_req_y5 ;
   wire Idecoder_dly_cfg2 ;
   output Isyn_mon_y132 ;
   wire I_demux_out2_d_d14_d0 ;
   output Idec_req_y147 ;
   wire Ififo_out_in_d_d2_d1 ;
   wire Isyn_mon_dec_y_out285 ;
   output Isyn_mon_y288 ;
   wire Isyn_mon_AMZI62 ;
   output Idec_req_y237 ;
   wire Isyn_mon_dec_y_out149 ;
   output Isyn_mon_y24 ;
   output Ireg_data5_d4_d1 ;
   wire Inrn_mon_AMZI8 ;
   wire Isyn_mon_dec_y_out74 ;
   output Isyn_mon_y150 ;
   output Ireg_data6_d19_d1 ;
   wire Isyn_mon_dec_y_out31 ;
   wire I_demux_out2_d_d21_d0 ;
   wire I_demux_out2_d_d12_d0 ;
   output Ireg_data5_d9_d0 ;
   wire Ienc_iny2_d_d0 ;
   output Ireg_data0_d1_d0 ;
   output Ireg_data5_d8_d0 ;
   wire Isyn_mon_dec_x_out28 ;
   wire Iregister_in_d_d25_d0 ;
   output Ienc_inx6_a ;
   wire Ififo_out_in_d_d19_d0 ;
   wire I_demux_out2_d_d20_d0 ;
   wire Inrn_mon_dec_x_out10 ;
   output Idec_req_y33 ;
   wire Isyn_pu8_d_d0 ;
   wire Iin_d_d14_d1 ;
   output Isyn_mon_y115 ;
   output Ireg_data2_d19_d1 ;
   wire Iappend_enc_out_d_d7_d1 ;
   output Idec_req_y307 ;
   wire Iappend_reg_in_d_d17_d1 ;
   output Iin_a ;
   output Isyn_mon_y28 ;
   output Ireg_data3_d3_d1 ;
   output Ireg_data7_d12_d0 ;
   output Ienc_iny2_a ;
   output Isyn_mon_y135 ;
   output Iout_d_d20_d0 ;
   wire I_demux_out1_d_d10_d0 ;
   output Idec_req_y260 ;
   wire Isyn_mon_dec_y_out156 ;
   wire Isyn_mon_dec_y_out301 ;
   output Idec_req_y178 ;
   wire reset_reg_B;
   wire Isyn_mon_dec_y_out89 ;
   wire Iands_devmon13_a ;
   wire Isyn_mon_dec_y_out313 ;
   output Inrn_mon_x19 ;
   output Isyn_mon_x11 ;
   wire Isyn_mon_AMZI16 ;
   output Iout_d_d24_d0 ;
   wire I_demux_out2_d_d28_d1 ;
   output Idec_req_y308 ;
   wire Iin_d_d28_d0 ;
   wire Isyn_mon_dec_y_out68 ;
   wire Isyn_mon_dec_y_out86 ;
   output Idec_req_y259 ;
   output Isyn_mon_y74 ;
   output Idec_req_y62 ;
   output Ireg_data2_d10_d0 ;
   output Isyn_mon_y251 ;
   output Isyn_mon_y163 ;
   output Idec_req_y152 ;
   output Idec_req_y281 ;
   wire Isyn_mon_dec_y_out218 ;
   wire Ififo_out_in_d_d12_d0 ;
   output Idec_req_y200 ;
   wire Isyn_mon_dec_y_out73 ;
   output Idec_req_y320 ;
   wire Iin_d_d28_d1 ;
   output Isyn_mon_y122 ;
   wire I_demux_in_d_d10_d0 ;
   output Idec_req_y347 ;
   wire Iin_d_d4_d0 ;
   wire Isyn_mon_dec_y_out210 ;
   wire Ififo_out_in_d_d14_d0 ;
   wire I_demux_in_d_d8_d1 ;
   output Idec_req_y304 ;
   wire Iregister_out_d_d9_d1 ;
   output Idec_req_y342 ;
   wire I_demux_in_d_d2_d1 ;
   wire Inrn_mon_AMZI39 ;
   output Idec_req_y59 ;
   wire Isyn_mon_dec_y_out145 ;
   wire Iappend_reg_out_d_d29_d1 ;
   output Inrn_mon_x20 ;
   wire Isyn_mon_x_buf_in51 ;
   output Idec_req_y89 ;
   output Idec_req_x13 ;
   output Ireg_data0_d20_d0 ;
   wire Inrn_mon_AMZI3 ;
   wire Isyn_mon_dec_y_out202 ;
   output Isyn_mon_y19 ;
   output Ireg_data6_d14_d1 ;
   wire I_demux_out1_d_d3_d1 ;
   output Ireg_data6_d12_d0 ;
   output Isyn_mon_y22 ;
   wire Inrn_pd_x9_a ;
   output Idec_req_y165 ;
   output Ireg_data7_d14_d1 ;
   output Idec_req_x11 ;
   output Idec_req_y11 ;
   wire Ififo_out_in_d_d3_d0 ;
   output Idec_req_y134 ;
   output Ireg_data1_d9_d0 ;
   wire Inrn_mon_AMZI26 ;
   wire I_demux_out2_d_d14_d1 ;
   output Idec_req_y231 ;
   output Ireg_data6_d22_d1 ;
   wire Iappend_reg_in_d_d23_d0 ;
   output Isyn_mon_y118 ;
   wire Iencoder_out_d_d6_d1 ;
   output Idec_req_y19 ;
   wire Ienc_inx3_d_d0 ;
   output Isyn_mon_y301 ;
   output Ienc_iny4_a ;
   wire Inrn_mon_AMZI5 ;
   wire Isyn_mon_dec_y_out56 ;
   wire Isupply_vss ;
   wire Isyn_mon_x_buf_in3 ;
   output Idec_req_y173 ;
   output Isyn_pu3_a ;
   output Ireg_data0_d12_d0 ;
   output Ireg_data0_d16_d0 ;
   output Ireg_data6_d4_d0 ;
   wire Isyn_mon_dec_y_out75 ;
   wire Isyn_mon_dec_y_out266 ;
   output Isyn_mon_y234 ;
   wire Isyn_mon_dec_x_out0 ;
   output Ireg_data7_d20_d1 ;
   wire Isyn_mon_x_buf_in31 ;
   wire I_demux_out1_d_d29_d1 ;
   output Idec_req_y82 ;
   output Inrn_mon_y3 ;
   output Idec_req_y43 ;
   wire Inrn_mon_AMZI41 ;
   output Isyn_mon_y33 ;
   output Inrn_pd_x2_d_d0 ;
   output Isyn_mon_y290 ;
   output Isyn_mon_y332 ;
   wire Iin_d_d23_d1 ;
   output Isyn_mon_y279 ;
   output Isyn_mon_y117 ;
   wire Isyn_mon_x_buf_in39 ;
   output Inrn_mon_y5 ;
   output Ireg_data4_d7_d0 ;

// --- instances
KEEP Isyn_AMZO_keeps0  (.y(Isyn_AMZO_keeps0_y ), .vdd(vdd), .vss(vss));
KEEP Isyn_AMZO_keeps1  (.y(Isyn_AMZO_keeps1_y ), .vdd(vdd), .vss(vss));
KEEP Isyn_AMZO_keeps2  (.y(Isyn_AMZO_keeps2_y ), .vdd(vdd), .vss(vss));
KEEP Isyn_AMZO_keeps3  (.y(Isyn_AMZO_keeps3_y ), .vdd(vdd), .vss(vss));
KEEP Isyn_AMZO_keeps4  (.y(Isyn_AMZO_keeps4_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4 Idecoder  (.Iin_d_d0_d0 (Idecoder_in_d_d0_d0 ), .Iin_d_d0_d1 (Idecoder_in_d_d0_d1 ), .Iin_d_d1_d0 (Idecoder_in_d_d1_d0 ), .Iin_d_d1_d1 (Idecoder_in_d_d1_d1 ), .Iin_d_d2_d0 (Idecoder_in_d_d2_d0 ), .Iin_d_d2_d1 (Idecoder_in_d_d2_d1 ), .Iin_d_d3_d0 (Idecoder_in_d_d3_d0 ), .Iin_d_d3_d1 (Idecoder_in_d_d3_d1 ), .Iin_d_d4_d0 (Idecoder_in_d_d4_d0 ), .Iin_d_d4_d1 (Idecoder_in_d_d4_d1 ), .Iin_d_d5_d0 (Idecoder_in_d_d5_d0 ), .Iin_d_d5_d1 (Idecoder_in_d_d5_d1 ), .Iin_d_d6_d0 (Idecoder_in_d_d6_d0 ), .Iin_d_d6_d1 (Idecoder_in_d_d6_d1 ), .Iin_d_d7_d0 (Idecoder_in_d_d7_d0 ), .Iin_d_d7_d1 (Idecoder_in_d_d7_d1 ), .Iin_d_d8_d0 (Idecoder_in_d_d8_d0 ), .Iin_d_d8_d1 (Idecoder_in_d_d8_d1 ), .Iin_d_d9_d0 (Idecoder_in_d_d9_d0 ), .Iin_d_d9_d1 (Idecoder_in_d_d9_d1 ), .Iin_d_d10_d0 (Idecoder_in_d_d10_d0 ), .Iin_d_d10_d1 (Idecoder_in_d_d10_d1 ), .Iin_d_d11_d0 (Idecoder_in_d_d11_d0 ), .Iin_d_d11_d1 (Idecoder_in_d_d11_d1 ), .Iin_d_d12_d0 (Idecoder_in_d_d12_d0 ), .Iin_d_d12_d1 (Idecoder_in_d_d12_d1 ), .Iin_a (Idecoder_in_a ), .Iin_v (Idecoder_in_v ), .Iout_req_x0 (Idec_req_x0 ), .Iout_req_x1 (Idec_req_x1 ), .Iout_req_x2 (Idec_req_x2 ), .Iout_req_x3 (Idec_req_x3 ), .Iout_req_x4 (Idec_req_x4 ), .Iout_req_x5 (Idec_req_x5 ), .Iout_req_x6 (Idec_req_x6 ), .Iout_req_x7 (Idec_req_x7 ), .Iout_req_x8 (Idec_req_x8 ), .Iout_req_x9 (Idec_req_x9 ), .Iout_req_x10 (Idec_req_x10 ), .Iout_req_x11 (Idec_req_x11 ), .Iout_req_x12 (Idec_req_x12 ), .Iout_req_x13 (Idec_req_x13 ), .Iout_req_x14 (Idec_req_x14 ), .Iout_req_y0 (Idec_req_y0 ), .Iout_req_y1 (Idec_req_y1 ), .Iout_req_y2 (Idec_req_y2 ), .Iout_req_y3 (Idec_req_y3 ), .Iout_req_y4 (Idec_req_y4 ), .Iout_req_y5 (Idec_req_y5 ), .Iout_req_y6 (Idec_req_y6 ), .Iout_req_y7 (Idec_req_y7 ), .Iout_req_y8 (Idec_req_y8 ), .Iout_req_y9 (Idec_req_y9 ), .Iout_req_y10 (Idec_req_y10 ), .Iout_req_y11 (Idec_req_y11 ), .Iout_req_y12 (Idec_req_y12 ), .Iout_req_y13 (Idec_req_y13 ), .Iout_req_y14 (Idec_req_y14 ), .Iout_req_y15 (Idec_req_y15 ), .Iout_req_y16 (Idec_req_y16 ), .Iout_req_y17 (Idec_req_y17 ), .Iout_req_y18 (Idec_req_y18 ), .Iout_req_y19 (Idec_req_y19 ), .Iout_req_y20 (Idec_req_y20 ), .Iout_req_y21 (Idec_req_y21 ), .Iout_req_y22 (Idec_req_y22 ), .Iout_req_y23 (Idec_req_y23 ), .Iout_req_y24 (Idec_req_y24 ), .Iout_req_y25 (Idec_req_y25 ), .Iout_req_y26 (Idec_req_y26 ), .Iout_req_y27 (Idec_req_y27 ), .Iout_req_y28 (Idec_req_y28 ), .Iout_req_y29 (Idec_req_y29 ), .Iout_req_y30 (Idec_req_y30 ), .Iout_req_y31 (Idec_req_y31 ), .Iout_req_y32 (Idec_req_y32 ), .Iout_req_y33 (Idec_req_y33 ), .Iout_req_y34 (Idec_req_y34 ), .Iout_req_y35 (Idec_req_y35 ), .Iout_req_y36 (Idec_req_y36 ), .Iout_req_y37 (Idec_req_y37 ), .Iout_req_y38 (Idec_req_y38 ), .Iout_req_y39 (Idec_req_y39 ), .Iout_req_y40 (Idec_req_y40 ), .Iout_req_y41 (Idec_req_y41 ), .Iout_req_y42 (Idec_req_y42 ), .Iout_req_y43 (Idec_req_y43 ), .Iout_req_y44 (Idec_req_y44 ), .Iout_req_y45 (Idec_req_y45 ), .Iout_req_y46 (Idec_req_y46 ), .Iout_req_y47 (Idec_req_y47 ), .Iout_req_y48 (Idec_req_y48 ), .Iout_req_y49 (Idec_req_y49 ), .Iout_req_y50 (Idec_req_y50 ), .Iout_req_y51 (Idec_req_y51 ), .Iout_req_y52 (Idec_req_y52 ), .Iout_req_y53 (Idec_req_y53 ), .Iout_req_y54 (Idec_req_y54 ), .Iout_req_y55 (Idec_req_y55 ), .Iout_req_y56 (Idec_req_y56 ), .Iout_req_y57 (Idec_req_y57 ), .Iout_req_y58 (Idec_req_y58 ), .Iout_req_y59 (Idec_req_y59 ), .Iout_req_y60 (Idec_req_y60 ), .Iout_req_y61 (Idec_req_y61 ), .Iout_req_y62 (Idec_req_y62 ), .Iout_req_y63 (Idec_req_y63 ), .Iout_req_y64 (Idec_req_y64 ), .Iout_req_y65 (Idec_req_y65 ), .Iout_req_y66 (Idec_req_y66 ), .Iout_req_y67 (Idec_req_y67 ), .Iout_req_y68 (Idec_req_y68 ), .Iout_req_y69 (Idec_req_y69 ), .Iout_req_y70 (Idec_req_y70 ), .Iout_req_y71 (Idec_req_y71 ), .Iout_req_y72 (Idec_req_y72 ), .Iout_req_y73 (Idec_req_y73 ), .Iout_req_y74 (Idec_req_y74 ), .Iout_req_y75 (Idec_req_y75 ), .Iout_req_y76 (Idec_req_y76 ), .Iout_req_y77 (Idec_req_y77 ), .Iout_req_y78 (Idec_req_y78 ), .Iout_req_y79 (Idec_req_y79 ), .Iout_req_y80 (Idec_req_y80 ), .Iout_req_y81 (Idec_req_y81 ), .Iout_req_y82 (Idec_req_y8
TBUF_X4 Isyn_x_AMZI_tbuf0  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI0 ), .en(Isyn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf1  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI1 ), .en(Isyn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf2  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI2 ), .en(Isyn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf3  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI3 ), .en(Isyn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf4  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI4 ), .en(Isyn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf5  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI5 ), .en(Isyn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf6  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI6 ), .en(Isyn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf7  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI7 ), .en(Isyn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf8  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI8 ), .en(Isyn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf9  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI9 ), .en(Isyn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf10  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI10 ), .en(Isyn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf11  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI11 ), .en(Isyn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf12  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI12 ), .en(Isyn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf13  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI13 ), .en(Isyn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf14  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI14 ), .en(Isyn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf15  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI15 ), .en(Isyn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf16  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI16 ), .en(Isyn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf17  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI17 ), .en(Isyn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf18  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI18 ), .en(Isyn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf19  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI19 ), .en(Isyn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf20  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI20 ), .en(Isyn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf21  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI21 ), .en(Isyn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf22  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI22 ), .en(Isyn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf23  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI23 ), .en(Isyn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf24  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI24 ), .en(Isyn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf25  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI25 ), .en(Isyn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf26  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI26 ), .en(Isyn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf27  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI27 ), .en(Isyn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf28  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI28 ), .en(Isyn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf29  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI29 ), .en(Isyn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf30  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI30 ), .en(Isyn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf31  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI31 ), .en(Isyn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf32  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI32 ), .en(Isyn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf33  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI33 ), .en(Isyn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf34  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI34 ), .en(Isyn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf35  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI35 ), .en(Isyn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf36  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI36 ), .en(Isyn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf37  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI37 ), .en(Isyn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf38  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI38 ), .en(Isyn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf39  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI39 ), .en(Isyn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf40  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI40 ), .en(Isyn_mon_x32 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf41  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI41 ), .en(Isyn_mon_x32 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf42  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI42 ), .en(Isyn_mon_x32 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf43  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI43 ), .en(Isyn_mon_x32 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf44  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI44 ), .en(Isyn_mon_x32 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf45  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI45 ), .en(Isyn_mon_x36 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf46  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI46 ), .en(Isyn_mon_x36 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf47  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI47 ), .en(Isyn_mon_x36 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf48  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI48 ), .en(Isyn_mon_x36 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf49  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI49 ), .en(Isyn_mon_x36 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf50  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI50 ), .en(Isyn_mon_x40 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf51  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI51 ), .en(Isyn_mon_x40 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf52  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI52 ), .en(Isyn_mon_x40 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf53  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI53 ), .en(Isyn_mon_x40 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf54  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI54 ), .en(Isyn_mon_x40 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf55  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI55 ), .en(Isyn_mon_x44 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf56  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI56 ), .en(Isyn_mon_x44 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf57  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI57 ), .en(Isyn_mon_x44 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf58  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI58 ), .en(Isyn_mon_x44 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf59  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI59 ), .en(Isyn_mon_x44 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf60  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI60 ), .en(Isyn_mon_x48 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf61  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI61 ), .en(Isyn_mon_x48 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf62  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI62 ), .en(Isyn_mon_x48 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf63  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI63 ), .en(Isyn_mon_x48 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf64  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI64 ), .en(Isyn_mon_x48 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf65  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI65 ), .en(Isyn_mon_x52 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf66  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI66 ), .en(Isyn_mon_x52 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf67  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI67 ), .en(Isyn_mon_x52 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf68  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI68 ), .en(Isyn_mon_x52 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf69  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI69 ), .en(Isyn_mon_x52 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf70  (.y(Isyn_AMZO_keeps0_y ), .a(Isyn_mon_AMZI70 ), .en(Isyn_mon_x56 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf71  (.y(Isyn_AMZO_keeps1_y ), .a(Isyn_mon_AMZI71 ), .en(Isyn_mon_x56 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf72  (.y(Isyn_AMZO_keeps2_y ), .a(Isyn_mon_AMZI72 ), .en(Isyn_mon_x56 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf73  (.y(Isyn_AMZO_keeps3_y ), .a(Isyn_mon_AMZI73 ), .en(Isyn_mon_x56 ), .vdd(vdd), .vss(vss));
TBUF_X4 Isyn_x_AMZI_tbuf74  (.y(Isyn_AMZO_keeps4_y ), .a(Isyn_mon_AMZI74 ), .en(Isyn_mon_x56 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_nrn_storage  (.in(Irsb_nrn_storage_in ), .Iout0 (Ireset_nrn_stge_BO0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_syn_storage  (.in(reset_syn_stge_BI), .Iout0 (Ireset_syn_stge_BO0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_nrn_hs  (.in(_reset_BX), .Iout0 (Ireset_nrn_hs_BO0 ), .vdd(vdd), .vss(vss));
KEEP Inrn_AMZO_keeps0  (.y(Inrn_AMZO_keeps0_y ), .vdd(vdd), .vss(vss));
KEEP Inrn_AMZO_keeps1  (.y(Inrn_AMZO_keeps1_y ), .vdd(vdd), .vss(vss));
KEEP Inrn_AMZO_keeps2  (.y(Inrn_AMZO_keeps2_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_36_748_4 Inrn_mon_y_buf  (.Iin0 (Inrn_mon_dec_y_out0 ), .Iin1 (Inrn_mon_dec_y_out1 ), .Iin2 (Inrn_mon_dec_y_out2 ), .Iin3 (Inrn_mon_dec_y_out3 ), .Iin4 (Inrn_mon_dec_y_out4 ), .Iin5 (Inrn_mon_dec_y_out5 ), .Iout0 (Inrn_mon_y0 ), .Iout1 (Inrn_mon_y1 ), .Iout2 (Inrn_mon_y2 ), .Iout3 (Inrn_mon_y3 ), .Iout4 (Inrn_mon_y4 ), .Iout5 (Inrn_mon_y5 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_360_713_4 Isyn_mon_x_buf  (.Iin0 (Isyn_mon_dec_x_out0 ), .Iin1 (Iands_devmon0_y ), .Iin2 (Isyn_mon_dec_x_out2 ), .Iin3 (Isyn_mon_x_buf_in3 ), .Iin4 (Isyn_mon_dec_x_out4 ), .Iin5 (Iands_devmon1_y ), .Iin6 (Isyn_mon_dec_x_out6 ), .Iin7 (Isyn_mon_x_buf_in7 ), .Iin8 (Isyn_mon_dec_x_out8 ), .Iin9 (Iands_devmon2_y ), .Iin10 (Isyn_mon_dec_x_out10 ), .Iin11 (Isyn_mon_x_buf_in11 ), .Iin12 (Isyn_mon_dec_x_out12 ), .Iin13 (Iands_devmon3_y ), .Iin14 (Isyn_mon_dec_x_out14 ), .Iin15 (Isyn_mon_x_buf_in15 ), .Iin16 (Isyn_mon_dec_x_out16 ), .Iin17 (Iands_devmon4_y ), .Iin18 (Isyn_mon_dec_x_out18 ), .Iin19 (Isyn_mon_x_buf_in19 ), .Iin20 (Isyn_mon_dec_x_out20 ), .Iin21 (Iands_devmon5_y ), .Iin22 (Isyn_mon_dec_x_out22 ), .Iin23 (Isyn_mon_x_buf_in23 ), .Iin24 (Isyn_mon_dec_x_out24 ), .Iin25 (Iands_devmon6_y ), .Iin26 (Isyn_mon_dec_x_out26 ), .Iin27 (Isyn_mon_x_buf_in27 ), .Iin28 (Isyn_mon_dec_x_out28 ), .Iin29 (Iands_devmon7_y ), .Iin30 (Isyn_mon_dec_x_out30 ), .Iin31 (Isyn_mon_x_buf_in31 ), .Iin32 (Isyn_mon_dec_x_out32 ), .Iin33 (Iands_devmon8_y ), .Iin34 (Isyn_mon_dec_x_out34 ), .Iin35 (Isyn_mon_x_buf_in35 ), .Iin36 (Isyn_mon_dec_x_out36 ), .Iin37 (Iands_devmon9_y ), .Iin38 (Isyn_mon_dec_x_out38 ), .Iin39 (Isyn_mon_x_buf_in39 ), .Iin40 (Isyn_mon_dec_x_out40 ), .Iin41 (Iands_devmon10_y ), .Iin42 (Isyn_mon_dec_x_out42 ), .Iin43 (Isyn_mon_x_buf_in43 ), .Iin44 (Isyn_mon_dec_x_out44 ), .Iin45 (Iands_devmon11_y ), .Iin46 (Isyn_mon_dec_x_out46 ), .Iin47 (Isyn_mon_x_buf_in47 ), .Iin48 (Isyn_mon_dec_x_out48 ), .Iin49 (Iands_devmon12_y ), .Iin50 (Isyn_mon_dec_x_out50 ), .Iin51 (Isyn_mon_x_buf_in51 ), .Iin52 (Isyn_mon_dec_x_out52 ), .Iin53 (Iands_devmon13_y ), .Iin54 (Isyn_mon_dec_x_out54 ), .Iin55 (Isyn_mon_x_buf_in55 ), .Iin56 (Isyn_mon_dec_x_out56 ), .Iin57 (Iands_devmon14_y ), .Iin58 (Isyn_mon_dec_x_out58 ), .Iin59 (Isyn_mon_x_buf_in59 ), .Iout0 (Isyn_mon_x0 ), .Iout1 (Isyn_mon_x1 ), .Iout2 (Isyn_mon_x2 ), .Iout3 (Isyn_mon_x3 ), .Iout4 (Isyn_mon_x4 ), .Iout5 (Isyn_mon_x5 ), .Iout6 (Isyn_mon_x6 ), .Iout7 (Isyn_mon_x7 ), .Iout8 (Isyn_mon_x8 ), .Iout9 (Isyn_mon_x9 ), .Iout10 (Isyn_mon_x10 ), .Iout11 (Isyn_mon_x11 ), .Iout12 (Isyn_mon_x12 ), .Iout13 (Isyn_mon_x13 ), .Iout14 (Isyn_mon_x14 ), .Iout15 (Isyn_mon_x15 ), .Iout16 (Isyn_mon_x16 ), .Iout17 (Isyn_mon_x17 ), .Iout18 (Isyn_mon_x18 ), .Iout19 (Isyn_mon_x19 ), .Iout20 (Isyn_mon_x20 ), .Iout21 (Isyn_mon_x21 ), .Iout22 (Isyn_mon_x22 ), .Iout23 (Isyn_mon_x23 ), .Iout24 (Isyn_mon_x24 ), .Iout25 (Isyn_mon_x25 ), .Iout26 (Isyn_mon_x26 ), .Iout27 (Isyn_mon_x27 ), .Iout28 (Isyn_mon_x28 ), .Iout29 (Isyn_mon_x29 ), .Iout30 (Isyn_mon_x30 ), .Iout31 (Isyn_mon_x31 ), .Iout32 (Isyn_mon_x32 ), .Iout33 (Isyn_mon_x33 ), .Iout34 (Isyn_mon_x34 ), .Iout35 (Isyn_mon_x35 ), .Iout36 (Isyn_mon_x36 ), .Iout37 (Isyn_mon_x37 ), .Iout38 (Isyn_mon_x38 ), .Iout39 (Isyn_mon_x39 ), .Iout40 (Isyn_mon_x40 ), .Iout41 (Isyn_mon_x41 ), .Iout42 (Isyn_mon_x42 ), .Iout43 (Isyn_mon_x43 ), .Iout44 (Isyn_mon_x44 ), .Iout45 (Isyn_mon_x45 ), .Iout46 (Isyn_mon_x46 ), .Iout47 (Isyn_mon_x47 ), .Iout48 (Isyn_mon_x48 ), .Iout49 (Isyn_mon_x49 ), .Iout50 (Isyn_mon_x50 ), .Iout51 (Isyn_mon_x51 ), .Iout52 (Isyn_mon_x52 ), .Iout53 (Isyn_mon_x53 ), .Iout54 (Isyn_mon_x54 ), .Iout55 (Isyn_mon_x55 ), .Iout56 (Isyn_mon_x56 ), .Iout57 (Isyn_mon_x57 ), .Iout58 (Isyn_mon_x58 ), .Iout59 (Isyn_mon_x59 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_330_713_4 Inrn_mon_x_buf  (.Iin0 (Inrn_mon_dec_x_out0 ), .Iin1 (Inrn_mon_dec_x_out1 ), .Iin2 (Inrn_mon_dec_x_out2 ), .Iin3 (Inrn_mon_dec_x_out3 ), .Iin4 (Inrn_mon_dec_x_out4 ), .Iin5 (Inrn_mon_dec_x_out5 ), .Iin6 (Inrn_mon_dec_x_out6 ), .Iin7 (Inrn_mon_dec_x_out7 ), .Iin8 (Inrn_mon_dec_x_out8 ), .Iin9 (Inrn_mon_dec_x_out9 ), .Iin10 (Inrn_mon_dec_x_out10 ), .Iin11 (Inrn_mon_dec_x_out11 ), .Iin12 (Inrn_mon_dec_x_out12 ), .Iin13 (Inrn_mon_dec_x_out13 ), .Iin14 (Inrn_mon_dec_x_out14 ), .Iin15 (Inrn_mon_dec_x_out15 ), .Iin16 (Inrn_mon_dec_x_out16 ), .Iin17 (Inrn_mon_dec_x_out17 ), .Iin18 (Inrn_mon_dec_x_out18 ), .Iin19 (Inrn_mon_dec_x_out19 ), .Iin20 (Inrn_mon_dec_x_out20 ), .Iin21 (Inrn_mon_dec_x_out21 ), .Iin22 (Inrn_mon_dec_x_out22 ), .Iin23 (Inrn_mon_dec_x_out23 ), .Iin24 (Inrn_mon_dec_x_out24 ), .Iin25 (Inrn_mon_dec_x_out25 ), .Iin26 (Inrn_mon_dec_x_out26 ), .Iin27 (Inrn_mon_dec_x_out27 ), .Iin28 (Inrn_mon_dec_x_out28 ), .Iin29 (Inrn_mon_dec_x_out29 ), .Iout0 (Inrn_mon_x0 ), .Iout1 (Inrn_mon_x1 ), .Iout2 (Inrn_mon_x2 ), .Iout3 (Inrn_mon_x3 ), .Iout4 (Inrn_mon_x4 ), .Iout5 (Inrn_mon_x5 ), .Iout6 (Inrn_mon_x6 ), .Iout7 (Inrn_mon_x7 ), .Iout8 (Inrn_mon_x8 ), .Iout9 (Inrn_mon_x9 ), .Iout10 (Inrn_mon_x10 ), .Iout11 (Inrn_mon_x11 ), .Iout12 (Inrn_mon_x12 ), .Iout13 (Inrn_mon_x13 ), .Iout14 (Inrn_mon_x14 ), .Iout15 (Inrn_mon_x15 ), .Iout16 (Inrn_mon_x16 ), .Iout17 (Inrn_mon_x17 ), .Iout18 (Inrn_mon_x18 ), .Iout19 (Inrn_mon_x19 ), .Iout20 (Inrn_mon_x20 ), .Iout21 (Inrn_mon_x21 ), .Iout22 (Inrn_mon_x22 ), .Iout23 (Inrn_mon_x23 ), .Iout24 (Inrn_mon_x24 ), .Iout25 (Inrn_mon_x25 ), .Iout26 (Inrn_mon_x26 ), .Iout27 (Inrn_mon_x27 ), .Iout28 (Inrn_mon_x28 ), .Iout29 (Inrn_mon_x29 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0append_37_724_70_4 Iappend_enc  (.Iin_d_d0_d0 (Iappend_enc_in_d_d0_d0 ), .Iin_d_d0_d1 (Iappend_enc_in_d_d0_d1 ), .Iin_d_d1_d0 (Iappend_enc_in_d_d1_d0 ), .Iin_d_d1_d1 (Iappend_enc_in_d_d1_d1 ), .Iin_d_d2_d0 (Iappend_enc_in_d_d2_d0 ), .Iin_d_d2_d1 (Iappend_enc_in_d_d2_d1 ), .Iin_d_d3_d0 (Iappend_enc_in_d_d3_d0 ), .Iin_d_d3_d1 (Iappend_enc_in_d_d3_d1 ), .Iin_d_d4_d0 (Iappend_enc_in_d_d4_d0 ), .Iin_d_d4_d1 (Iappend_enc_in_d_d4_d1 ), .Iin_d_d5_d0 (Iappend_enc_in_d_d5_d0 ), .Iin_d_d5_d1 (Iappend_enc_in_d_d5_d1 ), .Iin_d_d6_d0 (Iappend_enc_in_d_d6_d0 ), .Iin_d_d6_d1 (Iappend_enc_in_d_d6_d1 ), .Iout_d_d7_d0 (Iappend_enc_out_d_d7_d0 ), .Iout_d_d7_d1 (Iappend_enc_out_d_d7_d1 ), .Iout_d_d8_d1 (Iappend_enc_out_d_d8_d1 ), .Iout_d_d9_d1 (Iappend_enc_out_d_d9_d1 ), .Iout_d_d10_d1 (Iappend_enc_out_d_d10_d1 ), .Iout_d_d11_d1 (Iappend_enc_out_d_d11_d1 ), .Iout_d_d12_d1 (Iappend_enc_out_d_d12_d1 ), .Iout_d_d13_d1 (Iappend_enc_out_d_d13_d1 ), .Iout_d_d14_d1 (Iappend_enc_out_d_d14_d1 ), .Iout_d_d15_d1 (Iappend_enc_out_d_d15_d1 ), .Iout_d_d16_d1 (Iappend_enc_out_d_d16_d1 ), .Iout_d_d17_d1 (Iappend_enc_out_d_d17_d1 ), .Iout_d_d18_d1 (Iappend_enc_out_d_d18_d1 ), .Iout_d_d19_d1 (Iappend_enc_out_d_d19_d1 ), .Iout_d_d20_d1 (Iappend_enc_out_d_d20_d1 ), .Iout_d_d21_d1 (Iappend_enc_out_d_d21_d1 ), .Iout_d_d22_d1 (Iappend_enc_out_d_d22_d1 ), .Iout_d_d23_d1 (Iappend_enc_out_d_d23_d1 ), .Iout_d_d24_d1 (Iappend_enc_out_d_d24_d1 ), .Iout_d_d25_d1 (Iappend_enc_out_d_d25_d1 ), .Iout_d_d26_d1 (Iappend_enc_out_d_d26_d1 ), .Iout_d_d27_d1 (Iappend_enc_out_d_d27_d1 ), .Iout_d_d28_d1 (Iappend_enc_out_d_d28_d1 ), .Iout_d_d29_d1 (Iappend_enc_out_d_d29_d1 ), .Iout_d_d30_d1 (Iappend_enc_out_d_d30_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0demux__bit__msb_330_4 I_demux  (.Iin_d_d0_d0 (I_demux_in_d_d0_d0 ), .Iin_d_d0_d1 (I_demux_in_d_d0_d1 ), .Iin_d_d1_d0 (I_demux_in_d_d1_d0 ), .Iin_d_d1_d1 (I_demux_in_d_d1_d1 ), .Iin_d_d2_d0 (I_demux_in_d_d2_d0 ), .Iin_d_d2_d1 (I_demux_in_d_d2_d1 ), .Iin_d_d3_d0 (I_demux_in_d_d3_d0 ), .Iin_d_d3_d1 (I_demux_in_d_d3_d1 ), .Iin_d_d4_d0 (I_demux_in_d_d4_d0 ), .Iin_d_d4_d1 (I_demux_in_d_d4_d1 ), .Iin_d_d5_d0 (I_demux_in_d_d5_d0 ), .Iin_d_d5_d1 (I_demux_in_d_d5_d1 ), .Iin_d_d6_d0 (I_demux_in_d_d6_d0 ), .Iin_d_d6_d1 (I_demux_in_d_d6_d1 ), .Iin_d_d7_d0 (I_demux_in_d_d7_d0 ), .Iin_d_d7_d1 (I_demux_in_d_d7_d1 ), .Iin_d_d8_d0 (I_demux_in_d_d8_d0 ), .Iin_d_d8_d1 (I_demux_in_d_d8_d1 ), .Iin_d_d9_d0 (I_demux_in_d_d9_d0 ), .Iin_d_d9_d1 (I_demux_in_d_d9_d1 ), .Iin_d_d10_d0 (I_demux_in_d_d10_d0 ), .Iin_d_d10_d1 (I_demux_in_d_d10_d1 ), .Iin_d_d11_d0 (I_demux_in_d_d11_d0 ), .Iin_d_d11_d1 (I_demux_in_d_d11_d1 ), .Iin_d_d12_d0 (I_demux_in_d_d12_d0 ), .Iin_d_d12_d1 (I_demux_in_d_d12_d1 ), .Iin_d_d13_d0 (I_demux_in_d_d13_d0 ), .Iin_d_d13_d1 (I_demux_in_d_d13_d1 ), .Iin_d_d14_d0 (I_demux_in_d_d14_d0 ), .Iin_d_d14_d1 (I_demux_in_d_d14_d1 ), .Iin_d_d15_d0 (I_demux_in_d_d15_d0 ), .Iin_d_d15_d1 (I_demux_in_d_d15_d1 ), .Iin_d_d16_d0 (I_demux_in_d_d16_d0 ), .Iin_d_d16_d1 (I_demux_in_d_d16_d1 ), .Iin_d_d17_d0 (I_demux_in_d_d17_d0 ), .Iin_d_d17_d1 (I_demux_in_d_d17_d1 ), .Iin_d_d18_d0 (I_demux_in_d_d18_d0 ), .Iin_d_d18_d1 (I_demux_in_d_d18_d1 ), .Iin_d_d19_d0 (I_demux_in_d_d19_d0 ), .Iin_d_d19_d1 (I_demux_in_d_d19_d1 ), .Iin_d_d20_d0 (I_demux_in_d_d20_d0 ), .Iin_d_d20_d1 (I_demux_in_d_d20_d1 ), .Iin_d_d21_d0 (I_demux_in_d_d21_d0 ), .Iin_d_d21_d1 (I_demux_in_d_d21_d1 ), .Iin_d_d22_d0 (I_demux_in_d_d22_d0 ), .Iin_d_d22_d1 (I_demux_in_d_d22_d1 ), .Iin_d_d23_d0 (I_demux_in_d_d23_d0 ), .Iin_d_d23_d1 (I_demux_in_d_d23_d1 ), .Iin_d_d24_d0 (I_demux_in_d_d24_d0 ), .Iin_d_d24_d1 (I_demux_in_d_d24_d1 ), .Iin_d_d25_d0 (I_demux_in_d_d25_d0 ), .Iin_d_d25_d1 (I_demux_in_d_d25_d1 ), .Iin_d_d26_d0 (I_demux_in_d_d26_d0 ), .Iin_d_d26_d1 (I_demux_in_d_d26_d1 ), .Iin_d_d27_d0 (I_demux_in_d_d27_d0 ), .Iin_d_d27_d1 (I_demux_in_d_d27_d1 ), .Iin_d_d28_d0 (I_demux_in_d_d28_d0 ), .Iin_d_d28_d1 (I_demux_in_d_d28_d1 ), .Iin_d_d29_d0 (I_demux_in_d_d29_d0 ), .Iin_d_d29_d1 (I_demux_in_d_d29_d1 ), .Iin_d_d30_d0 (I_demux_in_d_d30_d0 ), .Iin_d_d30_d1 (I_demux_in_d_d30_d1 ), .Iin_a (I_demux_in_a ), .Iin_v (I_demux_in_v ), .Iout1_d_d0_d0 (I_demux_out1_d_d0_d0 ), .Iout1_d_d0_d1 (I_demux_out1_d_d0_d1 ), .Iout1_d_d1_d0 (I_demux_out1_d_d1_d0 ), .Iout1_d_d1_d1 (I_demux_out1_d_d1_d1 ), .Iout1_d_d2_d0 (I_demux_out1_d_d2_d0 ), .Iout1_d_d2_d1 (I_demux_out1_d_d2_d1 ), .Iout1_d_d3_d0 (I_demux_out1_d_d3_d0 ), .Iout1_d_d3_d1 (I_demux_out1_d_d3_d1 ), .Iout1_d_d4_d0 (I_demux_out1_d_d4_d0 ), .Iout1_d_d4_d1 (I_demux_out1_d_d4_d1 ), .Iout1_d_d5_d0 (I_demux_out1_d_d5_d0 ), .Iout1_d_d5_d1 (I_demux_out1_d_d5_d1 ), .Iout1_d_d6_d0 (I_demux_out1_d_d6_d0 ), .Iout1_d_d6_d1 (I_demux_out1_d_d6_d1 ), .Iout1_d_d7_d0 (I_demux_out1_d_d7_d0 ), .Iout1_d_d7_d1 (I_demux_out1_d_d7_d1 ), .Iout1_d_d8_d0 (I_demux_out1_d_d8_d0 ), .Iout1_d_d8_d1 (I_demux_out1_d_d8_d1 ), .Iout1_d_d9_d0 (I_demux_out1_d_d9_d0 ), .Iout1_d_d9_d1 (I_demux_out1_d_d9_d1 ), .Iout1_d_d10_d0 (I_demux_out1_d_d10_d0 ), .Iout1_d_d10_d1 (I_demux_out1_d_d10_d1 ), .Iout1_d_d11_d0 (I_demux_out1_d_d11_d0 ), .Iout1_d_d11_d1 (I_demux_out1_d_d11_d1 ), .Iout1_d_d12_d0 (I_demux_out1_d_d12_d0 ), .Iout1_d_d12_d1 (I_demux_out1_d_d12_d1 ), .Iout1_d_d13_d0 (I_demux_out1_d_d13_d0 ), .Iout1_d_d13_d1 (I_demux_out1_d_d13_d1 ), .Iout1_d_d14_d0 (I_demux_out1_d_d14_d0 ), .Iout1_d_d14_d1 (I_demux_out1_d_d14_d1 ), .Iout1_d_d15_d0 (I_demux_out1_d_d15_d0 ), .Iout1_d_d15_d1 (I_demux_out1_d_d15_d1 ), .Iout1_d_d16_d0 (I_demux_out1_d_d16_d0 ), .Iout1_d_d16_d1 (I_demux_out1_d_d16_d1 ), .Iout1_d_d17_d0 (I_demux_out1_d_d17_d0 ), .Iout1_d_d17_d1 (I_demux_out1_d_d17_d1 ), .Iout1_d_d18_d0 (I_demux_out1_d_d18_d0 ), .Iout1_d_d18_d1 (I_demux_out1_d_d18_d1 ), .Iout1_d_d19_d0 (I_demux_out1_d_d19_d0 ), .Iout1_d_d19_d1 (I_demux_out1_d_d19_d1 ), .Iout1_d_d20_d0 (I_demux_out1_d_
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_33_731_4 Isb_nrn_EFO  (.Iin0 (Ireg_data5_d0_d1 ), .Iin1 (Ireg_data5_d1_d1 ), .Iin2 (Ireg_data5_d2_d1 ), .Iout0 (Inrn_flags_EFO0 ), .Iout1 (Inrn_flags_EFO1 ), .Iout2 (Inrn_flags_EFO2 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv0  (.y(Isyn_mon_x_buf_in3 ), .a(Isyn_mon_dec_x_out3 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv1  (.y(Isyn_mon_x_buf_in7 ), .a(Isyn_mon_dec_x_out7 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv2  (.y(Isyn_mon_x_buf_in11 ), .a(Isyn_mon_dec_x_out11 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv3  (.y(Isyn_mon_x_buf_in15 ), .a(Isyn_mon_dec_x_out15 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv4  (.y(Isyn_mon_x_buf_in19 ), .a(Isyn_mon_dec_x_out19 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv5  (.y(Isyn_mon_x_buf_in23 ), .a(Isyn_mon_dec_x_out23 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv6  (.y(Isyn_mon_x_buf_in27 ), .a(Isyn_mon_dec_x_out27 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv7  (.y(Isyn_mon_x_buf_in31 ), .a(Isyn_mon_dec_x_out31 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv8  (.y(Isyn_mon_x_buf_in35 ), .a(Isyn_mon_dec_x_out35 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv9  (.y(Isyn_mon_x_buf_in39 ), .a(Isyn_mon_dec_x_out39 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv10  (.y(Isyn_mon_x_buf_in43 ), .a(Isyn_mon_dec_x_out43 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv11  (.y(Isyn_mon_x_buf_in47 ), .a(Isyn_mon_dec_x_out47 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv12  (.y(Isyn_mon_x_buf_in51 ), .a(Isyn_mon_dec_x_out51 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv13  (.y(Isyn_mon_x_buf_in55 ), .a(Isyn_mon_dec_x_out55 ), .vdd(vdd), .vss(vss));
INV_X1 Isyn_targ_set_high_inv14  (.y(Isyn_mon_x_buf_in59 ), .a(Isyn_mon_dec_x_out59 ), .vdd(vdd), .vss(vss));
INV_X1 Idly_cfg_inverters0  (.y(Idecoder_dly_cfg0 ), .a(Ireg_data0_d1_d1 ), .vdd(vdd), .vss(vss));
INV_X1 Idly_cfg_inverters1  (.y(Idecoder_dly_cfg1 ), .a(Ireg_data0_d2_d1 ), .vdd(vdd), .vss(vss));
INV_X1 Idly_cfg_inverters2  (.y(Idecoder_dly_cfg2 ), .a(Ireg_data0_d3_d1 ), .vdd(vdd), .vss(vss));
INV_X1 Idly_cfg_inverters3  (.y(Idecoder_dly_cfg3 ), .a(Ireg_data0_d4_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4 Isyn_mon_dec_x  (.Iin_d0_d0 (Ireg_data3_d0_d0 ), .Iin_d0_d1 (Ireg_data3_d0_d1 ), .Iin_d1_d0 (Ireg_data3_d1_d0 ), .Iin_d1_d1 (Ireg_data3_d1_d1 ), .Iin_d2_d0 (Ireg_data3_d2_d0 ), .Iin_d2_d1 (Ireg_data3_d2_d1 ), .Iin_d3_d0 (Ireg_data3_d3_d0 ), .Iin_d3_d1 (Ireg_data3_d3_d1 ), .Iin_d4_d0 (Ireg_data3_d4_d0 ), .Iin_d4_d1 (Ireg_data3_d4_d1 ), .Iin_d5_d0 (Ireg_data3_d5_d0 ), .Iin_d5_d1 (Ireg_data3_d5_d1 ), .en(Ireg_data1_d1_d1 ), .Iout0 (Isyn_mon_dec_x_out0 ), .Iout1 (Iands_devmon0_a ), .Iout2 (Isyn_mon_dec_x_out2 ), .Iout3 (Isyn_mon_dec_x_out3 ), .Iout4 (Isyn_mon_dec_x_out4 ), .Iout5 (Iands_devmon1_a ), .Iout6 (Isyn_mon_dec_x_out6 ), .Iout7 (Isyn_mon_dec_x_out7 ), .Iout8 (Isyn_mon_dec_x_out8 ), .Iout9 (Iands_devmon2_a ), .Iout10 (Isyn_mon_dec_x_out10 ), .Iout11 (Isyn_mon_dec_x_out11 ), .Iout12 (Isyn_mon_dec_x_out12 ), .Iout13 (Iands_devmon3_a ), .Iout14 (Isyn_mon_dec_x_out14 ), .Iout15 (Isyn_mon_dec_x_out15 ), .Iout16 (Isyn_mon_dec_x_out16 ), .Iout17 (Iands_devmon4_a ), .Iout18 (Isyn_mon_dec_x_out18 ), .Iout19 (Isyn_mon_dec_x_out19 ), .Iout20 (Isyn_mon_dec_x_out20 ), .Iout21 (Iands_devmon5_a ), .Iout22 (Isyn_mon_dec_x_out22 ), .Iout23 (Isyn_mon_dec_x_out23 ), .Iout24 (Isyn_mon_dec_x_out24 ), .Iout25 (Iands_devmon6_a ), .Iout26 (Isyn_mon_dec_x_out26 ), .Iout27 (Isyn_mon_dec_x_out27 ), .Iout28 (Isyn_mon_dec_x_out28 ), .Iout29 (Iands_devmon7_a ), .Iout30 (Isyn_mon_dec_x_out30 ), .Iout31 (Isyn_mon_dec_x_out31 ), .Iout32 (Isyn_mon_dec_x_out32 ), .Iout33 (Iands_devmon8_a ), .Iout34 (Isyn_mon_dec_x_out34 ), .Iout35 (Isyn_mon_dec_x_out35 ), .Iout36 (Isyn_mon_dec_x_out36 ), .Iout37 (Iands_devmon9_a ), .Iout38 (Isyn_mon_dec_x_out38 ), .Iout39 (Isyn_mon_dec_x_out39 ), .Iout40 (Isyn_mon_dec_x_out40 ), .Iout41 (Iands_devmon10_a ), .Iout42 (Isyn_mon_dec_x_out42 ), .Iout43 (Isyn_mon_dec_x_out43 ), .Iout44 (Isyn_mon_dec_x_out44 ), .Iout45 (Iands_devmon11_a ), .Iout46 (Isyn_mon_dec_x_out46 ), .Iout47 (Isyn_mon_dec_x_out47 ), .Iout48 (Isyn_mon_dec_x_out48 ), .Iout49 (Iands_devmon12_a ), .Iout50 (Isyn_mon_dec_x_out50 ), .Iout51 (Isyn_mon_dec_x_out51 ), .Iout52 (Isyn_mon_dec_x_out52 ), .Iout53 (Iands_devmon13_a ), .Iout54 (Isyn_mon_dec_x_out54 ), .Iout55 (Isyn_mon_dec_x_out55 ), .Iout56 (Isyn_mon_dec_x_out56 ), .Iout57 (Iands_devmon14_a ), .Iout58 (Isyn_mon_dec_x_out58 ), .Iout59 (Isyn_mon_dec_x_out59 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4 Inrn_mon_dec_y  (.Iin_d0_d0 (Ireg_data2_d5_d0 ), .Iin_d0_d1 (Ireg_data2_d5_d1 ), .Iin_d1_d0 (Ireg_data2_d6_d0 ), .Iin_d1_d1 (Ireg_data2_d6_d1 ), .Iin_d2_d0 (Ireg_data2_d7_d0 ), .Iin_d2_d1 (Ireg_data2_d7_d1 ), .en(Ireg_data1_d0_d1 ), .Iout0 (Inrn_mon_dec_y_out0 ), .Iout1 (Inrn_mon_dec_y_out1 ), .Iout2 (Inrn_mon_dec_y_out2 ), .Iout3 (Inrn_mon_dec_y_out3 ), .Iout4 (Inrn_mon_dec_y_out4 ), .Iout5 (Inrn_mon_dec_y_out5 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0slice__data_330_70_713_4 Islice_pre_dec  (.Iin_d_d0_d0 (I_demux_out1_d_d0_d0 ), .Iin_d_d0_d1 (I_demux_out1_d_d0_d1 ), .Iin_d_d1_d0 (I_demux_out1_d_d1_d0 ), .Iin_d_d1_d1 (I_demux_out1_d_d1_d1 ), .Iin_d_d2_d0 (I_demux_out1_d_d2_d0 ), .Iin_d_d2_d1 (I_demux_out1_d_d2_d1 ), .Iin_d_d3_d0 (I_demux_out1_d_d3_d0 ), .Iin_d_d3_d1 (I_demux_out1_d_d3_d1 ), .Iin_d_d4_d0 (I_demux_out1_d_d4_d0 ), .Iin_d_d4_d1 (I_demux_out1_d_d4_d1 ), .Iin_d_d5_d0 (I_demux_out1_d_d5_d0 ), .Iin_d_d5_d1 (I_demux_out1_d_d5_d1 ), .Iin_d_d6_d0 (I_demux_out1_d_d6_d0 ), .Iin_d_d6_d1 (I_demux_out1_d_d6_d1 ), .Iin_d_d7_d0 (I_demux_out1_d_d7_d0 ), .Iin_d_d7_d1 (I_demux_out1_d_d7_d1 ), .Iin_d_d8_d0 (I_demux_out1_d_d8_d0 ), .Iin_d_d8_d1 (I_demux_out1_d_d8_d1 ), .Iin_d_d9_d0 (I_demux_out1_d_d9_d0 ), .Iin_d_d9_d1 (I_demux_out1_d_d9_d1 ), .Iin_d_d10_d0 (I_demux_out1_d_d10_d0 ), .Iin_d_d10_d1 (I_demux_out1_d_d10_d1 ), .Iin_d_d11_d0 (I_demux_out1_d_d11_d0 ), .Iin_d_d11_d1 (I_demux_out1_d_d11_d1 ), .Iin_d_d12_d0 (I_demux_out1_d_d12_d0 ), .Iin_d_d12_d1 (I_demux_out1_d_d12_d1 ), .Iin_d_d13_d0 (I_demux_out1_d_d13_d0 ), .Iin_d_d13_d1 (I_demux_out1_d_d13_d1 ), .Iin_d_d14_d0 (I_demux_out1_d_d14_d0 ), .Iin_d_d14_d1 (I_demux_out1_d_d14_d1 ), .Iin_d_d15_d0 (I_demux_out1_d_d15_d0 ), .Iin_d_d15_d1 (I_demux_out1_d_d15_d1 ), .Iin_d_d16_d0 (I_demux_out1_d_d16_d0 ), .Iin_d_d16_d1 (I_demux_out1_d_d16_d1 ), .Iin_d_d17_d0 (I_demux_out1_d_d17_d0 ), .Iin_d_d17_d1 (I_demux_out1_d_d17_d1 ), .Iin_d_d18_d0 (I_demux_out1_d_d18_d0 ), .Iin_d_d18_d1 (I_demux_out1_d_d18_d1 ), .Iin_d_d19_d0 (I_demux_out1_d_d19_d0 ), .Iin_d_d19_d1 (I_demux_out1_d_d19_d1 ), .Iin_d_d20_d0 (I_demux_out1_d_d20_d0 ), .Iin_d_d20_d1 (I_demux_out1_d_d20_d1 ), .Iin_d_d21_d0 (I_demux_out1_d_d21_d0 ), .Iin_d_d21_d1 (I_demux_out1_d_d21_d1 ), .Iin_d_d22_d0 (I_demux_out1_d_d22_d0 ), .Iin_d_d22_d1 (I_demux_out1_d_d22_d1 ), .Iin_d_d23_d0 (I_demux_out1_d_d23_d0 ), .Iin_d_d23_d1 (I_demux_out1_d_d23_d1 ), .Iin_d_d24_d0 (I_demux_out1_d_d24_d0 ), .Iin_d_d24_d1 (I_demux_out1_d_d24_d1 ), .Iin_d_d25_d0 (I_demux_out1_d_d25_d0 ), .Iin_d_d25_d1 (I_demux_out1_d_d25_d1 ), .Iin_d_d26_d0 (I_demux_out1_d_d26_d0 ), .Iin_d_d26_d1 (I_demux_out1_d_d26_d1 ), .Iin_d_d27_d0 (I_demux_out1_d_d27_d0 ), .Iin_d_d27_d1 (I_demux_out1_d_d27_d1 ), .Iin_d_d28_d0 (I_demux_out1_d_d28_d0 ), .Iin_d_d28_d1 (I_demux_out1_d_d28_d1 ), .Iin_d_d29_d0 (I_demux_out1_d_d29_d0 ), .Iin_d_d29_d1 (I_demux_out1_d_d29_d1 ), .Iin_a (I_demux_out1_a ), .Iin_v (I_demux_out1_v ), .Iout_a (Ififo_dmx2dec_in_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_33_740_4 Inrn_mon_AMZO_sb  (.Iin0 (Inrn_AMZO_keeps0_y ), .Iin1 (Inrn_AMZO_keeps1_y ), .Iin2 (Inrn_AMZO_keeps2_y ), .Iout0 (Inrn_mon_AMZO0 ), .Iout1 (Inrn_mon_AMZO1 ), .Iout2 (Inrn_mon_AMZO2 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_35_740_4 Isyn_mon_AMZO_sb  (.Iin0 (Isyn_AMZO_keeps0_y ), .Iin1 (Isyn_AMZO_keeps1_y ), .Iin2 (Isyn_AMZO_keeps2_y ), .Iin3 (Isyn_AMZO_keeps3_y ), .Iin4 (Isyn_AMZO_keeps4_y ), .Iout0 (Isyn_mon_AMZO0 ), .Iout1 (Isyn_mon_AMZO1 ), .Iout2 (Isyn_mon_AMZO2 ), .Iout3 (Isyn_mon_AMZO3 ), .Iout4 (Isyn_mon_AMZO4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0register__wr__array_36_723_78_4 Iregister  (.Iin_d_d0_d0 (Iregister_in_d_d0_d0 ), .Iin_d_d0_d1 (Iregister_in_d_d0_d1 ), .Iin_d_d1_d0 (Iregister_in_d_d1_d0 ), .Iin_d_d1_d1 (Iregister_in_d_d1_d1 ), .Iin_d_d2_d0 (Iregister_in_d_d2_d0 ), .Iin_d_d2_d1 (Iregister_in_d_d2_d1 ), .Iin_d_d3_d0 (Iregister_in_d_d3_d0 ), .Iin_d_d3_d1 (Iregister_in_d_d3_d1 ), .Iin_d_d4_d0 (Iregister_in_d_d4_d0 ), .Iin_d_d4_d1 (Iregister_in_d_d4_d1 ), .Iin_d_d5_d0 (Iregister_in_d_d5_d0 ), .Iin_d_d5_d1 (Iregister_in_d_d5_d1 ), .Iin_d_d6_d0 (Iregister_in_d_d6_d0 ), .Iin_d_d6_d1 (Iregister_in_d_d6_d1 ), .Iin_d_d7_d0 (Iregister_in_d_d7_d0 ), .Iin_d_d7_d1 (Iregister_in_d_d7_d1 ), .Iin_d_d8_d0 (Iregister_in_d_d8_d0 ), .Iin_d_d8_d1 (Iregister_in_d_d8_d1 ), .Iin_d_d9_d0 (Iregister_in_d_d9_d0 ), .Iin_d_d9_d1 (Iregister_in_d_d9_d1 ), .Iin_d_d10_d0 (Iregister_in_d_d10_d0 ), .Iin_d_d10_d1 (Iregister_in_d_d10_d1 ), .Iin_d_d11_d0 (Iregister_in_d_d11_d0 ), .Iin_d_d11_d1 (Iregister_in_d_d11_d1 ), .Iin_d_d12_d0 (Iregister_in_d_d12_d0 ), .Iin_d_d12_d1 (Iregister_in_d_d12_d1 ), .Iin_d_d13_d0 (Iregister_in_d_d13_d0 ), .Iin_d_d13_d1 (Iregister_in_d_d13_d1 ), .Iin_d_d14_d0 (Iregister_in_d_d14_d0 ), .Iin_d_d14_d1 (Iregister_in_d_d14_d1 ), .Iin_d_d15_d0 (Iregister_in_d_d15_d0 ), .Iin_d_d15_d1 (Iregister_in_d_d15_d1 ), .Iin_d_d16_d0 (Iregister_in_d_d16_d0 ), .Iin_d_d16_d1 (Iregister_in_d_d16_d1 ), .Iin_d_d17_d0 (Iregister_in_d_d17_d0 ), .Iin_d_d17_d1 (Iregister_in_d_d17_d1 ), .Iin_d_d18_d0 (Iregister_in_d_d18_d0 ), .Iin_d_d18_d1 (Iregister_in_d_d18_d1 ), .Iin_d_d19_d0 (Iregister_in_d_d19_d0 ), .Iin_d_d19_d1 (Iregister_in_d_d19_d1 ), .Iin_d_d20_d0 (Iregister_in_d_d20_d0 ), .Iin_d_d20_d1 (Iregister_in_d_d20_d1 ), .Iin_d_d21_d0 (Iregister_in_d_d21_d0 ), .Iin_d_d21_d1 (Iregister_in_d_d21_d1 ), .Iin_d_d22_d0 (Iregister_in_d_d22_d0 ), .Iin_d_d22_d1 (Iregister_in_d_d22_d1 ), .Iin_d_d23_d0 (Iregister_in_d_d23_d0 ), .Iin_d_d23_d1 (Iregister_in_d_d23_d1 ), .Iin_d_d24_d0 (Iregister_in_d_d24_d0 ), .Iin_d_d24_d1 (Iregister_in_d_d24_d1 ), .Iin_d_d25_d0 (Iregister_in_d_d25_d0 ), .Iin_d_d25_d1 (Iregister_in_d_d25_d1 ), .Iin_d_d26_d0 (Iregister_in_d_d26_d0 ), .Iin_d_d26_d1 (Iregister_in_d_d26_d1 ), .Iin_d_d27_d0 (Iregister_in_d_d27_d0 ), .Iin_d_d27_d1 (Iregister_in_d_d27_d1 ), .Iin_d_d28_d0 (Iregister_in_d_d28_d0 ), .Iin_d_d28_d1 (Iregister_in_d_d28_d1 ), .Iin_d_d29_d0 (Iregister_in_d_d29_d0 ), .Iin_d_d29_d1 (Iregister_in_d_d29_d1 ), .Iin_a (Iregister_in_a ), .Iin_v (Iregister_in_v ), .Idata0_d0_d0 (Ireg_data0_d0_d0 ), .Idata0_d0_d1 (Ireg_data0_d0_d1 ), .Idata0_d1_d0 (Ireg_data0_d1_d0 ), .Idata0_d1_d1 (Ireg_data0_d1_d1 ), .Idata0_d2_d0 (Ireg_data0_d2_d0 ), .Idata0_d2_d1 (Ireg_data0_d2_d1 ), .Idata0_d3_d0 (Ireg_data0_d3_d0 ), .Idata0_d3_d1 (Ireg_data0_d3_d1 ), .Idata0_d4_d0 (Ireg_data0_d4_d0 ), .Idata0_d4_d1 (Ireg_data0_d4_d1 ), .Idata0_d5_d0 (Ireg_data0_d5_d0 ), .Idata0_d5_d1 (Ireg_data0_d5_d1 ), .Idata0_d6_d0 (Ireg_data0_d6_d0 ), .Idata0_d6_d1 (Ireg_data0_d6_d1 ), .Idata0_d7_d0 (Ireg_data0_d7_d0 ), .Idata0_d7_d1 (Ireg_data0_d7_d1 ), .Idata0_d8_d0 (Ireg_data0_d8_d0 ), .Idata0_d8_d1 (Ireg_data0_d8_d1 ), .Idata0_d9_d0 (Ireg_data0_d9_d0 ), .Idata0_d9_d1 (Ireg_data0_d9_d1 ), .Idata0_d10_d0 (Ireg_data0_d10_d0 ), .Idata0_d10_d1 (Ireg_data0_d10_d1 ), .Idata0_d11_d0 (Ireg_data0_d11_d0 ), .Idata0_d11_d1 (Ireg_data0_d11_d1 ), .Idata0_d12_d0 (Ireg_data0_d12_d0 ), .Idata0_d12_d1 (Ireg_data0_d12_d1 ), .Idata0_d13_d0 (Ireg_data0_d13_d0 ), .Idata0_d13_d1 (Ireg_data0_d13_d1 ), .Idata0_d14_d0 (Ireg_data0_d14_d0 ), .Idata0_d14_d1 (Ireg_data0_d14_d1 ), .Idata0_d15_d0 (Ireg_data0_d15_d0 ), .Idata0_d15_d1 (Ireg_data0_d15_d1 ), .Idata0_d16_d0 (Ireg_data0_d16_d0 ), .Idata0_d16_d1 (Ireg_data0_d16_d1 ), .Idata0_d17_d0 (Ireg_data0_d17_d0 ), .Idata0_d17_d1 (Ireg_data0_d17_d1 ), .Idata0_d18_d0 (Ireg_data0_d18_d0 ), .Idata0_d18_d1 (Ireg_data0_d18_d1 ), .Idata0_d19_d0 (Ireg_data0_d19_d0 ), .Idata0_d19_d1 (Ireg_data0_d19_d1 ), .Idata0_d20_d0 (Ireg_data0_d20_d0 ), .Idata0_d20_d1 (Ireg_data0_d20_d1 ), .Idata0_d21_d0 (Ireg_data0_d21_d0 ), .Idata0_d21_d1 (Ireg_data0_d21_d1 ), .Idata0_d22_d0 (Ireg_dat
tmpl_0_0dataflow__neuro_0_0fifo_329_73_4 Ififo_reg2mrg  (.Iin_d_d0_d0 (Iregister_out_d_d0_d0 ), .Iin_d_d0_d1 (Iregister_out_d_d0_d1 ), .Iin_d_d1_d0 (Iregister_out_d_d1_d0 ), .Iin_d_d1_d1 (Iregister_out_d_d1_d1 ), .Iin_d_d2_d0 (Iregister_out_d_d2_d0 ), .Iin_d_d2_d1 (Iregister_out_d_d2_d1 ), .Iin_d_d3_d0 (Iregister_out_d_d3_d0 ), .Iin_d_d3_d1 (Iregister_out_d_d3_d1 ), .Iin_d_d4_d0 (Iregister_out_d_d4_d0 ), .Iin_d_d4_d1 (Iregister_out_d_d4_d1 ), .Iin_d_d5_d0 (Iregister_out_d_d5_d0 ), .Iin_d_d5_d1 (Iregister_out_d_d5_d1 ), .Iin_d_d6_d0 (Iregister_out_d_d6_d0 ), .Iin_d_d6_d1 (Iregister_out_d_d6_d1 ), .Iin_d_d7_d0 (Iregister_out_d_d7_d0 ), .Iin_d_d7_d1 (Iregister_out_d_d7_d1 ), .Iin_d_d8_d0 (Iregister_out_d_d8_d0 ), .Iin_d_d8_d1 (Iregister_out_d_d8_d1 ), .Iin_d_d9_d0 (Iregister_out_d_d9_d0 ), .Iin_d_d9_d1 (Iregister_out_d_d9_d1 ), .Iin_d_d10_d0 (Iregister_out_d_d10_d0 ), .Iin_d_d10_d1 (Iregister_out_d_d10_d1 ), .Iin_d_d11_d0 (Iregister_out_d_d11_d0 ), .Iin_d_d11_d1 (Iregister_out_d_d11_d1 ), .Iin_d_d12_d0 (Iregister_out_d_d12_d0 ), .Iin_d_d12_d1 (Iregister_out_d_d12_d1 ), .Iin_d_d13_d0 (Iregister_out_d_d13_d0 ), .Iin_d_d13_d1 (Iregister_out_d_d13_d1 ), .Iin_d_d14_d0 (Iregister_out_d_d14_d0 ), .Iin_d_d14_d1 (Iregister_out_d_d14_d1 ), .Iin_d_d15_d0 (Iregister_out_d_d15_d0 ), .Iin_d_d15_d1 (Iregister_out_d_d15_d1 ), .Iin_d_d16_d0 (Iregister_out_d_d16_d0 ), .Iin_d_d16_d1 (Iregister_out_d_d16_d1 ), .Iin_d_d17_d0 (Iregister_out_d_d17_d0 ), .Iin_d_d17_d1 (Iregister_out_d_d17_d1 ), .Iin_d_d18_d0 (Iregister_out_d_d18_d0 ), .Iin_d_d18_d1 (Iregister_out_d_d18_d1 ), .Iin_d_d19_d0 (Iregister_out_d_d19_d0 ), .Iin_d_d19_d1 (Iregister_out_d_d19_d1 ), .Iin_d_d20_d0 (Iregister_out_d_d20_d0 ), .Iin_d_d20_d1 (Iregister_out_d_d20_d1 ), .Iin_d_d21_d0 (Iregister_out_d_d21_d0 ), .Iin_d_d21_d1 (Iregister_out_d_d21_d1 ), .Iin_d_d22_d0 (Iregister_out_d_d22_d0 ), .Iin_d_d22_d1 (Iregister_out_d_d22_d1 ), .Iin_d_d23_d0 (Iregister_out_d_d23_d0 ), .Iin_d_d23_d1 (Iregister_out_d_d23_d1 ), .Iin_d_d24_d0 (Iregister_out_d_d24_d0 ), .Iin_d_d24_d1 (Iregister_out_d_d24_d1 ), .Iin_d_d25_d0 (Iregister_out_d_d25_d0 ), .Iin_d_d25_d1 (Iregister_out_d_d25_d1 ), .Iin_d_d26_d0 (Iregister_out_d_d26_d0 ), .Iin_d_d26_d1 (Iregister_out_d_d26_d1 ), .Iin_d_d27_d0 (Iregister_out_d_d27_d0 ), .Iin_d_d27_d1 (Iregister_out_d_d27_d1 ), .Iin_d_d28_d0 (Iregister_out_d_d28_d0 ), .Iin_d_d28_d1 (Iregister_out_d_d28_d1 ), .Iin_a (Iregister_out_a ), .Iin_v (Iregister_out_v ), .Iout_d_d0_d0 (Iappend_reg_in_d_d0_d0 ), .Iout_d_d0_d1 (Iappend_reg_in_d_d0_d1 ), .Iout_d_d1_d0 (Iappend_reg_in_d_d1_d0 ), .Iout_d_d1_d1 (Iappend_reg_in_d_d1_d1 ), .Iout_d_d2_d0 (Iappend_reg_in_d_d2_d0 ), .Iout_d_d2_d1 (Iappend_reg_in_d_d2_d1 ), .Iout_d_d3_d0 (Iappend_reg_in_d_d3_d0 ), .Iout_d_d3_d1 (Iappend_reg_in_d_d3_d1 ), .Iout_d_d4_d0 (Iappend_reg_in_d_d4_d0 ), .Iout_d_d4_d1 (Iappend_reg_in_d_d4_d1 ), .Iout_d_d5_d0 (Iappend_reg_in_d_d5_d0 ), .Iout_d_d5_d1 (Iappend_reg_in_d_d5_d1 ), .Iout_d_d6_d0 (Iappend_reg_in_d_d6_d0 ), .Iout_d_d6_d1 (Iappend_reg_in_d_d6_d1 ), .Iout_d_d7_d0 (Iappend_reg_in_d_d7_d0 ), .Iout_d_d7_d1 (Iappend_reg_in_d_d7_d1 ), .Iout_d_d8_d0 (Iappend_reg_in_d_d8_d0 ), .Iout_d_d8_d1 (Iappend_reg_in_d_d8_d1 ), .Iout_d_d9_d0 (Iappend_reg_in_d_d9_d0 ), .Iout_d_d9_d1 (Iappend_reg_in_d_d9_d1 ), .Iout_d_d10_d0 (Iappend_reg_in_d_d10_d0 ), .Iout_d_d10_d1 (Iappend_reg_in_d_d10_d1 ), .Iout_d_d11_d0 (Iappend_reg_in_d_d11_d0 ), .Iout_d_d11_d1 (Iappend_reg_in_d_d11_d1 ), .Iout_d_d12_d0 (Iappend_reg_in_d_d12_d0 ), .Iout_d_d12_d1 (Iappend_reg_in_d_d12_d1 ), .Iout_d_d13_d0 (Iappend_reg_in_d_d13_d0 ), .Iout_d_d13_d1 (Iappend_reg_in_d_d13_d1 ), .Iout_d_d14_d0 (Iappend_reg_in_d_d14_d0 ), .Iout_d_d14_d1 (Iappend_reg_in_d_d14_d1 ), .Iout_d_d15_d0 (Iappend_reg_in_d_d15_d0 ), .Iout_d_d15_d1 (Iappend_reg_in_d_d15_d1 ), .Iout_d_d16_d0 (Iappend_reg_in_d_d16_d0 ), .Iout_d_d16_d1 (Iappend_reg_in_d_d16_d1 ), .Iout_d_d17_d0 (Iappend_reg_in_d_d17_d0 ), .Iout_d_d17_d1 (Iappend_reg_in_d_d17_d1 ), .Iout_d_d18_d0 (Iappend_reg_in_d_d18_d0 ), .Iout_d_d18_d1 (Iappend_reg_in_d_d18_d1 ), .Iout_d_d19_d0 (Iappend_reg_in_d_d19_d0 ), .Iout_d_d
AND2_X1 Isyn_flags_dev_safety0  (.y(Isb_syn_EFO_in0 ), .a(Ireg_data4_d0_d1 ), .b(Ireg_data0_d5_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Isyn_flags_dev_safety1  (.y(Isb_syn_EFO_in1 ), .a(Ireg_data4_d1_d1 ), .b(Ireg_data0_d5_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Isyn_flags_dev_safety2  (.y(Isb_syn_EFO_in2 ), .a(Ireg_data4_d2_d1 ), .b(Ireg_data0_d5_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Isb_DEV_DEBUG  (.in(Ireg_data0_d5_d1 ), .Iout0 (DEV_DEBUG), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0fifo_331_73_4 Ififo_in  (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_d_d7_d0 (Iin_d_d7_d0 ), .Iin_d_d7_d1 (Iin_d_d7_d1 ), .Iin_d_d8_d0 (Iin_d_d8_d0 ), .Iin_d_d8_d1 (Iin_d_d8_d1 ), .Iin_d_d9_d0 (Iin_d_d9_d0 ), .Iin_d_d9_d1 (Iin_d_d9_d1 ), .Iin_d_d10_d0 (Iin_d_d10_d0 ), .Iin_d_d10_d1 (Iin_d_d10_d1 ), .Iin_d_d11_d0 (Iin_d_d11_d0 ), .Iin_d_d11_d1 (Iin_d_d11_d1 ), .Iin_d_d12_d0 (Iin_d_d12_d0 ), .Iin_d_d12_d1 (Iin_d_d12_d1 ), .Iin_d_d13_d0 (Iin_d_d13_d0 ), .Iin_d_d13_d1 (Iin_d_d13_d1 ), .Iin_d_d14_d0 (Iin_d_d14_d0 ), .Iin_d_d14_d1 (Iin_d_d14_d1 ), .Iin_d_d15_d0 (Iin_d_d15_d0 ), .Iin_d_d15_d1 (Iin_d_d15_d1 ), .Iin_d_d16_d0 (Iin_d_d16_d0 ), .Iin_d_d16_d1 (Iin_d_d16_d1 ), .Iin_d_d17_d0 (Iin_d_d17_d0 ), .Iin_d_d17_d1 (Iin_d_d17_d1 ), .Iin_d_d18_d0 (Iin_d_d18_d0 ), .Iin_d_d18_d1 (Iin_d_d18_d1 ), .Iin_d_d19_d0 (Iin_d_d19_d0 ), .Iin_d_d19_d1 (Iin_d_d19_d1 ), .Iin_d_d20_d0 (Iin_d_d20_d0 ), .Iin_d_d20_d1 (Iin_d_d20_d1 ), .Iin_d_d21_d0 (Iin_d_d21_d0 ), .Iin_d_d21_d1 (Iin_d_d21_d1 ), .Iin_d_d22_d0 (Iin_d_d22_d0 ), .Iin_d_d22_d1 (Iin_d_d22_d1 ), .Iin_d_d23_d0 (Iin_d_d23_d0 ), .Iin_d_d23_d1 (Iin_d_d23_d1 ), .Iin_d_d24_d0 (Iin_d_d24_d0 ), .Iin_d_d24_d1 (Iin_d_d24_d1 ), .Iin_d_d25_d0 (Iin_d_d25_d0 ), .Iin_d_d25_d1 (Iin_d_d25_d1 ), .Iin_d_d26_d0 (Iin_d_d26_d0 ), .Iin_d_d26_d1 (Iin_d_d26_d1 ), .Iin_d_d27_d0 (Iin_d_d27_d0 ), .Iin_d_d27_d1 (Iin_d_d27_d1 ), .Iin_d_d28_d0 (Iin_d_d28_d0 ), .Iin_d_d28_d1 (Iin_d_d28_d1 ), .Iin_d_d29_d0 (Iin_d_d29_d0 ), .Iin_d_d29_d1 (Iin_d_d29_d1 ), .Iin_d_d30_d0 (Iin_d_d30_d0 ), .Iin_d_d30_d1 (Iin_d_d30_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (I_demux_in_d_d0_d0 ), .Iout_d_d0_d1 (I_demux_in_d_d0_d1 ), .Iout_d_d1_d0 (I_demux_in_d_d1_d0 ), .Iout_d_d1_d1 (I_demux_in_d_d1_d1 ), .Iout_d_d2_d0 (I_demux_in_d_d2_d0 ), .Iout_d_d2_d1 (I_demux_in_d_d2_d1 ), .Iout_d_d3_d0 (I_demux_in_d_d3_d0 ), .Iout_d_d3_d1 (I_demux_in_d_d3_d1 ), .Iout_d_d4_d0 (I_demux_in_d_d4_d0 ), .Iout_d_d4_d1 (I_demux_in_d_d4_d1 ), .Iout_d_d5_d0 (I_demux_in_d_d5_d0 ), .Iout_d_d5_d1 (I_demux_in_d_d5_d1 ), .Iout_d_d6_d0 (I_demux_in_d_d6_d0 ), .Iout_d_d6_d1 (I_demux_in_d_d6_d1 ), .Iout_d_d7_d0 (I_demux_in_d_d7_d0 ), .Iout_d_d7_d1 (I_demux_in_d_d7_d1 ), .Iout_d_d8_d0 (I_demux_in_d_d8_d0 ), .Iout_d_d8_d1 (I_demux_in_d_d8_d1 ), .Iout_d_d9_d0 (I_demux_in_d_d9_d0 ), .Iout_d_d9_d1 (I_demux_in_d_d9_d1 ), .Iout_d_d10_d0 (I_demux_in_d_d10_d0 ), .Iout_d_d10_d1 (I_demux_in_d_d10_d1 ), .Iout_d_d11_d0 (I_demux_in_d_d11_d0 ), .Iout_d_d11_d1 (I_demux_in_d_d11_d1 ), .Iout_d_d12_d0 (I_demux_in_d_d12_d0 ), .Iout_d_d12_d1 (I_demux_in_d_d12_d1 ), .Iout_d_d13_d0 (I_demux_in_d_d13_d0 ), .Iout_d_d13_d1 (I_demux_in_d_d13_d1 ), .Iout_d_d14_d0 (I_demux_in_d_d14_d0 ), .Iout_d_d14_d1 (I_demux_in_d_d14_d1 ), .Iout_d_d15_d0 (I_demux_in_d_d15_d0 ), .Iout_d_d15_d1 (I_demux_in_d_d15_d1 ), .Iout_d_d16_d0 (I_demux_in_d_d16_d0 ), .Iout_d_d16_d1 (I_demux_in_d_d16_d1 ), .Iout_d_d17_d0 (I_demux_in_d_d17_d0 ), .Iout_d_d17_d1 (I_demux_in_d_d17_d1 ), .Iout_d_d18_d0 (I_demux_in_d_d18_d0 ), .Iout_d_d18_d1 (I_demux_in_d_d18_d1 ), .Iout_d_d19_d0 (I_demux_in_d_d19_d0 ), .Iout_d_d19_d1 (I_demux_in_d_d19_d1 ), .Iout_d_d20_d0 (I_demux_in_d_d20_d0 ), .Iout_d_d20_d1 (I_demux_in_d_d20_d1 ), .Iout_d_d21_d0 (I_demux_in_d_d21_d0 ), .Iout_d_d21_d1 (I_demux_in_d_d21_d1 ), .Iout_d_d22_d0 (I_demux_in_d_d22_d0 ), .Iout_d_d22_d1 (I_demux_in_d_d22_d1 ), .Iout_d_d23_d0 (I_demux_in_d_d23_d0 ), .Iout_d_d23_d1 (I_demux_in_d_d23_d1 ), .Iout_d_d24_d0 (I_demux_in_d_d24_d0 ), .Iout_d_d24_d1 (I_demux_in_d_d24_d1 ), .Iout_d_d25_d0 (I_demux_in_d_d25_d0 ), .Iout_d_d25_d1 (I_demux_in_d_d25_d1 ), .Iout_d_d26_d0 (I_demux_in_d_d26_d0 ), .Iout_d_d26_d1 (I_demux_in_d_d26_d1 ), .Iout_d_d27_d0 (I_demux_in_d_d27_d0 ), .Iout_d_d27_d1 (I_demu
tmpl_0_0dataflow__neuro_0_0fifo_330_73_4 Ififo_dmx2reg  (.Iin_d_d0_d0 (I_demux_out2_d_d0_d0 ), .Iin_d_d0_d1 (I_demux_out2_d_d0_d1 ), .Iin_d_d1_d0 (I_demux_out2_d_d1_d0 ), .Iin_d_d1_d1 (I_demux_out2_d_d1_d1 ), .Iin_d_d2_d0 (I_demux_out2_d_d2_d0 ), .Iin_d_d2_d1 (I_demux_out2_d_d2_d1 ), .Iin_d_d3_d0 (I_demux_out2_d_d3_d0 ), .Iin_d_d3_d1 (I_demux_out2_d_d3_d1 ), .Iin_d_d4_d0 (I_demux_out2_d_d4_d0 ), .Iin_d_d4_d1 (I_demux_out2_d_d4_d1 ), .Iin_d_d5_d0 (I_demux_out2_d_d5_d0 ), .Iin_d_d5_d1 (I_demux_out2_d_d5_d1 ), .Iin_d_d6_d0 (I_demux_out2_d_d6_d0 ), .Iin_d_d6_d1 (I_demux_out2_d_d6_d1 ), .Iin_d_d7_d0 (I_demux_out2_d_d7_d0 ), .Iin_d_d7_d1 (I_demux_out2_d_d7_d1 ), .Iin_d_d8_d0 (I_demux_out2_d_d8_d0 ), .Iin_d_d8_d1 (I_demux_out2_d_d8_d1 ), .Iin_d_d9_d0 (I_demux_out2_d_d9_d0 ), .Iin_d_d9_d1 (I_demux_out2_d_d9_d1 ), .Iin_d_d10_d0 (I_demux_out2_d_d10_d0 ), .Iin_d_d10_d1 (I_demux_out2_d_d10_d1 ), .Iin_d_d11_d0 (I_demux_out2_d_d11_d0 ), .Iin_d_d11_d1 (I_demux_out2_d_d11_d1 ), .Iin_d_d12_d0 (I_demux_out2_d_d12_d0 ), .Iin_d_d12_d1 (I_demux_out2_d_d12_d1 ), .Iin_d_d13_d0 (I_demux_out2_d_d13_d0 ), .Iin_d_d13_d1 (I_demux_out2_d_d13_d1 ), .Iin_d_d14_d0 (I_demux_out2_d_d14_d0 ), .Iin_d_d14_d1 (I_demux_out2_d_d14_d1 ), .Iin_d_d15_d0 (I_demux_out2_d_d15_d0 ), .Iin_d_d15_d1 (I_demux_out2_d_d15_d1 ), .Iin_d_d16_d0 (I_demux_out2_d_d16_d0 ), .Iin_d_d16_d1 (I_demux_out2_d_d16_d1 ), .Iin_d_d17_d0 (I_demux_out2_d_d17_d0 ), .Iin_d_d17_d1 (I_demux_out2_d_d17_d1 ), .Iin_d_d18_d0 (I_demux_out2_d_d18_d0 ), .Iin_d_d18_d1 (I_demux_out2_d_d18_d1 ), .Iin_d_d19_d0 (I_demux_out2_d_d19_d0 ), .Iin_d_d19_d1 (I_demux_out2_d_d19_d1 ), .Iin_d_d20_d0 (I_demux_out2_d_d20_d0 ), .Iin_d_d20_d1 (I_demux_out2_d_d20_d1 ), .Iin_d_d21_d0 (I_demux_out2_d_d21_d0 ), .Iin_d_d21_d1 (I_demux_out2_d_d21_d1 ), .Iin_d_d22_d0 (I_demux_out2_d_d22_d0 ), .Iin_d_d22_d1 (I_demux_out2_d_d22_d1 ), .Iin_d_d23_d0 (I_demux_out2_d_d23_d0 ), .Iin_d_d23_d1 (I_demux_out2_d_d23_d1 ), .Iin_d_d24_d0 (I_demux_out2_d_d24_d0 ), .Iin_d_d24_d1 (I_demux_out2_d_d24_d1 ), .Iin_d_d25_d0 (I_demux_out2_d_d25_d0 ), .Iin_d_d25_d1 (I_demux_out2_d_d25_d1 ), .Iin_d_d26_d0 (I_demux_out2_d_d26_d0 ), .Iin_d_d26_d1 (I_demux_out2_d_d26_d1 ), .Iin_d_d27_d0 (I_demux_out2_d_d27_d0 ), .Iin_d_d27_d1 (I_demux_out2_d_d27_d1 ), .Iin_d_d28_d0 (I_demux_out2_d_d28_d0 ), .Iin_d_d28_d1 (I_demux_out2_d_d28_d1 ), .Iin_d_d29_d0 (I_demux_out2_d_d29_d0 ), .Iin_d_d29_d1 (I_demux_out2_d_d29_d1 ), .Iin_a (I_demux_out2_a ), .Iin_v (I_demux_out2_v ), .Iout_d_d0_d0 (Iregister_in_d_d0_d0 ), .Iout_d_d0_d1 (Iregister_in_d_d0_d1 ), .Iout_d_d1_d0 (Iregister_in_d_d1_d0 ), .Iout_d_d1_d1 (Iregister_in_d_d1_d1 ), .Iout_d_d2_d0 (Iregister_in_d_d2_d0 ), .Iout_d_d2_d1 (Iregister_in_d_d2_d1 ), .Iout_d_d3_d0 (Iregister_in_d_d3_d0 ), .Iout_d_d3_d1 (Iregister_in_d_d3_d1 ), .Iout_d_d4_d0 (Iregister_in_d_d4_d0 ), .Iout_d_d4_d1 (Iregister_in_d_d4_d1 ), .Iout_d_d5_d0 (Iregister_in_d_d5_d0 ), .Iout_d_d5_d1 (Iregister_in_d_d5_d1 ), .Iout_d_d6_d0 (Iregister_in_d_d6_d0 ), .Iout_d_d6_d1 (Iregister_in_d_d6_d1 ), .Iout_d_d7_d0 (Iregister_in_d_d7_d0 ), .Iout_d_d7_d1 (Iregister_in_d_d7_d1 ), .Iout_d_d8_d0 (Iregister_in_d_d8_d0 ), .Iout_d_d8_d1 (Iregister_in_d_d8_d1 ), .Iout_d_d9_d0 (Iregister_in_d_d9_d0 ), .Iout_d_d9_d1 (Iregister_in_d_d9_d1 ), .Iout_d_d10_d0 (Iregister_in_d_d10_d0 ), .Iout_d_d10_d1 (Iregister_in_d_d10_d1 ), .Iout_d_d11_d0 (Iregister_in_d_d11_d0 ), .Iout_d_d11_d1 (Iregister_in_d_d11_d1 ), .Iout_d_d12_d0 (Iregister_in_d_d12_d0 ), .Iout_d_d12_d1 (Iregister_in_d_d12_d1 ), .Iout_d_d13_d0 (Iregister_in_d_d13_d0 ), .Iout_d_d13_d1 (Iregister_in_d_d13_d1 ), .Iout_d_d14_d0 (Iregister_in_d_d14_d0 ), .Iout_d_d14_d1 (Iregister_in_d_d14_d1 ), .Iout_d_d15_d0 (Iregister_in_d_d15_d0 ), .Iout_d_d15_d1 (Iregister_in_d_d15_d1 ), .Iout_d_d16_d0 (Iregister_in_d_d16_d0 ), .Iout_d_d16_d1 (Iregister_in_d_d16_d1 ), .Iout_d_d17_d0 (Iregister_in_d_d17_d0 ), .Iout_d_d17_d1 (Iregister_in_d_d17_d1 ), .Iout_d_d18_d0 (Iregister_in_d_d18_d0 ), .Iout_d_d18_d1 (Iregister_in_d_d18_d1 ), .Iout_d_d19_d0 (Iregister_in_d_d19_d0 ), .Iout_d_d19_d1 (Iregister_in_d_d19_d1 ), .Iout_d_d20_d0 (Iregister_
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_syn_hs  (.in(_reset_BX), .Iout0 (Ireset_syn_hs_BO0 ), .vdd(vdd), .vss(vss));
BUF_X12 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf0  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI0 ), .en(Inrn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf1  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI1 ), .en(Inrn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf2  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI2 ), .en(Inrn_mon_x0 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf3  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI3 ), .en(Inrn_mon_x2 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf4  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI4 ), .en(Inrn_mon_x2 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf5  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI5 ), .en(Inrn_mon_x2 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf6  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI6 ), .en(Inrn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf7  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI7 ), .en(Inrn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf8  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI8 ), .en(Inrn_mon_x4 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf9  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI9 ), .en(Inrn_mon_x6 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf10  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI10 ), .en(Inrn_mon_x6 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf11  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI11 ), .en(Inrn_mon_x6 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf12  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI12 ), .en(Inrn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf13  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI13 ), .en(Inrn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf14  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI14 ), .en(Inrn_mon_x8 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf15  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI15 ), .en(Inrn_mon_x10 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf16  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI16 ), .en(Inrn_mon_x10 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf17  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI17 ), .en(Inrn_mon_x10 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf18  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI18 ), .en(Inrn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf19  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI19 ), .en(Inrn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf20  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI20 ), .en(Inrn_mon_x12 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf21  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI21 ), .en(Inrn_mon_x14 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf22  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI22 ), .en(Inrn_mon_x14 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf23  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI23 ), .en(Inrn_mon_x14 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf24  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI24 ), .en(Inrn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf25  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI25 ), .en(Inrn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf26  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI26 ), .en(Inrn_mon_x16 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf27  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI27 ), .en(Inrn_mon_x18 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf28  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI28 ), .en(Inrn_mon_x18 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf29  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI29 ), .en(Inrn_mon_x18 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf30  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI30 ), .en(Inrn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf31  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI31 ), .en(Inrn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf32  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI32 ), .en(Inrn_mon_x20 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf33  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI33 ), .en(Inrn_mon_x22 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf34  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI34 ), .en(Inrn_mon_x22 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf35  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI35 ), .en(Inrn_mon_x22 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf36  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI36 ), .en(Inrn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf37  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI37 ), .en(Inrn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf38  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI38 ), .en(Inrn_mon_x24 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf39  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI39 ), .en(Inrn_mon_x26 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf40  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI40 ), .en(Inrn_mon_x26 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf41  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI41 ), .en(Inrn_mon_x26 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf42  (.y(Inrn_AMZO_keeps0_y ), .a(Inrn_mon_AMZI42 ), .en(Inrn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf43  (.y(Inrn_AMZO_keeps1_y ), .a(Inrn_mon_AMZI43 ), .en(Inrn_mon_x28 ), .vdd(vdd), .vss(vss));
TBUF_X4 Inrn_x_AMZI_tbuf44  (.y(Inrn_AMZO_keeps2_y ), .a(Inrn_mon_AMZI44 ), .en(Inrn_mon_x28 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_35_731_4 Isb_syn_EFO  (.Iin0 (Isb_syn_EFO_in0 ), .Iin1 (Isb_syn_EFO_in1 ), .Iin2 (Isb_syn_EFO_in2 ), .Iin3 (Ireg_data4_d3_d1 ), .Iin4 (Ireg_data4_d4_d1 ), .Iout0 (Isyn_flags_EFO0 ), .Iout1 (Isyn_flags_EFO1 ), .Iout2 (Isyn_flags_EFO2 ), .Iout3 (Isyn_flags_EFO3 ), .Iout4 (Isyn_flags_EFO4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_39_7348_4 Isyn_mon_dec_y  (.Iin_d0_d0 (Ireg_data3_d6_d0 ), .Iin_d0_d1 (Ireg_data3_d6_d1 ), .Iin_d1_d0 (Ireg_data3_d7_d0 ), .Iin_d1_d1 (Ireg_data3_d7_d1 ), .Iin_d2_d0 (Ireg_data3_d8_d0 ), .Iin_d2_d1 (Ireg_data3_d8_d1 ), .Iin_d3_d0 (Ireg_data3_d9_d0 ), .Iin_d3_d1 (Ireg_data3_d9_d1 ), .Iin_d4_d0 (Ireg_data3_d10_d0 ), .Iin_d4_d1 (Ireg_data3_d10_d1 ), .Iin_d5_d0 (Ireg_data3_d11_d0 ), .Iin_d5_d1 (Ireg_data3_d11_d1 ), .Iin_d6_d0 (Ireg_data3_d12_d0 ), .Iin_d6_d1 (Ireg_data3_d12_d1 ), .Iin_d7_d0 (Ireg_data3_d13_d0 ), .Iin_d7_d1 (Ireg_data3_d13_d1 ), .Iin_d8_d0 (Ireg_data3_d14_d0 ), .Iin_d8_d1 (Ireg_data3_d14_d1 ), .en(Ireg_data1_d1_d1 ), .Iout0 (Isyn_mon_dec_y_out0 ), .Iout1 (Isyn_mon_dec_y_out1 ), .Iout2 (Isyn_mon_dec_y_out2 ), .Iout3 (Isyn_mon_dec_y_out3 ), .Iout4 (Isyn_mon_dec_y_out4 ), .Iout5 (Isyn_mon_dec_y_out5 ), .Iout6 (Isyn_mon_dec_y_out6 ), .Iout7 (Isyn_mon_dec_y_out7 ), .Iout8 (Isyn_mon_dec_y_out8 ), .Iout9 (Isyn_mon_dec_y_out9 ), .Iout10 (Isyn_mon_dec_y_out10 ), .Iout11 (Isyn_mon_dec_y_out11 ), .Iout12 (Isyn_mon_dec_y_out12 ), .Iout13 (Isyn_mon_dec_y_out13 ), .Iout14 (Isyn_mon_dec_y_out14 ), .Iout15 (Isyn_mon_dec_y_out15 ), .Iout16 (Isyn_mon_dec_y_out16 ), .Iout17 (Isyn_mon_dec_y_out17 ), .Iout18 (Isyn_mon_dec_y_out18 ), .Iout19 (Isyn_mon_dec_y_out19 ), .Iout20 (Isyn_mon_dec_y_out20 ), .Iout21 (Isyn_mon_dec_y_out21 ), .Iout22 (Isyn_mon_dec_y_out22 ), .Iout23 (Isyn_mon_dec_y_out23 ), .Iout24 (Isyn_mon_dec_y_out24 ), .Iout25 (Isyn_mon_dec_y_out25 ), .Iout26 (Isyn_mon_dec_y_out26 ), .Iout27 (Isyn_mon_dec_y_out27 ), .Iout28 (Isyn_mon_dec_y_out28 ), .Iout29 (Isyn_mon_dec_y_out29 ), .Iout30 (Isyn_mon_dec_y_out30 ), .Iout31 (Isyn_mon_dec_y_out31 ), .Iout32 (Isyn_mon_dec_y_out32 ), .Iout33 (Isyn_mon_dec_y_out33 ), .Iout34 (Isyn_mon_dec_y_out34 ), .Iout35 (Isyn_mon_dec_y_out35 ), .Iout36 (Isyn_mon_dec_y_out36 ), .Iout37 (Isyn_mon_dec_y_out37 ), .Iout38 (Isyn_mon_dec_y_out38 ), .Iout39 (Isyn_mon_dec_y_out39 ), .Iout40 (Isyn_mon_dec_y_out40 ), .Iout41 (Isyn_mon_dec_y_out41 ), .Iout42 (Isyn_mon_dec_y_out42 ), .Iout43 (Isyn_mon_dec_y_out43 ), .Iout44 (Isyn_mon_dec_y_out44 ), .Iout45 (Isyn_mon_dec_y_out45 ), .Iout46 (Isyn_mon_dec_y_out46 ), .Iout47 (Isyn_mon_dec_y_out47 ), .Iout48 (Isyn_mon_dec_y_out48 ), .Iout49 (Isyn_mon_dec_y_out49 ), .Iout50 (Isyn_mon_dec_y_out50 ), .Iout51 (Isyn_mon_dec_y_out51 ), .Iout52 (Isyn_mon_dec_y_out52 ), .Iout53 (Isyn_mon_dec_y_out53 ), .Iout54 (Isyn_mon_dec_y_out54 ), .Iout55 (Isyn_mon_dec_y_out55 ), .Iout56 (Isyn_mon_dec_y_out56 ), .Iout57 (Isyn_mon_dec_y_out57 ), .Iout58 (Isyn_mon_dec_y_out58 ), .Iout59 (Isyn_mon_dec_y_out59 ), .Iout60 (Isyn_mon_dec_y_out60 ), .Iout61 (Isyn_mon_dec_y_out61 ), .Iout62 (Isyn_mon_dec_y_out62 ), .Iout63 (Isyn_mon_dec_y_out63 ), .Iout64 (Isyn_mon_dec_y_out64 ), .Iout65 (Isyn_mon_dec_y_out65 ), .Iout66 (Isyn_mon_dec_y_out66 ), .Iout67 (Isyn_mon_dec_y_out67 ), .Iout68 (Isyn_mon_dec_y_out68 ), .Iout69 (Isyn_mon_dec_y_out69 ), .Iout70 (Isyn_mon_dec_y_out70 ), .Iout71 (Isyn_mon_dec_y_out71 ), .Iout72 (Isyn_mon_dec_y_out72 ), .Iout73 (Isyn_mon_dec_y_out73 ), .Iout74 (Isyn_mon_dec_y_out74 ), .Iout75 (Isyn_mon_dec_y_out75 ), .Iout76 (Isyn_mon_dec_y_out76 ), .Iout77 (Isyn_mon_dec_y_out77 ), .Iout78 (Isyn_mon_dec_y_out78 ), .Iout79 (Isyn_mon_dec_y_out79 ), .Iout80 (Isyn_mon_dec_y_out80 ), .Iout81 (Isyn_mon_dec_y_out81 ), .Iout82 (Isyn_mon_dec_y_out82 ), .Iout83 (Isyn_mon_dec_y_out83 ), .Iout84 (Isyn_mon_dec_y_out84 ), .Iout85 (Isyn_mon_dec_y_out85 ), .Iout86 (Isyn_mon_dec_y_out86 ), .Iout87 (Isyn_mon_dec_y_out87 ), .Iout88 (Isyn_mon_dec_y_out88 ), .Iout89 (Isyn_mon_dec_y_out89 ), .Iout90 (Isyn_mon_dec_y_out90 ), .Iout91 (Isyn_mon_dec_y_out91 ), .Iout92 (Isyn_mon_dec_y_out92 ), .Iout93 (Isyn_mon_dec_y_out93 ), .Iout94 (Isyn_mon_dec_y_out94 ), .Iout95 (Isyn_mon_dec_y_out95 ), .Iout96 (Isyn_mon_dec_y_out96 ), .Iout97 (Isyn_mon_dec_y_out97 ), .Iout98 (Isyn_mon_dec_y_out98 ), .Iout99 (Isyn_mon_dec_y_out99 ), .Iout100 (Isyn_mon_dec_y_out100 ), .Iout101 (Isyn_mon_dec_y_out101 ), .Iout102 (Isyn_mon_dec_y_out102 ), .Iout103 (Isyn_mon_dec_y
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4 Inrn_mon_dec_x  (.Iin_d0_d0 (Ireg_data2_d0_d0 ), .Iin_d0_d1 (Ireg_data2_d0_d1 ), .Iin_d1_d0 (Ireg_data2_d1_d0 ), .Iin_d1_d1 (Ireg_data2_d1_d1 ), .Iin_d2_d0 (Ireg_data2_d2_d0 ), .Iin_d2_d1 (Ireg_data2_d2_d1 ), .Iin_d3_d0 (Ireg_data2_d3_d0 ), .Iin_d3_d1 (Ireg_data2_d3_d1 ), .Iin_d4_d0 (Ireg_data2_d4_d0 ), .Iin_d4_d1 (Ireg_data2_d4_d1 ), .en(Ireg_data1_d0_d1 ), .Iout0 (Inrn_mon_dec_x_out0 ), .Iout1 (Inrn_mon_dec_x_out1 ), .Iout2 (Inrn_mon_dec_x_out2 ), .Iout3 (Inrn_mon_dec_x_out3 ), .Iout4 (Inrn_mon_dec_x_out4 ), .Iout5 (Inrn_mon_dec_x_out5 ), .Iout6 (Inrn_mon_dec_x_out6 ), .Iout7 (Inrn_mon_dec_x_out7 ), .Iout8 (Inrn_mon_dec_x_out8 ), .Iout9 (Inrn_mon_dec_x_out9 ), .Iout10 (Inrn_mon_dec_x_out10 ), .Iout11 (Inrn_mon_dec_x_out11 ), .Iout12 (Inrn_mon_dec_x_out12 ), .Iout13 (Inrn_mon_dec_x_out13 ), .Iout14 (Inrn_mon_dec_x_out14 ), .Iout15 (Inrn_mon_dec_x_out15 ), .Iout16 (Inrn_mon_dec_x_out16 ), .Iout17 (Inrn_mon_dec_x_out17 ), .Iout18 (Inrn_mon_dec_x_out18 ), .Iout19 (Inrn_mon_dec_x_out19 ), .Iout20 (Inrn_mon_dec_x_out20 ), .Iout21 (Inrn_mon_dec_x_out21 ), .Iout22 (Inrn_mon_dec_x_out22 ), .Iout23 (Inrn_mon_dec_x_out23 ), .Iout24 (Inrn_mon_dec_x_out24 ), .Iout25 (Inrn_mon_dec_x_out25 ), .Iout26 (Inrn_mon_dec_x_out26 ), .Iout27 (Inrn_mon_dec_x_out27 ), .Iout28 (Inrn_mon_dec_x_out28 ), .Iout29 (Inrn_mon_dec_x_out29 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4 Iencoder  (.Iinx0_d_d0 (Ienc_inx0_d_d0 ), .Iinx0_a (Ienc_inx0_a ), .Iinx1_d_d0 (Ienc_inx1_d_d0 ), .Iinx1_a (Ienc_inx1_a ), .Iinx2_d_d0 (Ienc_inx2_d_d0 ), .Iinx2_a (Ienc_inx2_a ), .Iinx3_d_d0 (Ienc_inx3_d_d0 ), .Iinx3_a (Ienc_inx3_a ), .Iinx4_d_d0 (Ienc_inx4_d_d0 ), .Iinx4_a (Ienc_inx4_a ), .Iinx5_d_d0 (Ienc_inx5_d_d0 ), .Iinx5_a (Ienc_inx5_a ), .Iinx6_d_d0 (Ienc_inx6_d_d0 ), .Iinx6_a (Ienc_inx6_a ), .Iinx7_d_d0 (Ienc_inx7_d_d0 ), .Iinx7_a (Ienc_inx7_a ), .Iinx8_d_d0 (Ienc_inx8_d_d0 ), .Iinx8_a (Ienc_inx8_a ), .Iinx9_d_d0 (Ienc_inx9_d_d0 ), .Iinx9_a (Ienc_inx9_a ), .Iinx10_d_d0 (Ienc_inx10_d_d0 ), .Iinx10_a (Ienc_inx10_a ), .Iinx11_d_d0 (Ienc_inx11_d_d0 ), .Iinx11_a (Ienc_inx11_a ), .Iinx12_d_d0 (Ienc_inx12_d_d0 ), .Iinx12_a (Ienc_inx12_a ), .Iinx13_d_d0 (Ienc_inx13_d_d0 ), .Iinx13_a (Ienc_inx13_a ), .Iinx14_d_d0 (Ienc_inx14_d_d0 ), .Iinx14_a (Ienc_inx14_a ), .Iiny0_d_d0 (Ienc_iny0_d_d0 ), .Iiny0_a (Ienc_iny0_a ), .Iiny1_d_d0 (Ienc_iny1_d_d0 ), .Iiny1_a (Ienc_iny1_a ), .Iiny2_d_d0 (Ienc_iny2_d_d0 ), .Iiny2_a (Ienc_iny2_a ), .Iiny3_d_d0 (Ienc_iny3_d_d0 ), .Iiny3_a (Ienc_iny3_a ), .Iiny4_d_d0 (Ienc_iny4_d_d0 ), .Iiny4_a (Ienc_iny4_a ), .Iiny5_d_d0 (Ienc_iny5_d_d0 ), .Iiny5_a (Ienc_iny5_a ), .Iout_d_d0_d0 (Iencoder_out_d_d0_d0 ), .Iout_d_d0_d1 (Iencoder_out_d_d0_d1 ), .Iout_d_d1_d0 (Iencoder_out_d_d1_d0 ), .Iout_d_d1_d1 (Iencoder_out_d_d1_d1 ), .Iout_d_d2_d0 (Iencoder_out_d_d2_d0 ), .Iout_d_d2_d1 (Iencoder_out_d_d2_d1 ), .Iout_d_d3_d0 (Iencoder_out_d_d3_d0 ), .Iout_d_d3_d1 (Iencoder_out_d_d3_d1 ), .Iout_d_d4_d0 (Iencoder_out_d_d4_d0 ), .Iout_d_d4_d1 (Iencoder_out_d_d4_d1 ), .Iout_d_d5_d0 (Iencoder_out_d_d5_d0 ), .Iout_d_d5_d1 (Iencoder_out_d_d5_d1 ), .Iout_d_d6_d0 (Iencoder_out_d_d6_d0 ), .Iout_d_d6_d1 (Iencoder_out_d_d6_d1 ), .Iout_a (Iencoder_out_a ), .Iout_v (Iencoder_out_v ), .Ito_pd_x0_d_d0 (Inrn_pd_x0_d_d0 ), .Ito_pd_x0_a (Inrn_pd_x0_a ), .Ito_pd_x1_d_d0 (Inrn_pd_x1_d_d0 ), .Ito_pd_x1_a (Inrn_pd_x1_a ), .Ito_pd_x2_d_d0 (Inrn_pd_x2_d_d0 ), .Ito_pd_x2_a (Inrn_pd_x2_a ), .Ito_pd_x3_d_d0 (Inrn_pd_x3_d_d0 ), .Ito_pd_x3_a (Inrn_pd_x3_a ), .Ito_pd_x4_d_d0 (Inrn_pd_x4_d_d0 ), .Ito_pd_x4_a (Inrn_pd_x4_a ), .Ito_pd_x5_d_d0 (Inrn_pd_x5_d_d0 ), .Ito_pd_x5_a (Inrn_pd_x5_a ), .Ito_pd_x6_d_d0 (Inrn_pd_x6_d_d0 ), .Ito_pd_x6_a (Inrn_pd_x6_a ), .Ito_pd_x7_d_d0 (Inrn_pd_x7_d_d0 ), .Ito_pd_x7_a (Inrn_pd_x7_a ), .Ito_pd_x8_d_d0 (Inrn_pd_x8_d_d0 ), .Ito_pd_x8_a (Inrn_pd_x8_a ), .Ito_pd_x9_d_d0 (Inrn_pd_x9_d_d0 ), .Ito_pd_x9_a (Inrn_pd_x9_a ), .Ito_pd_x10_d_d0 (Inrn_pd_x10_d_d0 ), .Ito_pd_x10_a (Inrn_pd_x10_a ), .Ito_pd_x11_d_d0 (Inrn_pd_x11_d_d0 ), .Ito_pd_x11_a (Inrn_pd_x11_a ), .Ito_pd_x12_d_d0 (Inrn_pd_x12_d_d0 ), .Ito_pd_x12_a (Inrn_pd_x12_a ), .Ito_pd_x13_d_d0 (Inrn_pd_x13_d_d0 ), .Ito_pd_x13_a (Inrn_pd_x13_a ), .Ito_pd_x14_d_d0 (Inrn_pd_x14_d_d0 ), .Ito_pd_x14_a (Inrn_pd_x14_a ), .Ito_pd_y0_d_d0 (Inrn_pd_y0_d_d0 ), .Ito_pd_y0_a (Inrn_pd_y0_a ), .Ito_pd_y1_d_d0 (Inrn_pd_y1_d_d0 ), .Ito_pd_y1_a (Inrn_pd_y1_a ), .Ito_pd_y2_d_d0 (Inrn_pd_y2_d_d0 ), .Ito_pd_y2_a (Inrn_pd_y2_a ), .Ito_pd_y3_d_d0 (Inrn_pd_y3_d_d0 ), .Ito_pd_y3_a (Inrn_pd_y3_a ), .Ito_pd_y4_d_d0 (Inrn_pd_y4_d_d0 ), .Ito_pd_y4_a (Inrn_pd_y4_a ), .Ito_pd_y5_d_d0 (Inrn_pd_y5_d_d0 ), .Ito_pd_y5_a (Inrn_pd_y5_a ), .Isupply_vdd (Isupply_vdd ), .Isupply_vss (Isupply_vss ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0fifo_331_73_4 Ififo_out  (.Iin_d_d0_d0 (Ififo_out_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_out_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_out_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_out_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_out_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_out_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_out_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_out_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_out_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_out_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_out_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_out_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_out_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_out_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_out_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_out_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_out_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_out_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_out_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_out_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_out_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_out_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_out_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_out_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_out_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_out_in_d_d12_d1 ), .Iin_d_d13_d0 (Ififo_out_in_d_d13_d0 ), .Iin_d_d13_d1 (Ififo_out_in_d_d13_d1 ), .Iin_d_d14_d0 (Ififo_out_in_d_d14_d0 ), .Iin_d_d14_d1 (Ififo_out_in_d_d14_d1 ), .Iin_d_d15_d0 (Ififo_out_in_d_d15_d0 ), .Iin_d_d15_d1 (Ififo_out_in_d_d15_d1 ), .Iin_d_d16_d0 (Ififo_out_in_d_d16_d0 ), .Iin_d_d16_d1 (Ififo_out_in_d_d16_d1 ), .Iin_d_d17_d0 (Ififo_out_in_d_d17_d0 ), .Iin_d_d17_d1 (Ififo_out_in_d_d17_d1 ), .Iin_d_d18_d0 (Ififo_out_in_d_d18_d0 ), .Iin_d_d18_d1 (Ififo_out_in_d_d18_d1 ), .Iin_d_d19_d0 (Ififo_out_in_d_d19_d0 ), .Iin_d_d19_d1 (Ififo_out_in_d_d19_d1 ), .Iin_d_d20_d0 (Ififo_out_in_d_d20_d0 ), .Iin_d_d20_d1 (Ififo_out_in_d_d20_d1 ), .Iin_d_d21_d0 (Ififo_out_in_d_d21_d0 ), .Iin_d_d21_d1 (Ififo_out_in_d_d21_d1 ), .Iin_d_d22_d0 (Ififo_out_in_d_d22_d0 ), .Iin_d_d22_d1 (Ififo_out_in_d_d22_d1 ), .Iin_d_d23_d0 (Ififo_out_in_d_d23_d0 ), .Iin_d_d23_d1 (Ififo_out_in_d_d23_d1 ), .Iin_d_d24_d0 (Ififo_out_in_d_d24_d0 ), .Iin_d_d24_d1 (Ififo_out_in_d_d24_d1 ), .Iin_d_d25_d0 (Ififo_out_in_d_d25_d0 ), .Iin_d_d25_d1 (Ififo_out_in_d_d25_d1 ), .Iin_d_d26_d0 (Ififo_out_in_d_d26_d0 ), .Iin_d_d26_d1 (Ififo_out_in_d_d26_d1 ), .Iin_d_d27_d0 (Ififo_out_in_d_d27_d0 ), .Iin_d_d27_d1 (Ififo_out_in_d_d27_d1 ), .Iin_d_d28_d0 (Ififo_out_in_d_d28_d0 ), .Iin_d_d28_d1 (Ififo_out_in_d_d28_d1 ), .Iin_d_d29_d0 (Ififo_out_in_d_d29_d0 ), .Iin_d_d29_d1 (Ififo_out_in_d_d29_d1 ), .Iin_d_d30_d0 (Ififo_out_in_d_d30_d0 ), .Iin_d_d30_d1 (Ififo_out_in_d_d30_d1 ), .Iin_a (Ififo_out_in_a ), .Iin_v (Ififo_out_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_d_d7_d0 (Iout_d_d7_d0 ), .Iout_d_d7_d1 (Iout_d_d7_d1 ), .Iout_d_d8_d0 (Iout_d_d8_d0 ), .Iout_d_d8_d1 (Iout_d_d8_d1 ), .Iout_d_d9_d0 (Iout_d_d9_d0 ), .Iout_d_d9_d1 (Iout_d_d9_d1 ), .Iout_d_d10_d0 (Iout_d_d10_d0 ), .Iout_d_d10_d1 (Iout_d_d10_d1 ), .Iout_d_d11_d0 (Iout_d_d11_d0 ), .Iout_d_d11_d1 (Iout_d_d11_d1 ), .Iout_d_d12_d0 (Iout_d_d12_d0 ), .Iout_d_d12_d1 (Iout_d_d12_d1 ), .Iout_d_d13_d0 (Iout_d_d13_d0 ), .Iout_d_d13_d1 (Iout_d_d13_d1 ), .Iout_d_d14_d0 (Iout_d_d14_d0 ), .Iout_d_d14_d1 (Iout_d_d14_d1 ), .Iout_d_d15_d0 (Iout_d_d15_d0 ), .Iout_d_d15_d1 (Iout_d_d15_d1 ), .Iout_d_d16_d0 (Iout_d_d16_d0 ), .Iout_d_d16_d1 (Iout_d_d16_d1 ), .Iout_d_d17_d0 (Iout_d_d17_d0 ), .Iout_d_d17_d1 (Iout_d_d17_d1 ), .Iout_d_d18_d0 (Iout_d_d18_d0 ), .Iout_d_d18_d1 (Iout_d_d18_d1 ), .Iout_d_d19_d0 (Iout_d_d19_d0 ), .Iout_d_d19_d1 (Iout_d_d19_d1 ), .Iout_d_d20_d0 (Iout_d_d20_d0 ), .Iout_d_d20_d1 (Iout_d_d20_d1 ), .Iout_d_d21_d0 (Iout_d_d21_d0 ), .Iout_d_d21_d1 (Iout_d_d21_d1 ), .Iout_d_d22_d0 (Iout_d_d22_d0 ), .Iout_d_d22_d1 (Iout_d_d22_d1 ), .Iout_d_d23_d0 (Iout_d_d23_d0 ), .Iout_d_d23_d1 (Iout_d_d23_d1 ), .Iout_
tmpl_0_0dataflow__neuro_0_0append_329_72_72_4 Iappend_reg  (.Iin_d_d0_d0 (Iappend_reg_in_d_d0_d0 ), .Iin_d_d0_d1 (Iappend_reg_in_d_d0_d1 ), .Iin_d_d1_d0 (Iappend_reg_in_d_d1_d0 ), .Iin_d_d1_d1 (Iappend_reg_in_d_d1_d1 ), .Iin_d_d2_d0 (Iappend_reg_in_d_d2_d0 ), .Iin_d_d2_d1 (Iappend_reg_in_d_d2_d1 ), .Iin_d_d3_d0 (Iappend_reg_in_d_d3_d0 ), .Iin_d_d3_d1 (Iappend_reg_in_d_d3_d1 ), .Iin_d_d4_d0 (Iappend_reg_in_d_d4_d0 ), .Iin_d_d4_d1 (Iappend_reg_in_d_d4_d1 ), .Iin_d_d5_d0 (Iappend_reg_in_d_d5_d0 ), .Iin_d_d5_d1 (Iappend_reg_in_d_d5_d1 ), .Iin_d_d6_d0 (Iappend_reg_in_d_d6_d0 ), .Iin_d_d6_d1 (Iappend_reg_in_d_d6_d1 ), .Iin_d_d7_d0 (Iappend_reg_in_d_d7_d0 ), .Iin_d_d7_d1 (Iappend_reg_in_d_d7_d1 ), .Iin_d_d8_d0 (Iappend_reg_in_d_d8_d0 ), .Iin_d_d8_d1 (Iappend_reg_in_d_d8_d1 ), .Iin_d_d9_d0 (Iappend_reg_in_d_d9_d0 ), .Iin_d_d9_d1 (Iappend_reg_in_d_d9_d1 ), .Iin_d_d10_d0 (Iappend_reg_in_d_d10_d0 ), .Iin_d_d10_d1 (Iappend_reg_in_d_d10_d1 ), .Iin_d_d11_d0 (Iappend_reg_in_d_d11_d0 ), .Iin_d_d11_d1 (Iappend_reg_in_d_d11_d1 ), .Iin_d_d12_d0 (Iappend_reg_in_d_d12_d0 ), .Iin_d_d12_d1 (Iappend_reg_in_d_d12_d1 ), .Iin_d_d13_d0 (Iappend_reg_in_d_d13_d0 ), .Iin_d_d13_d1 (Iappend_reg_in_d_d13_d1 ), .Iin_d_d14_d0 (Iappend_reg_in_d_d14_d0 ), .Iin_d_d14_d1 (Iappend_reg_in_d_d14_d1 ), .Iin_d_d15_d0 (Iappend_reg_in_d_d15_d0 ), .Iin_d_d15_d1 (Iappend_reg_in_d_d15_d1 ), .Iin_d_d16_d0 (Iappend_reg_in_d_d16_d0 ), .Iin_d_d16_d1 (Iappend_reg_in_d_d16_d1 ), .Iin_d_d17_d0 (Iappend_reg_in_d_d17_d0 ), .Iin_d_d17_d1 (Iappend_reg_in_d_d17_d1 ), .Iin_d_d18_d0 (Iappend_reg_in_d_d18_d0 ), .Iin_d_d18_d1 (Iappend_reg_in_d_d18_d1 ), .Iin_d_d19_d0 (Iappend_reg_in_d_d19_d0 ), .Iin_d_d19_d1 (Iappend_reg_in_d_d19_d1 ), .Iin_d_d20_d0 (Iappend_reg_in_d_d20_d0 ), .Iin_d_d20_d1 (Iappend_reg_in_d_d20_d1 ), .Iin_d_d21_d0 (Iappend_reg_in_d_d21_d0 ), .Iin_d_d21_d1 (Iappend_reg_in_d_d21_d1 ), .Iin_d_d22_d0 (Iappend_reg_in_d_d22_d0 ), .Iin_d_d22_d1 (Iappend_reg_in_d_d22_d1 ), .Iin_d_d23_d0 (Iappend_reg_in_d_d23_d0 ), .Iin_d_d23_d1 (Iappend_reg_in_d_d23_d1 ), .Iin_d_d24_d0 (Iappend_reg_in_d_d24_d0 ), .Iin_d_d24_d1 (Iappend_reg_in_d_d24_d1 ), .Iin_d_d25_d0 (Iappend_reg_in_d_d25_d0 ), .Iin_d_d25_d1 (Iappend_reg_in_d_d25_d1 ), .Iin_d_d26_d0 (Iappend_reg_in_d_d26_d0 ), .Iin_d_d26_d1 (Iappend_reg_in_d_d26_d1 ), .Iin_d_d27_d0 (Iappend_reg_in_d_d27_d0 ), .Iin_d_d27_d1 (Iappend_reg_in_d_d27_d1 ), .Iin_d_d28_d0 (Iappend_reg_in_d_d28_d0 ), .Iin_d_d28_d1 (Iappend_reg_in_d_d28_d1 ), .Iout_d_d29_d0 (Iappend_reg_out_d_d29_d0 ), .Iout_d_d29_d1 (Iappend_reg_out_d_d29_d1 ), .Iout_d_d30_d0 (Iappend_reg_out_d_d30_d0 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
INV_X1 Inrn_reset_stge_inv  (.y(Irsb_nrn_storage_in ), .a(Ireg_data0_d6_d1 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon0  (.y(Iands_devmon0_y ), .a(Iands_devmon0_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon1  (.y(Iands_devmon1_y ), .a(Iands_devmon1_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon2  (.y(Iands_devmon2_y ), .a(Iands_devmon2_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon3  (.y(Iands_devmon3_y ), .a(Iands_devmon3_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon4  (.y(Iands_devmon4_y ), .a(Iands_devmon4_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon5  (.y(Iands_devmon5_y ), .a(Iands_devmon5_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon6  (.y(Iands_devmon6_y ), .a(Iands_devmon6_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon7  (.y(Iands_devmon7_y ), .a(Iands_devmon7_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon8  (.y(Iands_devmon8_y ), .a(Iands_devmon8_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon9  (.y(Iands_devmon9_y ), .a(Iands_devmon9_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon10  (.y(Iands_devmon10_y ), .a(Iands_devmon10_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon11  (.y(Iands_devmon11_y ), .a(Iands_devmon11_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon12  (.y(Iands_devmon12_y ), .a(Iands_devmon12_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon13  (.y(Iands_devmon13_y ), .a(Iands_devmon13_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
AND2_X1 Iands_devmon14  (.y(Iands_devmon14_y ), .a(Iands_devmon14_a ), .b(DEV_DEBUG), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_3348_748_4 Isyn_mon_y_buf  (.Iin0 (Isyn_mon_dec_y_out0 ), .Iin1 (Isyn_mon_dec_y_out1 ), .Iin2 (Isyn_mon_dec_y_out2 ), .Iin3 (Isyn_mon_dec_y_out3 ), .Iin4 (Isyn_mon_dec_y_out4 ), .Iin5 (Isyn_mon_dec_y_out5 ), .Iin6 (Isyn_mon_dec_y_out6 ), .Iin7 (Isyn_mon_dec_y_out7 ), .Iin8 (Isyn_mon_dec_y_out8 ), .Iin9 (Isyn_mon_dec_y_out9 ), .Iin10 (Isyn_mon_dec_y_out10 ), .Iin11 (Isyn_mon_dec_y_out11 ), .Iin12 (Isyn_mon_dec_y_out12 ), .Iin13 (Isyn_mon_dec_y_out13 ), .Iin14 (Isyn_mon_dec_y_out14 ), .Iin15 (Isyn_mon_dec_y_out15 ), .Iin16 (Isyn_mon_dec_y_out16 ), .Iin17 (Isyn_mon_dec_y_out17 ), .Iin18 (Isyn_mon_dec_y_out18 ), .Iin19 (Isyn_mon_dec_y_out19 ), .Iin20 (Isyn_mon_dec_y_out20 ), .Iin21 (Isyn_mon_dec_y_out21 ), .Iin22 (Isyn_mon_dec_y_out22 ), .Iin23 (Isyn_mon_dec_y_out23 ), .Iin24 (Isyn_mon_dec_y_out24 ), .Iin25 (Isyn_mon_dec_y_out25 ), .Iin26 (Isyn_mon_dec_y_out26 ), .Iin27 (Isyn_mon_dec_y_out27 ), .Iin28 (Isyn_mon_dec_y_out28 ), .Iin29 (Isyn_mon_dec_y_out29 ), .Iin30 (Isyn_mon_dec_y_out30 ), .Iin31 (Isyn_mon_dec_y_out31 ), .Iin32 (Isyn_mon_dec_y_out32 ), .Iin33 (Isyn_mon_dec_y_out33 ), .Iin34 (Isyn_mon_dec_y_out34 ), .Iin35 (Isyn_mon_dec_y_out35 ), .Iin36 (Isyn_mon_dec_y_out36 ), .Iin37 (Isyn_mon_dec_y_out37 ), .Iin38 (Isyn_mon_dec_y_out38 ), .Iin39 (Isyn_mon_dec_y_out39 ), .Iin40 (Isyn_mon_dec_y_out40 ), .Iin41 (Isyn_mon_dec_y_out41 ), .Iin42 (Isyn_mon_dec_y_out42 ), .Iin43 (Isyn_mon_dec_y_out43 ), .Iin44 (Isyn_mon_dec_y_out44 ), .Iin45 (Isyn_mon_dec_y_out45 ), .Iin46 (Isyn_mon_dec_y_out46 ), .Iin47 (Isyn_mon_dec_y_out47 ), .Iin48 (Isyn_mon_dec_y_out48 ), .Iin49 (Isyn_mon_dec_y_out49 ), .Iin50 (Isyn_mon_dec_y_out50 ), .Iin51 (Isyn_mon_dec_y_out51 ), .Iin52 (Isyn_mon_dec_y_out52 ), .Iin53 (Isyn_mon_dec_y_out53 ), .Iin54 (Isyn_mon_dec_y_out54 ), .Iin55 (Isyn_mon_dec_y_out55 ), .Iin56 (Isyn_mon_dec_y_out56 ), .Iin57 (Isyn_mon_dec_y_out57 ), .Iin58 (Isyn_mon_dec_y_out58 ), .Iin59 (Isyn_mon_dec_y_out59 ), .Iin60 (Isyn_mon_dec_y_out60 ), .Iin61 (Isyn_mon_dec_y_out61 ), .Iin62 (Isyn_mon_dec_y_out62 ), .Iin63 (Isyn_mon_dec_y_out63 ), .Iin64 (Isyn_mon_dec_y_out64 ), .Iin65 (Isyn_mon_dec_y_out65 ), .Iin66 (Isyn_mon_dec_y_out66 ), .Iin67 (Isyn_mon_dec_y_out67 ), .Iin68 (Isyn_mon_dec_y_out68 ), .Iin69 (Isyn_mon_dec_y_out69 ), .Iin70 (Isyn_mon_dec_y_out70 ), .Iin71 (Isyn_mon_dec_y_out71 ), .Iin72 (Isyn_mon_dec_y_out72 ), .Iin73 (Isyn_mon_dec_y_out73 ), .Iin74 (Isyn_mon_dec_y_out74 ), .Iin75 (Isyn_mon_dec_y_out75 ), .Iin76 (Isyn_mon_dec_y_out76 ), .Iin77 (Isyn_mon_dec_y_out77 ), .Iin78 (Isyn_mon_dec_y_out78 ), .Iin79 (Isyn_mon_dec_y_out79 ), .Iin80 (Isyn_mon_dec_y_out80 ), .Iin81 (Isyn_mon_dec_y_out81 ), .Iin82 (Isyn_mon_dec_y_out82 ), .Iin83 (Isyn_mon_dec_y_out83 ), .Iin84 (Isyn_mon_dec_y_out84 ), .Iin85 (Isyn_mon_dec_y_out85 ), .Iin86 (Isyn_mon_dec_y_out86 ), .Iin87 (Isyn_mon_dec_y_out87 ), .Iin88 (Isyn_mon_dec_y_out88 ), .Iin89 (Isyn_mon_dec_y_out89 ), .Iin90 (Isyn_mon_dec_y_out90 ), .Iin91 (Isyn_mon_dec_y_out91 ), .Iin92 (Isyn_mon_dec_y_out92 ), .Iin93 (Isyn_mon_dec_y_out93 ), .Iin94 (Isyn_mon_dec_y_out94 ), .Iin95 (Isyn_mon_dec_y_out95 ), .Iin96 (Isyn_mon_dec_y_out96 ), .Iin97 (Isyn_mon_dec_y_out97 ), .Iin98 (Isyn_mon_dec_y_out98 ), .Iin99 (Isyn_mon_dec_y_out99 ), .Iin100 (Isyn_mon_dec_y_out100 ), .Iin101 (Isyn_mon_dec_y_out101 ), .Iin102 (Isyn_mon_dec_y_out102 ), .Iin103 (Isyn_mon_dec_y_out103 ), .Iin104 (Isyn_mon_dec_y_out104 ), .Iin105 (Isyn_mon_dec_y_out105 ), .Iin106 (Isyn_mon_dec_y_out106 ), .Iin107 (Isyn_mon_dec_y_out107 ), .Iin108 (Isyn_mon_dec_y_out108 ), .Iin109 (Isyn_mon_dec_y_out109 ), .Iin110 (Isyn_mon_dec_y_out110 ), .Iin111 (Isyn_mon_dec_y_out111 ), .Iin112 (Isyn_mon_dec_y_out112 ), .Iin113 (Isyn_mon_dec_y_out113 ), .Iin114 (Isyn_mon_dec_y_out114 ), .Iin115 (Isyn_mon_dec_y_out115 ), .Iin116 (Isyn_mon_dec_y_out116 ), .Iin117 (Isyn_mon_dec_y_out117 ), .Iin118 (Isyn_mon_dec_y_out118 ), .Iin119 (Isyn_mon_dec_y_out119 ), .Iin120 (Isyn_mon_dec_y_out120 ), .Iin121 (Isyn_mon_dec_y_out121 ), .Iin122 (Isyn_mon_dec_y_out122 ), .Iin123 (Isyn_mon_dec_y_out123 ), .Iin124 (Isyn_mon_dec_y_ou
tmpl_0_0dataflow__neuro_0_0merge_331_4 Imerge_enc8reg  (.Iin1_d_d0_d0 (Iappend_enc_in_d_d0_d0 ), .Iin1_d_d0_d1 (Iappend_enc_in_d_d0_d1 ), .Iin1_d_d1_d0 (Iappend_enc_in_d_d1_d0 ), .Iin1_d_d1_d1 (Iappend_enc_in_d_d1_d1 ), .Iin1_d_d2_d0 (Iappend_enc_in_d_d2_d0 ), .Iin1_d_d2_d1 (Iappend_enc_in_d_d2_d1 ), .Iin1_d_d3_d0 (Iappend_enc_in_d_d3_d0 ), .Iin1_d_d3_d1 (Iappend_enc_in_d_d3_d1 ), .Iin1_d_d4_d0 (Iappend_enc_in_d_d4_d0 ), .Iin1_d_d4_d1 (Iappend_enc_in_d_d4_d1 ), .Iin1_d_d5_d0 (Iappend_enc_in_d_d5_d0 ), .Iin1_d_d5_d1 (Iappend_enc_in_d_d5_d1 ), .Iin1_d_d6_d0 (Iappend_enc_in_d_d6_d0 ), .Iin1_d_d6_d1 (Iappend_enc_in_d_d6_d1 ), .Iin1_d_d7_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d7_d1 (Iappend_enc_out_d_d7_d1 ), .Iin1_d_d8_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d8_d1 (Iappend_enc_out_d_d8_d1 ), .Iin1_d_d9_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d9_d1 (Iappend_enc_out_d_d9_d1 ), .Iin1_d_d10_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d10_d1 (Iappend_enc_out_d_d10_d1 ), .Iin1_d_d11_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d11_d1 (Iappend_enc_out_d_d11_d1 ), .Iin1_d_d12_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d12_d1 (Iappend_enc_out_d_d12_d1 ), .Iin1_d_d13_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d13_d1 (Iappend_enc_out_d_d13_d1 ), .Iin1_d_d14_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d14_d1 (Iappend_enc_out_d_d14_d1 ), .Iin1_d_d15_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d15_d1 (Iappend_enc_out_d_d15_d1 ), .Iin1_d_d16_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d16_d1 (Iappend_enc_out_d_d16_d1 ), .Iin1_d_d17_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d17_d1 (Iappend_enc_out_d_d17_d1 ), .Iin1_d_d18_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d18_d1 (Iappend_enc_out_d_d18_d1 ), .Iin1_d_d19_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d19_d1 (Iappend_enc_out_d_d19_d1 ), .Iin1_d_d20_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d20_d1 (Iappend_enc_out_d_d20_d1 ), .Iin1_d_d21_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d21_d1 (Iappend_enc_out_d_d21_d1 ), .Iin1_d_d22_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d22_d1 (Iappend_enc_out_d_d22_d1 ), .Iin1_d_d23_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d23_d1 (Iappend_enc_out_d_d23_d1 ), .Iin1_d_d24_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d24_d1 (Iappend_enc_out_d_d24_d1 ), .Iin1_d_d25_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d25_d1 (Iappend_enc_out_d_d25_d1 ), .Iin1_d_d26_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d26_d1 (Iappend_enc_out_d_d26_d1 ), .Iin1_d_d27_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d27_d1 (Iappend_enc_out_d_d27_d1 ), .Iin1_d_d28_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d28_d1 (Iappend_enc_out_d_d28_d1 ), .Iin1_d_d29_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d29_d1 (Iappend_enc_out_d_d29_d1 ), .Iin1_d_d30_d0 (Iappend_enc_out_d_d7_d0 ), .Iin1_d_d30_d1 (Iappend_enc_out_d_d30_d1 ), .Iin1_a (Iappend_enc_in_a ), .Iin1_v (Iappend_enc_in_v ), .Iin2_d_d0_d0 (Iappend_reg_in_d_d0_d0 ), .Iin2_d_d0_d1 (Iappend_reg_in_d_d0_d1 ), .Iin2_d_d1_d0 (Iappend_reg_in_d_d1_d0 ), .Iin2_d_d1_d1 (Iappend_reg_in_d_d1_d1 ), .Iin2_d_d2_d0 (Iappend_reg_in_d_d2_d0 ), .Iin2_d_d2_d1 (Iappend_reg_in_d_d2_d1 ), .Iin2_d_d3_d0 (Iappend_reg_in_d_d3_d0 ), .Iin2_d_d3_d1 (Iappend_reg_in_d_d3_d1 ), .Iin2_d_d4_d0 (Iappend_reg_in_d_d4_d0 ), .Iin2_d_d4_d1 (Iappend_reg_in_d_d4_d1 ), .Iin2_d_d5_d0 (Iappend_reg_in_d_d5_d0 ), .Iin2_d_d5_d1 (Iappend_reg_in_d_d5_d1 ), .Iin2_d_d6_d0 (Iappend_reg_in_d_d6_d0 ), .Iin2_d_d6_d1 (Iappend_reg_in_d_d6_d1 ), .Iin2_d_d7_d0 (Iappend_reg_in_d_d7_d0 ), .Iin2_d_d7_d1 (Iappend_reg_in_d_d7_d1 ), .Iin2_d_d8_d0 (Iappend_reg_in_d_d8_d0 ), .Iin2_d_d8_d1 (Iappend_reg_in_d_d8_d1 ), .Iin2_d_d9_d0 (Iappend_reg_in_d_d9_d0 ), .Iin2_d_d9_d1 (Iappend_reg_in_d_d9_d1 ), .Iin2_d_d10_d0 (Iappend_reg_in_d_d10_d0 ), .Iin2_d_d10_d1 (Iappend_reg_in_d_d10_d1 ), .Iin2_d_d11_d0 (Iappend_reg_in_d_d11_d0 ), .Iin2_d_d11_d1 (Iappend_reg_in_d_d11_d1 ), .Iin2_d_d12_d0 (Iappend_reg_in_d_d12_d0 ), .Iin2_d_d12_d1 (Iappend_reg_in_d_d12_d1 ), .Iin2_d_d13_d0 (Iappend_reg_in_d_d13_d0 ), .Iin2_d_d13_d1 (Iappend_reg_in_d_d13_d1 ), .Iin2_d_d14_d0 (Iappend_reg_in_d_d14_d0 ), .Iin2_d_d14_d1 (Iappend_reg_in_d_d14_d1 ), .Iin2_d_d15_d0 (Iappend_reg_in_d_d15_d0 ), .Iin2_d_d15_d1 (Iappend_reg_in_d_d1
tmpl_0_0dataflow__neuro_0_0fifo_37_73_4 Ififo_enc2mrg  (.Iin_d_d0_d0 (Iencoder_out_d_d0_d0 ), .Iin_d_d0_d1 (Iencoder_out_d_d0_d1 ), .Iin_d_d1_d0 (Iencoder_out_d_d1_d0 ), .Iin_d_d1_d1 (Iencoder_out_d_d1_d1 ), .Iin_d_d2_d0 (Iencoder_out_d_d2_d0 ), .Iin_d_d2_d1 (Iencoder_out_d_d2_d1 ), .Iin_d_d3_d0 (Iencoder_out_d_d3_d0 ), .Iin_d_d3_d1 (Iencoder_out_d_d3_d1 ), .Iin_d_d4_d0 (Iencoder_out_d_d4_d0 ), .Iin_d_d4_d1 (Iencoder_out_d_d4_d1 ), .Iin_d_d5_d0 (Iencoder_out_d_d5_d0 ), .Iin_d_d5_d1 (Iencoder_out_d_d5_d1 ), .Iin_d_d6_d0 (Iencoder_out_d_d6_d0 ), .Iin_d_d6_d1 (Iencoder_out_d_d6_d1 ), .Iin_a (Iencoder_out_a ), .Iin_v (Iencoder_out_v ), .Iout_d_d0_d0 (Iappend_enc_in_d_d0_d0 ), .Iout_d_d0_d1 (Iappend_enc_in_d_d0_d1 ), .Iout_d_d1_d0 (Iappend_enc_in_d_d1_d0 ), .Iout_d_d1_d1 (Iappend_enc_in_d_d1_d1 ), .Iout_d_d2_d0 (Iappend_enc_in_d_d2_d0 ), .Iout_d_d2_d1 (Iappend_enc_in_d_d2_d1 ), .Iout_d_d3_d0 (Iappend_enc_in_d_d3_d0 ), .Iout_d_d3_d1 (Iappend_enc_in_d_d3_d1 ), .Iout_d_d4_d0 (Iappend_enc_in_d_d4_d0 ), .Iout_d_d4_d1 (Iappend_enc_in_d_d4_d1 ), .Iout_d_d5_d0 (Iappend_enc_in_d_d5_d0 ), .Iout_d_d5_d1 (Iappend_enc_in_d_d5_d1 ), .Iout_d_d6_d0 (Iappend_enc_in_d_d6_d0 ), .Iout_d_d6_d1 (Iappend_enc_in_d_d6_d1 ), .Iout_a (Iappend_enc_in_a ), .Iout_v (Iappend_enc_in_v ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0fifo_313_73_4 Ififo_dmx2dec  (.Iin_d_d0_d0 (I_demux_out1_d_d0_d0 ), .Iin_d_d0_d1 (I_demux_out1_d_d0_d1 ), .Iin_d_d1_d0 (I_demux_out1_d_d1_d0 ), .Iin_d_d1_d1 (I_demux_out1_d_d1_d1 ), .Iin_d_d2_d0 (I_demux_out1_d_d2_d0 ), .Iin_d_d2_d1 (I_demux_out1_d_d2_d1 ), .Iin_d_d3_d0 (I_demux_out1_d_d3_d0 ), .Iin_d_d3_d1 (I_demux_out1_d_d3_d1 ), .Iin_d_d4_d0 (I_demux_out1_d_d4_d0 ), .Iin_d_d4_d1 (I_demux_out1_d_d4_d1 ), .Iin_d_d5_d0 (I_demux_out1_d_d5_d0 ), .Iin_d_d5_d1 (I_demux_out1_d_d5_d1 ), .Iin_d_d6_d0 (I_demux_out1_d_d6_d0 ), .Iin_d_d6_d1 (I_demux_out1_d_d6_d1 ), .Iin_d_d7_d0 (I_demux_out1_d_d7_d0 ), .Iin_d_d7_d1 (I_demux_out1_d_d7_d1 ), .Iin_d_d8_d0 (I_demux_out1_d_d8_d0 ), .Iin_d_d8_d1 (I_demux_out1_d_d8_d1 ), .Iin_d_d9_d0 (I_demux_out1_d_d9_d0 ), .Iin_d_d9_d1 (I_demux_out1_d_d9_d1 ), .Iin_d_d10_d0 (I_demux_out1_d_d10_d0 ), .Iin_d_d10_d1 (I_demux_out1_d_d10_d1 ), .Iin_d_d11_d0 (I_demux_out1_d_d11_d0 ), .Iin_d_d11_d1 (I_demux_out1_d_d11_d1 ), .Iin_d_d12_d0 (I_demux_out1_d_d12_d0 ), .Iin_d_d12_d1 (I_demux_out1_d_d12_d1 ), .Iin_a (Ififo_dmx2dec_in_a ), .Iin_v (Ififo_dmx2dec_in_v ), .Iout_d_d0_d0 (Idecoder_in_d_d0_d0 ), .Iout_d_d0_d1 (Idecoder_in_d_d0_d1 ), .Iout_d_d1_d0 (Idecoder_in_d_d1_d0 ), .Iout_d_d1_d1 (Idecoder_in_d_d1_d1 ), .Iout_d_d2_d0 (Idecoder_in_d_d2_d0 ), .Iout_d_d2_d1 (Idecoder_in_d_d2_d1 ), .Iout_d_d3_d0 (Idecoder_in_d_d3_d0 ), .Iout_d_d3_d1 (Idecoder_in_d_d3_d1 ), .Iout_d_d4_d0 (Idecoder_in_d_d4_d0 ), .Iout_d_d4_d1 (Idecoder_in_d_d4_d1 ), .Iout_d_d5_d0 (Idecoder_in_d_d5_d0 ), .Iout_d_d5_d1 (Idecoder_in_d_d5_d1 ), .Iout_d_d6_d0 (Idecoder_in_d_d6_d0 ), .Iout_d_d6_d1 (Idecoder_in_d_d6_d1 ), .Iout_d_d7_d0 (Idecoder_in_d_d7_d0 ), .Iout_d_d7_d1 (Idecoder_in_d_d7_d1 ), .Iout_d_d8_d0 (Idecoder_in_d_d8_d0 ), .Iout_d_d8_d1 (Idecoder_in_d_d8_d1 ), .Iout_d_d9_d0 (Idecoder_in_d_d9_d0 ), .Iout_d_d9_d1 (Idecoder_in_d_d9_d1 ), .Iout_d_d10_d0 (Idecoder_in_d_d10_d0 ), .Iout_d_d10_d1 (Idecoder_in_d_d10_d1 ), .Iout_d_d11_d0 (Idecoder_in_d_d11_d0 ), .Iout_d_d11_d1 (Idecoder_in_d_d11_d1 ), .Iout_d_d12_d0 (Idecoder_in_d_d12_d0 ), .Iout_d_d12_d1 (Idecoder_in_d_d12_d1 ), .Iout_a (Idecoder_in_a ), .Iout_v (Idecoder_in_v ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
endmodule