actlib_dataflow_neuro/test/unit_tests/texel_dualcore_innovus/test.prsim

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2022-04-21 14:31:35 +02:00
# watchall
set c.bd_dly_cfg[0] 1
set c.bd_dly_cfg[1] 1
set c.bd_dly_cfg[2] 1
set c.bd_dly_cfg[3] 1
set c.bd_dly_cfg2[0] 1
set c.bd_dly_cfg2[1] 1
set-bd-channel-neutral "c.in" 32
set c.out.a 0
set c.loopback_en 1
# set c.loopback_en 0
# set R
cycle