2022-02-28 18:54:52 +01:00
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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2022-03-01 17:14:10 +01:00
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defproc merge_2 (avMx1of2<2> in1; avMx1of2<2> in2; avMx1of2<2> out){
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2022-02-28 18:54:52 +01:00
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2022-03-01 17:14:10 +01:00
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merge<2> merge_cell(.in1=in1, .in2=in2,.out = out);
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2022-02-28 18:54:52 +01:00
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//Low active Reset
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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2022-03-01 13:26:29 +01:00
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merge_cell.supply.vss = GND;
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merge_cell.supply.vdd = Vdd;
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merge_cell.reset_B = _reset_B;
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2022-02-28 18:54:52 +01:00
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}
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2022-03-01 17:14:10 +01:00
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merge_2 my_merge;
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