2022-06-17 11:56:01 +02:00
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module tmpl_0_0dataflow__neuro_0_0sigbuf_3120_4(in, Iout0 , vdd, vss);
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input vdd;
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input vss;
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input in;
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// -- signals ---
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output Iout0 ;
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2022-06-17 12:29:45 +02:00
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wire in;
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2022-06-17 11:56:01 +02:00
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// --- instances
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BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
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endmodule
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