actlib_dataflow_neuro/test/unit_tests/register_wrw/run/prsim.out

t.registers.ack_dly.dly[3].bufchain[7].y t.registers.ack_dly.dly[2].bufchain[3]._y t.registers.clk_dly.dly[0].bufchain[2]._y t.registers.clk_dly.dly[5].bufchain[14].y t.registers.clk_dly.dly[0].bufchain[11]._y t.registers.clk_dly.dly[3].bufchain[0].y t.registers.clk_dly.dly[1].bufchain[12].y t.dly_cfg[1] t.registers.ack_dly.dly[5].bufchain[10].y t.registers.ff[0].d t.registers.ack_dly.dly[3].bufchain[10].y t.registers.ff[4].clk_B t.registers.val_chck[7].y t.registers.ack_dly.dly[0].bufchain[4].y t.registers.clk_dly.dly[4].bufchain[3].y t.registers.output_buf._in_vX[0] t.registers.ack_dly.dly[1].bufchain[12].y t.registers.clk_dly.dly[0].bufchain[10]._y t.registers.ff[6].clk_B t.registers.clock_buffer[1].buf1._y t.registers.ack_dly._a[2] t.registers.address_propagator_t[0].y t.registers.ack_dly.dly[5].bufchain[11].y t.registers.bitselector_f[0].out t.in.d.d[0].f t.in.v t.registers.ack_dly.dly[1].bufchain[2].y t.registers.or_encoder[2].a t.registers._clock[0] t.registers.ack_dly.dly[0].bufchain[3]._y t.registers.clk_dly.dly[4].bufchain[4]._y t.registers._in_v_temp_write t.registers.word_selector_f[0].a t.registers._in_a_write t.registers.clk_dly.dly[6].bufchain[7].y t.registers.clk_dly.dly[3].y t.registers.val_chck[3].y t.dly_cfg[2] t.registers.ack_dly.dly[4].bufchain[5].y t.registers._in_v_temp_buf[0] t.registers.clk_dly.dly[6].bufchain[14]._y t.registers.clk_dly.dly[5].bufchain[10].y t.registers.ack_dly.dly[3].bufchain[8].y t.registers.word_to_read[0].y t.registers.clk_dly.dly[5].bufchain[13].y t.registers.ack_dly.dly[6].bufchain[3]._y t.registers.ack_dly.dly[0].bufchain[5]._y t.registers.ack_dly.dly[3].bufchain[14].y t.registers.clk_dly.dly[2].bufchain[11]._y t.registers.ack_dly.dly[1].bufchain[0].y t.registers.clk_dly.dly[2].bufchain[3].y t.registers.clk_dly.dly[6].bufchain[5].y t.registers.ack_dly.dly[0].bufchain[12]._y t.registers.word_selector_f[2].y t.registers.output_buf.vc.ct.in[3] t.registers.clk_dly.dly[2].bufchain[13].y t.registers.atree[0].in[0] t.registers.clk_dly.dly[5].bufchain[4]._y t.registers.address_propagator_f[0]._y t.registers.clk_dly.dly[0].bufchain[8].y t.registers.clk_dly.dly[3].bufchain[1].y t.registers.ack_dly.dly[6].bufchain[1]._y t.registers.clk_dly.dly[3].bufchain[11].y t.registers.ack_dly.dly[2].bufchain[1].y t.registers.output_buf.vc.ct.tmp[4] t.registers.clk_dly.dly[2].bufchain[5].y t.registers.output_buf.vc.ct.tmp[5] t.registers.ack_dly.dly[4].bufchain[12]._y t.registers.ack_dly.mu2[0]._y t.registers.ack_dly.dly[6].bufchain[1].y t.registers.clk_dly.dly[4].bufchain[0].y t.registers.clk_dly.dly[3].bufchain[5]._y t.registers.ack_dly.dly[2].bufchain[11]._y t.in.d.d[1].f t.registers.clk_dly.dly[6].bufchain[10].y t.registers.ack_dly.dly[0].bufchain[5].y t.registers.address_propagator_t[0]._y t.registers.ack_dly.dly[1].bufchain[6]._y t.registers.val_input.OR2_tf[3]._y t.registers.clk_dly.dly[2].bufchain[2].y t.registers.clk_dly.dly[6].bufchain[8]._y t.registers.clk_dly.dly[1].bufchain[12]._y t.registers.ack_dly.dly[0].bufchain[6].y t.registers.word_to_read[3].y t.registers.clk_dly._a[2] t.registers._clock_temp t.registers.ff[7]._clk_B t.in.a t.registers.address_propagator_f[1].y t.registers.ack_dly.dly[3].bufchain[13].y t.registers.val_chck[6].y t.registers.ff[1]._clk_B t.registers.word_selector_f[1].y t.registers.ff[1].d t.registers.clk_dly.dly[6].bufchain[1].y t.registers.output_buf._in_v t.registers.clk_dly.dly[6].bufchain[6].y t.registers.ack_dly.dly[0].bufchain[2].y t.registers.atree[0].in[1] t.registers.word_to_read[1]._y t.registers.clk_dly.dly[1].bufchain[11].y t.registers.address_propagator_t[1].y t.registers.clk_dly.dly[3].a t.registers.clk_dly.dly[1].bufchain[2]._y t.registers.clk_dly.dly[1].bufchain[14]._y t.registers.output_buf._out_a_BX_f[0] t.registers.ack_dly.dly[6].bufchain[8].y t.registers.clk_dly.dly[4].bufchain[9].y t.registers._clock_word_temp[3] t.registers.clk_dly.dly[3].bufchain[3]._y t.registers.ack_dly.dly[4].bufchain[2].y t.registers.clk_dly.dly[2].bufchain[10]._y t.registers.ack_dly.dly[1].bufchain[1].y t.registers.ack_dly.dly[5].bufchain[6].y t.registers.ack_dly.dly
[0] start test
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	    140994 t.registers.ff[4].clk_B : 1  [by t.registers.clock_buffer[2].buf1._y:=0]
	    179718 t.registers.ff[2].clk_B : 1  [by t.registers.clock_buffer[1].buf1._y:=0]
	    187387 t.registers.ff[0].clk_B : 1  [by t.registers.clock_buffer[0].buf1._y:=0]
	    198536 t.registers.ff[6].clk_B : 1  [by t.registers.clock_buffer[3].buf1._y:=0]
[1] reset completed
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	   4421589 t.registers.ff[0].clk_B : 0  [by t.registers.clock_buffer[0].buf1._y:=1]
	   5922746 t.registers.ff[0].clk_B : 1  [by t.registers.clock_buffer[0].buf1._y:=0]
WARNING: unstable `t.registers.ff[1]._sqib'+
>> cause: t.registers.ff[1].__clk_B (val: 1)
WARNING: weak-interference `t.registers.ff[1]._sqi'
>> cause: t.registers.ff[1]._sqib (val: X)
>> time:    5949568
WARNING: weak-interference `t.data[0].d[1]'
>> cause: t.registers.ff[1]._sqib (val: X)
>> time:    5949568
WARNING: weak-interference `t.registers.ff[1].q_B'
>> cause: t.data[0].d[1] (val: X)
>> time:    5949569
WARNING: weak-unstable `t.registers.ff[1]._sqib'-
>> cause: t.registers.ff[1]._sqi (val: X)
>> time:    5949575
WRONG ASSERT:	"t.registers.ff[1].q" has value X and not 1.
[3] first writing done
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