actlib_dataflow_neuro/test/unit_tests/texel_small/run/prsim.in

random_seed 0
initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
set Reset 1

mode reset
cycle
status U
watchall


set c.bd_dly_cfg[0] 1
set c.bd_dly_cfg[1] 1
set c.bd_dly_cfg[2] 1
set c.bd_dly_cfg[3] 1

set c.bd_dly_cfg2[0] 1
set c.bd_dly_cfg2[1] 1

set-bd-channel-neutral "c.in" 14
set c.out.a 0
# set c.loopback_en 1
set c.loopback_en 0
set Reset 1

cycle

mode run
status X
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle

# Reading address 0
set-bd-data-valid "c.in" 14 8192
cycle
set c.in.r 1
cycle
assert c.in.a 1

# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

# Should first get loopback
# Receiving output 0 from register 0
# assert-bd-channel-valid "c.out" 14 8192
# set c.out.a 1
# cycle
# assert-bd-channel-neutral "c.out" 14
# set c.out.a 0
# cycle


# Expect register read packet to arrive
# Receiving output 0 from register 0
assert-bd-channel-valid "c.out" 14 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Disable loopback cus it's annoying
set c.loopback_en 0
cycle

# Writing 17 to address 1
set-bd-data-valid "c.in" 14 12561
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0


# Writing 255 to address 5
set-bd-data-valid "c.in" 14 16373
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

# Reading address 1
system "echo '[] Reading reg 1'"
set-bd-data-valid "c.in" 14 8193
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Reading address 5
system "echo '[] Reading reg 5'"
set-bd-data-valid "c.in" 14 8197
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0


# Receiving output 17 from register 1
system "echo '[] Receiving 17'"
assert-bd-channel-valid "c.out" 14 273
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

system "echo '[] Receiving 4085'"
# Receiving output 255 from register 5
assert-bd-channel-valid "c.out" 14 4085
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle



# SEND PACKET TO CHANGE TO SYNAPSE HANDSHAKING
# Writing 255 to address 0
set-bd-data-valid "c.in" 14 16368
cycle
set c.in.r 1
cycle
assert c.in.a 1

# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0


# SPIKES



# Sending spike to synapse [0,1]
system "echo '[] Spike'"
set-bd-data-valid "c.in" 14 2
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,1]
assert-bd-channel-valid "c.out" 14 2
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [1,3]
system "echo '[] Spike'"
set-bd-data-valid "c.in" 14 7
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [1,3]
assert-bd-channel-valid "c.out" 14 7
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [1,2]
system "echo '[] Spike'"
set-bd-data-valid "c.in" 14 5
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [1,2]
assert-bd-channel-valid "c.out" 14 5
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [1,3]
system "echo '[] Spike'"
set-bd-data-valid "c.in" 14 7
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [1,3]
assert-bd-channel-valid "c.out" 14 7
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [0,2]
set-bd-data-valid "c.in" 14 4
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,2]
assert-bd-channel-valid "c.out" 14 4
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [0,3]
set-bd-data-valid "c.in" 14 6
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,3]
assert-bd-channel-valid "c.out" 14 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [0,1]
set-bd-data-valid "c.in" 14 2
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,1]
assert-bd-channel-valid "c.out" 14 2
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [0,0]
set-bd-data-valid "c.in" 14 0
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,0]
assert-bd-channel-valid "c.out" 14 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [0,0]
set-bd-data-valid "c.in" 14 0
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,0]
assert-bd-channel-valid "c.out" 14 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle

# Sending spike to synapse [0,3]
set-bd-data-valid "c.in" 14 6
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0

    
# Receiving output spike [0,3]
assert-bd-channel-valid "c.out" 14 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle