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Merge remote-tracking branch 'origin/dev' into dev

This commit is contained in:
Michele 2022-03-01 13:26:32 +01:00
parent 340a20e49e fc4ccea3c0
commit 0a8496d4f7
18 changed files with 1721 additions and 19 deletions
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60
dataflow_neuro/primitives.act
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@ -5,6 +5,8 @@
* Copyright (c) 2022 University of Groningen - Ole Richter * Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella * Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex * Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* *
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
* *
@ -150,6 +152,64 @@ namespace tmpl {
) )
} }
/**
* Buffer_S template.
* S maybe stands for special.
* Like a buffer, except that the output function block does not load the data in
* until the input data is valid.
* Not entirely sure what the point of it is,
* Ole says is useful for funky timing scenarios.
*/
export template<pint N>
defproc buffer_s (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N];
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v, _in_vX[N];
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> in_v_bufN(.in = in.v, .out = _in_vX, .supply = supply);
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].n2=_in_vX[i];
t_buf_func[i].n2=_in_vX[i];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
export template<pint N> export template<pint N>
defproc demux (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; avMx1of2<1> cond; power supply) { defproc demux (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; avMx1of2<1> cond; power supply) {
//control //control

112
dataflow_neuro/treegates.act
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@ -3,6 +3,9 @@
* This file is part of ACT dataflow neuro library * This file is part of ACT dataflow neuro library
* *
* Copyright (c) 2022 University of Groningen - Ole Richter * Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Madison Cotteret
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2021 Rajit Manohar * Copyright (c) 2021 Rajit Manohar
* *
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
@ -146,6 +149,115 @@ defproc ortree (bool? in[N]; bool! out; power supply)
out = tmp[end]; out = tmp[end];
} }
export template<pint N>
defproc andtree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
(k:N:tmp[k] = in[k];)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
AND2_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
AND3_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
C3Els[tree3Index].a = tmp[i];
C3Els[tree3Index].b = tmp[i+1];
C3Els[tree3Index].c = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
}
/* /*
* Build a completion tree using a combination of 2-input and 3-input * Build a completion tree using a combination of 2-input and 3-input
* C-elements * C-elements

48
test/prsim_plot.py
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@ -53,6 +53,20 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
else: else:
raise Exception("Unknown colour given. I cba to code up general colours atm.") raise Exception("Unknown colour given. I cba to code up general colours atm.")
# Check if start time given
for arg in argv:
r = re.findall(r'-t0=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
entries = [e for e in entries if int(e[0]) >= int(r[0])]
# Check if end time given
for arg in argv:
r = re.findall(r'-t1=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
entries = [e for e in entries if int(e[0]) <= int(r[0])]
# Check if user gave an include filter # Check if user gave an include filter
include_given = False include_given = False
@ -72,6 +86,18 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
exclude_given = True exclude_given = True
exclude_re = r[0][1] exclude_re = r[0][1]
# Check if user gave "keep all times" flag
# This is so you can look at certain signals only
# without them all bunching up.
include_all_times = False
for arg in argv:
r = re.findall(r'(-alltimes?)', arg)
if len(r) >= 1:
include_all_times = True
# Get list of all times (before filtering)
unique_times = np.unique([int(e[0]) for e in entries])
assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously." assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
if include_given: print(f"Including signals that match regex {include_re}") if include_given: print(f"Including signals that match regex {include_re}")
if exclude_given: print(f"Excluding signals that match regex {exclude_re}") if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
@ -82,27 +108,15 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
if exclude_given: if exclude_given:
entries = [e for e in entries if re.search(exclude_re, e[1]) == None] entries = [e for e in entries if re.search(exclude_re, e[1]) == None]
# Check if start time given
for arg in argv:
r = re.findall(r'-t0=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
entries = [e for e in entries if int(e[0]) >= int(r[0])]
# Check if end time given
for arg in argv:
r = re.findall(r'-t1=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
entries = [e for e in entries if int(e[0]) <= int(r[0])]
assert len(entries) >= 1, "No valid entries in prsim.out!" assert len(entries) >= 1, "No valid entries in prsim.out!"
# Get list of all sigs and times
times = np.array([int(e[0]) for e in entries])
unique_times = np.unique(times)
num_times = unique_times.shape[0] num_times = unique_times.shape[0]
# Get list of all times (after filtering)
times = np.array([int(e[0]) for e in entries])
if not include_all_times: unique_times = np.unique(times)
# Get list of all sigs
sigs = np.array([e[1] for e in entries]) sigs = np.array([e[1] for e in entries])
unique_sigs = np.unique(sigs) unique_sigs = np.unique(sigs)
num_sigs = unique_sigs.shape[0] num_sigs = unique_sigs.shape[0]

118
test/unit_tests/andtree_15/run/prsim.out Normal file
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@ -0,0 +1,118 @@
t.in[0] t.at.tmp[22] t.in[5] t.in[2] t.at.tmp[15] t.in[3] t.at.tmp[23] t.at.C2Els[0]._y t.in[7] t.in[6] t.at.C2Els[3]._y t.in[4] t.at.C3Els[0]._y t.in[12] t.out t.at.tmp[21] t.at.C2Els[6]._y t.in[11] t.at.tmp[17] t.in[14] t.in[1] t.in[10] t.in[9] t.at.C2Els[5]._y t.at.tmp[19] t.at.tmp[20] t.at.tmp[24] t.in[13] t.at.tmp[16] t.at.C2Els[4]._y t.in[8] t.at.tmp[18] t.at.C2Els[2]._y t.at.C3Els[2]._y t.at.C2Els[1]._y t.at.C2Els[7]._y t.at.C3Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[14] : 0
0 t.in[2] : 0
0 t.in[6] : 0
0 t.in[13] : 0
0 t.in[5] : 0
0 t.in[12] : 0
0 t.in[11] : 0
0 t.in[1] : 0
0 t.in[4] : 0
0 t.in[10] : 0
0 t.in[9] : 0
0 t.in[3] : 0
0 t.in[8] : 0
0 t.in[7] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
2 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
114 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
153 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
168 t.at.C3Els[1]._y : 1 [by t.at.tmp[19]:=0]
659 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
672 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
712 t.out : 0 [by t.at.C3Els[2]._y:=1]
1137 t.at.C2Els[5]._y : 1 [by t.in[11]:=0]
1552 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
1728 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
1748 t.at.C2Els[7]._y : 1 [by t.at.tmp[18]:=0]
4753 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
4800 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
7092 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
7108 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
7809 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
10467 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
54565 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]
65367 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
68289 t.at.C2Els[6]._y : 1 [by t.at.tmp[16]:=0]
68293 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
[] setting some bits high
68293 t.in[0] : 1
68293 t.in[11] : 1
68293 t.in[10] : 1
68293 t.in[9] : 1
68293 t.in[2] : 1
68293 t.in[8] : 1
68293 t.in[7] : 1
68293 t.in[6] : 1
68293 t.in[5] : 1
68293 t.in[1] : 1
68293 t.in[4] : 1
68293 t.in[3] : 1
68308 t.at.C2Els[4]._y : 0 [by t.in[8]:=1]
68348 t.at.C2Els[2]._y : 0 [by t.in[4]:=1]
77422 t.at.C2Els[5]._y : 0 [by t.in[10]:=1]
82197 t.at.tmp[17] : 1 [by t.at.C2Els[2]._y:=0]
98088 t.at.tmp[19] : 1 [by t.at.C2Els[4]._y:=0]
102234 t.at.tmp[20] : 1 [by t.at.C2Els[5]._y:=0]
105224 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
111541 t.at.C2Els[3]._y : 0 [by t.in[6]:=1]
111963 t.at.tmp[18] : 1 [by t.at.C2Els[3]._y:=0]
119567 t.at.tmp[15] : 1 [by t.at.C2Els[0]._y:=0]
119946 t.at.C2Els[1]._y : 0 [by t.in[3]:=1]
119947 t.at.tmp[16] : 1 [by t.at.C2Els[1]._y:=0]
119948 t.at.C2Els[6]._y : 0 [by t.at.tmp[16]:=1]
140153 t.at.tmp[22] : 1 [by t.at.C2Els[6]._y:=0]
160677 t.at.C2Els[7]._y : 0 [by t.at.tmp[18]:=1]
160959 t.at.tmp[23] : 1 [by t.at.C2Els[7]._y:=0]
[] setting all bits high
160959 t.in[12] : 1
160959 t.in[14] : 1
160959 t.in[13] : 1
161727 t.at.C3Els[0]._y : 0 [by t.in[13]:=1]
161730 t.at.tmp[21] : 1 [by t.at.C3Els[0]._y:=0]
184171 t.at.C3Els[1]._y : 0 [by t.at.tmp[21]:=1]
184722 t.at.tmp[24] : 1 [by t.at.C3Els[1]._y:=0]
185793 t.at.C3Els[2]._y : 0 [by t.at.tmp[24]:=1]
186747 t.out : 1 [by t.at.C3Els[2]._y:=0]
[] setting some low
186747 t.in[10] : 0
187828 t.at.C2Els[5]._y : 1 [by t.in[10]:=0]
242298 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
243280 t.at.C3Els[1]._y : 1 [by t.at.tmp[20]:=0]
243298 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
247311 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
251314 t.out : 0 [by t.at.C3Els[2]._y:=1]
[] setting all low
251314 t.in[0] : 0
251314 t.in[14] : 0
251314 t.in[2] : 0
251314 t.in[6] : 0
251314 t.in[5] : 0
251314 t.in[13] : 0
251314 t.in[12] : 0
251314 t.in[1] : 0
251314 t.in[4] : 0
251314 t.in[11] : 0
251314 t.in[9] : 0
251314 t.in[3] : 0
251314 t.in[8] : 0
251314 t.in[7] : 0
251517 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
251656 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
251816 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
251885 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
253168 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
253179 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
256074 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
272898 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
273102 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
288002 t.at.C2Els[7]._y : 1 [by t.at.tmp[17]:=0]
288017 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
296215 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
296216 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
296253 t.at.C2Els[6]._y : 1 [by t.at.tmp[15]:=0]
296992 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
307860 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]

BIN
test/unit_tests/andtree_15/run/prsim.pdf Normal file
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139
test/unit_tests/andtree_15/run/test.prs Normal file
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@ -0,0 +1,139 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C2Els[2].a"&"t.at.C2Els[2].b"->"t.at.C2Els[2]._y"-
~("t.at.C2Els[2].a"&"t.at.C2Els[2].b")->"t.at.C2Els[2]._y"+
"t.at.C2Els[2]._y"->"t.at.C2Els[2].y"-
~("t.at.C2Els[2]._y")->"t.at.C2Els[2].y"+
"t.at.C2Els[3].a"&"t.at.C2Els[3].b"->"t.at.C2Els[3]._y"-
~("t.at.C2Els[3].a"&"t.at.C2Els[3].b")->"t.at.C2Els[3]._y"+
"t.at.C2Els[3]._y"->"t.at.C2Els[3].y"-
~("t.at.C2Els[3]._y")->"t.at.C2Els[3].y"+
"t.at.C2Els[4].a"&"t.at.C2Els[4].b"->"t.at.C2Els[4]._y"-
~("t.at.C2Els[4].a"&"t.at.C2Els[4].b")->"t.at.C2Els[4]._y"+
"t.at.C2Els[4]._y"->"t.at.C2Els[4].y"-
~("t.at.C2Els[4]._y")->"t.at.C2Els[4].y"+
"t.at.C2Els[5].a"&"t.at.C2Els[5].b"->"t.at.C2Els[5]._y"-
~("t.at.C2Els[5].a"&"t.at.C2Els[5].b")->"t.at.C2Els[5]._y"+
"t.at.C2Els[5]._y"->"t.at.C2Els[5].y"-
~("t.at.C2Els[5]._y")->"t.at.C2Els[5].y"+
"t.at.C2Els[6].a"&"t.at.C2Els[6].b"->"t.at.C2Els[6]._y"-
~("t.at.C2Els[6].a"&"t.at.C2Els[6].b")->"t.at.C2Els[6]._y"+
"t.at.C2Els[6]._y"->"t.at.C2Els[6].y"-
~("t.at.C2Els[6]._y")->"t.at.C2Els[6].y"+
"t.at.C2Els[7].a"&"t.at.C2Els[7].b"->"t.at.C2Els[7]._y"-
~("t.at.C2Els[7].a"&"t.at.C2Els[7].b")->"t.at.C2Els[7]._y"+
"t.at.C2Els[7]._y"->"t.at.C2Els[7].y"-
~("t.at.C2Els[7]._y")->"t.at.C2Els[7].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
"t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c"->"t.at.C3Els[1]._y"-
~("t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c")->"t.at.C3Els[1]._y"+
"t.at.C3Els[1]._y"->"t.at.C3Els[1].y"-
~("t.at.C3Els[1]._y")->"t.at.C3Els[1].y"+
"t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c"->"t.at.C3Els[2]._y"-
~("t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c")->"t.at.C3Els[2]._y"+
"t.at.C3Els[2]._y"->"t.at.C3Els[2].y"-
~("t.at.C3Els[2]._y")->"t.at.C3Els[2].y"+
= "t.at.tmp[15]" "t.at.C2Els[6].a"
= "t.at.tmp[15]" "t.at.C2Els[0].y"
= "t.at.tmp[16]" "t.at.C2Els[6].b"
= "t.at.tmp[16]" "t.at.C2Els[1].y"
= "t.at.tmp[17]" "t.at.C2Els[7].a"
= "t.at.tmp[17]" "t.at.C2Els[2].y"
= "t.at.tmp[18]" "t.at.C2Els[7].b"
= "t.at.tmp[18]" "t.at.C2Els[3].y"
= "t.at.tmp[19]" "t.at.C3Els[1].a"
= "t.at.tmp[19]" "t.at.C2Els[4].y"
= "t.at.tmp[20]" "t.at.C3Els[1].b"
= "t.at.tmp[20]" "t.at.C2Els[5].y"
= "t.at.tmp[21]" "t.at.C3Els[1].c"
= "t.at.tmp[21]" "t.at.C3Els[0].y"
= "t.at.tmp[22]" "t.at.C3Els[2].a"
= "t.at.tmp[22]" "t.at.C2Els[6].y"
= "t.at.tmp[23]" "t.at.C3Els[2].b"
= "t.at.tmp[23]" "t.at.C2Els[7].y"
= "t.at.tmp[24]" "t.at.C3Els[2].c"
= "t.at.tmp[24]" "t.at.C3Els[1].y"
= "t.at.supply.vdd" "t.at.C3Els[2].vdd"
= "t.at.supply.vdd" "t.at.C3Els[1].vdd"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[7].vdd"
= "t.at.supply.vdd" "t.at.C2Els[6].vdd"
= "t.at.supply.vdd" "t.at.C2Els[5].vdd"
= "t.at.supply.vdd" "t.at.C2Els[4].vdd"
= "t.at.supply.vdd" "t.at.C2Els[3].vdd"
= "t.at.supply.vdd" "t.at.C2Els[2].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[2].vss"
= "t.at.supply.vss" "t.at.C3Els[1].vss"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[7].vss"
= "t.at.supply.vss" "t.at.C2Els[6].vss"
= "t.at.supply.vss" "t.at.C2Els[5].vss"
= "t.at.supply.vss" "t.at.C2Els[4].vss"
= "t.at.supply.vss" "t.at.C2Els[3].vss"
= "t.at.supply.vss" "t.at.C2Els[2].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C2Els[1].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C2Els[1].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C2Els[2].a"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.in[5]" "t.at.C2Els[2].b"
= "t.at.in[5]" "t.at.tmp[5]"
= "t.at.in[6]" "t.at.C2Els[3].a"
= "t.at.in[6]" "t.at.tmp[6]"
= "t.at.in[7]" "t.at.C2Els[3].b"
= "t.at.in[7]" "t.at.tmp[7]"
= "t.at.in[8]" "t.at.C2Els[4].a"
= "t.at.in[8]" "t.at.tmp[8]"
= "t.at.in[9]" "t.at.C2Els[4].b"
= "t.at.in[9]" "t.at.tmp[9]"
= "t.at.in[10]" "t.at.C2Els[5].a"
= "t.at.in[10]" "t.at.tmp[10]"
= "t.at.in[11]" "t.at.C2Els[5].b"
= "t.at.in[11]" "t.at.tmp[11]"
= "t.at.in[12]" "t.at.C3Els[0].a"
= "t.at.in[12]" "t.at.tmp[12]"
= "t.at.in[13]" "t.at.C3Els[0].b"
= "t.at.in[13]" "t.at.tmp[13]"
= "t.at.in[14]" "t.at.C3Els[0].c"
= "t.at.in[14]" "t.at.tmp[14]"
= "t.at.out" "t.at.C3Els[2].y"
= "t.at.out" "t.at.tmp[25]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"
= "t.in[5]" "t.at.in[5]"
= "t.in[6]" "t.at.in[6]"
= "t.in[7]" "t.at.in[7]"
= "t.in[8]" "t.at.in[8]"
= "t.in[9]" "t.at.in[9]"
= "t.in[10]" "t.at.in[10]"
= "t.in[11]" "t.at.in[11]"
= "t.in[12]" "t.at.in[12]"
= "t.in[13]" "t.at.in[13]"
= "t.in[14]" "t.at.in[14]"

41
test/unit_tests/andtree_15/test.act Normal file
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@ -0,0 +1,41 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_15 (bool? in[15]; bool! out){
andtree<15> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_15 t;

110
test/unit_tests/andtree_15/test.prsim Normal file
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@ -0,0 +1,110 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 0
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0

40
test/unit_tests/andtree_5/run/prsim.out Normal file
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@ -0,0 +1,40 @@
t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[4] : 0
0 t.in[2] : 0
0 t.in[1] : 0
0 t.in[3] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
7092 t.at.C3Els[0]._y : 1 [by t.in[4]:=0]
7094 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
10468 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
11847 t.at.C2Els[1]._y : 1 [by t.at.tmp[6]:=0]
12984 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting some bits high
12984 t.in[0] : 1
12984 t.in[2] : 1
12984 t.in[1] : 1
13098 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
78464 t.at.tmp[5] : 1 [by t.at.C2Els[0]._y:=0]
[] setting all bits high
78464 t.in[3] : 1
78464 t.in[4] : 1
80190 t.at.C3Els[0]._y : 0 [by t.in[4]:=1]
80229 t.at.tmp[6] : 1 [by t.at.C3Els[0]._y:=0]
80244 t.at.C2Els[1]._y : 0 [by t.at.tmp[6]:=1]
80735 t.out : 1 [by t.at.C2Els[1]._y:=0]
[] setting some low
80735 t.in[0] : 0
80735 t.in[1] : 0
80748 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
80788 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
81203 t.at.C2Els[1]._y : 1 [by t.at.tmp[5]:=0]
81223 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting all low
81223 t.in[2] : 0
81223 t.in[4] : 0
81223 t.in[3] : 0
87284 t.at.C3Els[0]._y : 1 [by t.in[2]:=0]
87331 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]

BIN
test/unit_tests/andtree_5/run/prsim.pdf Normal file
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Binary file not shown.

45
test/unit_tests/andtree_5/run/test.prs Normal file
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@ -0,0 +1,45 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
= "t.at.tmp[5]" "t.at.C2Els[1].a"
= "t.at.tmp[5]" "t.at.C2Els[0].y"
= "t.at.tmp[6]" "t.at.C2Els[1].b"
= "t.at.tmp[6]" "t.at.C3Els[0].y"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C3Els[0].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C3Els[0].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C3Els[0].c"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.out" "t.at.C2Els[1].y"
= "t.at.out" "t.at.tmp[7]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"

41
test/unit_tests/andtree_5/test.act Normal file
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@ -0,0 +1,41 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_5 (bool? in[5]; bool! out){
andtree<5> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_5 t;

50
test/unit_tests/andtree_5/test.prsim Normal file
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@ -0,0 +1,50 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[3] 1
set t.in[4] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 0
set t.in[1] 0
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
assert t.out 0

173
test/unit_tests/buf_s_5/run/prsim.out Normal file
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@ -0,0 +1,173 @@
b.b.vc.tmp[1] b.b.f_buf_func[3].n1 b.b.vc.C2Els[1]._y b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.vc.tmp[0] b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.tmp[2] b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.OR2_tf[2]._y b.b.en_buf_f.buf2._y b.b.vc.tmp[5] b.b.en_buf_t.buf2._y b.b._en b.b.vc.tmp[4] b.b.vc.C3Els[0]._y b.b.vc.OR2_tf[4]._y b.out.a b.b._in_v b.b.vc.tmp[6] b.b.vc.tmp[3] b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.vc.C2Els[0]._y b.b.out_a_B_buf_f.buf2._y b.b.vc.OR2_tf[3]._y
84120 b.b.f_buf_func[0].n1 : 0
84120 b.b.f_buf_func[4].y : 1
84120 b.b.t_buf_func[4].y : 1
84120 b.b.f_buf_func[1].n1 : 0
84120 b.b.f_buf_func[3].n1 : 0
84120 b.b.f_buf_func[3].y : 1
84120 b.b.t_buf_func[3].y : 1
84120 b.b.f_buf_func[0].y : 1
84120 b.b.t_buf_func[0].y : 1
84120 b.b.t_buf_func[2].n1 : 0
84120 Reset : 0
84120 b.b.f_buf_func[2].y : 1
84120 b.out.v : 0
84120 b.b.t_buf_func[0].n1 : 0
84120 b.b.f_buf_func[2].n1 : 0
84120 b.out.a : 0
84120 b.b.t_buf_func[4].n1 : 0
84120 b.b.t_buf_func[1].n1 : 0
84120 b.b.f_buf_func[4].n1 : 0
84120 b.b.t_buf_func[2].y : 1
84120 b.b.t_buf_func[3].n1 : 0
84120 b.b.f_buf_func[1].y : 1
84120 b.b.t_buf_func[1].y : 1
84121 b.b.f_buf_func[2].y : 0
84121 b.b._en : 1 [by b.out.v:=0]
84123 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
84141 b.b.vc.tmp[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
84402 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
84542 b.b.t_buf_func[0].y : 0
84671 b.b.t_buf_func[2].y : 0
84888 b.b._out_a_B : 1 [by b.out.a:=0]
85074 b.b.f_buf_func[1].y : 0
85103 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
85191 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
85201 b.b.t_buf_func[1].y : 0
88415 b.b.vc.tmp[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
88891 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
89393 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
89951 b.b.vc.tmp[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
97969 b.b.f_buf_func[3].y : 0
98463 b.b.f_buf_func[0].y : 0
104325 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
104528 b.b.vc.tmp[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
106382 b.b.vc.C2Els[0]._y : 1 [by b.b.vc.tmp[0]:=0]
106521 b.b.vc.tmp[5] : 0 [by b.b.vc.C2Els[0]._y:=1]
106561 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
106687 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
108932 b.b.t_buf_func[3].y : 0
113900 b.b.t_buf_func[4].y : 0
129789 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
129858 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
132834 b._reset_B : 1 [by Reset:=0]
132845 b.b.reset_buf._y : 0 [by b._reset_B:=1]
135773 b.b.f_buf_func[4].y : 0
138591 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
138795 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
142907 b.b.vc.tmp[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
142922 b.b.vc.C3Els[0]._y : 1 [by b.b.vc.tmp[4]:=0]
142923 b.b.vc.tmp[6] : 0 [by b.b.vc.C3Els[0]._y:=1]
142960 b.b.vc.C2Els[1]._y : 1 [by b.b.vc.tmp[6]:=0]
143699 b.b._in_v : 0 [by b.b.vc.C2Els[1]._y:=1]
143811 b.b.in_v_buf4._y : 1 [by b.b._in_v:=0]
184631 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
184671 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
184928 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
191323 b.in.v : 0 [by b.b.in_v_buf4._y:=1]
191410 b.b.in_v_bufN.buf2._y : 1 [by b.in.v:=0]
191704 b.b._in_vX[0] : 0 [by b.b.in_v_bufN.buf2._y:=1]
[] set Reset 1
191704 Reset : 1
191705 b._reset_B : 0 [by Reset:=1]
193511 b.b.reset_buf._y : 1 [by b._reset_B:=0]
195518 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
196727 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
197317 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
[] set Reset 0
197317 Reset : 0
197495 b._reset_B : 1 [by Reset:=0]
198298 b.b.reset_buf._y : 0 [by b._reset_B:=1]
198462 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
200657 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
200679 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
[] Reset finished, setting some inputs.
200679 b.b.t_buf_func[0].n1 : 1
200679 b.b.f_buf_func[3].n1 : 1
200679 b.b.f_buf_func[2].n1 : 1
200679 b.b.t_buf_func[1].n1 : 1
200812 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
201171 b.b.vc.tmp[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
201526 b.b.vc.OR2_tf[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
215642 b.b.vc.tmp[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
216341 b.b.vc.OR2_tf[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
216562 b.b.vc.tmp[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
216569 b.b.vc.C2Els[0]._y : 0 [by b.b.vc.tmp[1]:=1]
216599 b.b.vc.tmp[5] : 1 [by b.b.vc.C2Els[0]._y:=0]
230807 b.b.vc.OR2_tf[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
237520 b.b.vc.tmp[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
[] Setting final input
237520 b.b.t_buf_func[4].n1 : 1
294981 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
295072 b.b.vc.tmp[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
297261 b.b.vc.C3Els[0]._y : 0 [by b.b.vc.tmp[4]:=1]
297268 b.b.vc.tmp[6] : 1 [by b.b.vc.C3Els[0]._y:=0]
300055 b.b.vc.C2Els[1]._y : 0 [by b.b.vc.tmp[6]:=1]
300161 b.b._in_v : 1 [by b.b.vc.C2Els[1]._y:=0]
300239 b.b.in_v_buf4._y : 0 [by b.b._in_v:=1]
300514 b.in.v : 1 [by b.b.in_v_buf4._y:=0]
319510 b.b.in_v_bufN.buf2._y : 0 [by b.in.v:=1]
319965 b.b._in_vX[0] : 1 [by b.b.in_v_bufN.buf2._y:=0]
319977 b.b.t_buf_func[0]._y : 0 [by b.b._in_vX[0]:=1]
319977 b.b.t_buf_func[4]._y : 0 [by b.b._in_vX[0]:=1]
320369 b.b.t_buf_func[1]._y : 0 [by b.b._in_vX[0]:=1]
320371 b.b.t_buf_func[1].y : 1 [by b.b.t_buf_func[1]._y:=0]
322876 b.b.t_buf_func[0].y : 1 [by b.b.t_buf_func[0]._y:=0]
324241 b.b.f_buf_func[3]._y : 0 [by b.b._in_vX[0]:=1]
324272 b.b.t_buf_func[4].y : 1 [by b.b.t_buf_func[4]._y:=0]
325881 b.b.f_buf_func[2]._y : 0 [by b.b._in_vX[0]:=1]
327130 b.b.f_buf_func[2].y : 1 [by b.b.f_buf_func[2]._y:=0]
328776 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
[] Receiving out val
328776 b.out.v : 1
332275 b.b.inack_ctl._y : 0 [by b.out.v:=1]
332441 b.in.a : 1 [by b.b.inack_ctl._y:=0]
332516 b.b._en : 0 [by b.in.a:=1]
332654 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
332861 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
332863 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
337917 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
[] Removing input
337917 b.b.t_buf_func[0].n1 : 0
337917 b.b.t_buf_func[4].n1 : 0
337917 b.b.f_buf_func[2].n1 : 0
337917 b.b.t_buf_func[1].n1 : 0
337917 b.b.f_buf_func[3].n1 : 0
337918 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
337928 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
337985 b.b.vc.tmp[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
338287 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
338303 b.b.vc.tmp[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
338465 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
340569 b.b.vc.tmp[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
343027 b.b.vc.tmp[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
343555 b.b.vc.C3Els[0]._y : 1 [by b.b.vc.tmp[2]:=0]
345990 b.b.vc.tmp[6] : 0 [by b.b.vc.C3Els[0]._y:=1]
381834 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
408714 b.b.vc.tmp[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
432639 b.b.vc.C2Els[0]._y : 1 [by b.b.vc.tmp[0]:=0]
445680 b.b.vc.tmp[5] : 0 [by b.b.vc.C2Els[0]._y:=1]
445682 b.b.vc.C2Els[1]._y : 1 [by b.b.vc.tmp[5]:=0]
506640 b.b._in_v : 0 [by b.b.vc.C2Els[1]._y:=1]
506643 b.b.in_v_buf4._y : 1 [by b.b._in_v:=0]
506672 b.in.v : 0 [by b.b.in_v_buf4._y:=1]
506989 b.b.in_v_bufN.buf2._y : 1 [by b.in.v:=0]
508590 b.b._in_vX[0] : 0 [by b.b.in_v_bufN.buf2._y:=1]
[] Receiving out ack
508590 b.out.a : 1
508743 b.b._out_a_B : 0 [by b.out.a:=1]
508787 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
511504 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
511505 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
511506 b.b.t_buf_func[4]._y : 1 [by b.b._out_a_BX_t[0]:=0]
511527 b.b.t_buf_func[1]._y : 1 [by b.b._out_a_BX_t[0]:=0]
511722 b.b.t_buf_func[0]._y : 1 [by b.b._out_a_BX_t[0]:=0]
511881 b.b.t_buf_func[0].y : 0 [by b.b.t_buf_func[0]._y:=1]
513087 b.b.t_buf_func[4].y : 0 [by b.b.t_buf_func[4]._y:=1]
520872 b.b.t_buf_func[1].y : 0 [by b.b.t_buf_func[1]._y:=1]
522470 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
523757 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
525989 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
542146 b.b.f_buf_func[2]._y : 1 [by b.b._out_a_BX_f[0]:=0]
542291 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]

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test/unit_tests/buf_s_5/run/prsim.pdf Normal file
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test/unit_tests/buf_s_5/run/test.prs Normal file
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= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
"b.b.in_v_buf4.a"->"b.b.in_v_buf4._y"-
~("b.b.in_v_buf4.a")->"b.b.in_v_buf4._y"+
"b.b.in_v_buf4._y"->"b.b.in_v_buf4.y"-
~("b.b.in_v_buf4._y")->"b.b.in_v_buf4.y"+
"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.in_v_bufN.supply.vss"
= "b.b.supply.vdd" "b.b.in_v_bufN.supply.vdd"
= "b.b.supply.vss" "b.b.vc.supply.vss"
= "b.b.supply.vdd" "b.b.vc.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.in_v_buf4.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vdd" "b.b.en_ctl.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.in_v_buf4.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
= "b.b.supply.vss" "b.b.en_ctl.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
~"b.b.vc.C2Els[0].c1"&~"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"+
"b.b.vc.C2Els[0].c1"&"b.b.vc.C2Els[0].c2"->"b.b.vc.C2Els[0]._y"-
"b.b.vc.C2Els[0]._y"->"b.b.vc.C2Els[0].y"-
~("b.b.vc.C2Els[0]._y")->"b.b.vc.C2Els[0].y"+
~"b.b.vc.C2Els[1].c1"&~"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"+
"b.b.vc.C2Els[1].c1"&"b.b.vc.C2Els[1].c2"->"b.b.vc.C2Els[1]._y"-
"b.b.vc.C2Els[1]._y"->"b.b.vc.C2Els[1].y"-
~("b.b.vc.C2Els[1]._y")->"b.b.vc.C2Els[1].y"+
~"b.b.vc.C3Els[0].c1"&~"b.b.vc.C3Els[0].c2"&~"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"+
"b.b.vc.C3Els[0].c1"&"b.b.vc.C3Els[0].c2"&"b.b.vc.C3Els[0].c3"->"b.b.vc.C3Els[0]._y"-
"b.b.vc.C3Els[0]._y"->"b.b.vc.C3Els[0].y"-
~("b.b.vc.C3Els[0]._y")->"b.b.vc.C3Els[0].y"+
"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
= "b.b.vc.tmp[0]" "b.b.vc.C2Els[0].c1"
= "b.b.vc.tmp[0]" "b.b.vc.OR2_tf[0].y"
= "b.b.vc.tmp[1]" "b.b.vc.C2Els[0].c2"
= "b.b.vc.tmp[1]" "b.b.vc.OR2_tf[1].y"
= "b.b.vc.tmp[2]" "b.b.vc.C3Els[0].c1"
= "b.b.vc.tmp[2]" "b.b.vc.OR2_tf[2].y"
= "b.b.vc.tmp[3]" "b.b.vc.C3Els[0].c2"
= "b.b.vc.tmp[3]" "b.b.vc.OR2_tf[3].y"
= "b.b.vc.tmp[4]" "b.b.vc.C3Els[0].c3"
= "b.b.vc.tmp[4]" "b.b.vc.OR2_tf[4].y"
= "b.b.vc.tmp[5]" "b.b.vc.C2Els[1].c1"
= "b.b.vc.tmp[5]" "b.b.vc.C2Els[0].y"
= "b.b.vc.tmp[6]" "b.b.vc.C2Els[1].c2"
= "b.b.vc.tmp[6]" "b.b.vc.C3Els[0].y"
= "b.b.vc.supply.vdd" "b.b.vc.C3Els[0].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.C2Els[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.C2Els[0].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
= "b.b.vc.supply.vss" "b.b.vc.C3Els[0].vss"
= "b.b.vc.supply.vss" "b.b.vc.C2Els[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.C2Els[0].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.out" "b.b.vc.C2Els[1].y"
= "b.b.vc.out" "b.b.vc.tmp[7]"
"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.en_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.a" "b.b.out_a_inv.a"
= "b.b.out.v" "b.b.en_ctl.p1"
= "b.b.out.v" "b.b.inack_ctl.c3"
= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
= "b.b.in.a" "b.b.en_ctl.c1"
= "b.b.in.a" "b.b.inack_ctl.y"
= "b.b.in.v" "b.b.in_v_bufN.in"
= "b.b.in.v" "b.b.in_v_buf4.y"
= "b.b.in.v" "b.b.inack_ctl.c2"
= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
= "b.b._in_v" "b.b.in_v_buf4.a"
= "b.b._in_v" "b.b.vc.out"
= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b.reset_B" "b.b.reset_buf.a"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
= "b.b._out_a_B" "b.b.out_a_inv.y"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
= "b.b._in_vX[0]" "b.b.in_v_bufN.out[0]"
= "b.b._in_vX[1]" "b.b.in_v_bufN.out[1]"
= "b.b._in_vX[2]" "b.b.in_v_bufN.out[2]"
= "b.b._in_vX[3]" "b.b.in_v_bufN.out[3]"
= "b.b._in_vX[4]" "b.b.in_v_bufN.out[4]"
= "b.b._in_vX[0]" "b.b.t_buf_func[4].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[4].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[3].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[3].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[2].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[2].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[1].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[1].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[0].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[0].n2"
= "b.b._in_vX[0]" "b.b._in_vX[4]"
= "b.b._in_vX[0]" "b.b._in_vX[3]"
= "b.b._in_vX[0]" "b.b._in_vX[2]"
= "b.b._in_vX[0]" "b.b._in_vX[1]"
"b.b.in_v_bufN.buf2.a"->"b.b.in_v_bufN.buf2._y"-
~("b.b.in_v_bufN.buf2.a")->"b.b.in_v_bufN.buf2._y"+
"b.b.in_v_bufN.buf2._y"->"b.b.in_v_bufN.buf2.y"-
~("b.b.in_v_bufN.buf2._y")->"b.b.in_v_bufN.buf2.y"+
= "b.b.in_v_bufN.supply.vdd" "b.b.in_v_bufN.buf2.vdd"
= "b.b.in_v_bufN.supply.vss" "b.b.in_v_bufN.buf2.vss"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[4]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[3]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[2]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[1]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.buf2.y"
= "b.b.in_v_bufN.in" "b.b.in_v_bufN.buf2.a"
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
= "Vdd" "b.b.supply.vdd"
= "GND" "b.b.supply.vss"
= "b._reset_B" "b.b.reset_B"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.v" "b.b.out.v"
= "b.out.a" "b.b.out.a"
= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.v" "b.b.in.v"
= "b.in.a" "b.b.in.a"
= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

47
test/unit_tests/buf_s_5/test.act Normal file
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@ -0,0 +1,47 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_s_5(avMx1of2<5> in; avMx1of2<5> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
buffer_s<5> b(.in = in, .out = out);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
buffer_s_5 b;

66
test/unit_tests/buf_s_5/test.prsim Normal file
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watchall
set-qdi-channel-neutral "b.in" 5
set b.out.a 0
set b.out.v 0
# set b.in.a 1
# set b.in.v 1
set Reset 0
# Set output channel variables to all active (incorrect)
set b.out.d.d[0].t 1
set b.out.d.d[0].f 1
set b.out.d.d[1].t 1
set b.out.d.d[1].f 1
set b.out.d.d[2].t 1
set b.out.d.d[2].f 1
set b.out.d.d[3].t 1
set b.out.d.d[3].f 1
set b.out.d.d[4].t 1
set b.out.d.d[4].f 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
assert-qdi-channel-neutral "b.out" 5
system "echo '[] Reset finished, setting some inputs.'"
status X
set b.in.d.d[0].t 1
set b.in.d.d[1].t 1
set b.in.d.d[2].f 1
set b.in.d.d[3].f 1
cycle
system "echo '[] Setting final input'"
set b.in.d.d[4].t 1
cycle
system "echo '[] Receiving out val'"
set b.out.v 1
cycle
assert b.in.a 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] Receiving out ack'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5