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removed old decoder, only simple now, fixed 8x8 test, deleted other 2

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alexmadison
2023-11-21 11:26:04 +01:00
parent db39324593
commit 0a91459073
7 changed files with 137 additions and 990 deletions
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dataflow_neuro/coders.act
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@ -754,136 +754,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
}
export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH>
defproc encoder2d(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B) {
// Reset buffers
pint H = 2*(NxC + NyC); //Reset strength? to be investigated
bool _reset_BX,_reset_BXX[H];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
// Arbiters
a1of1 _arb_out_x, _arb_out_y;
a1of1 _x_temp[Nx],_y_temp[Ny]; // For wiring the reqs to the arbtrees
(i:Nx:
_x_temp[i].r = inx[i].r;
)
(i:Ny:
_y_temp[i].r = iny[i].r;
)
arbtree<Nx> Xarb(.in = _x_temp,.out = _arb_out_x,.supply = supply);
arbtree<Ny> Yarb(.in = _y_temp,.out = _arb_out_y,.supply = supply);
// Sigbufs for strong ackowledge signals from arb_in's
sigbuf_1output<ACK_STRENGTH> x_ack_arb[Nx];
sigbuf_1output<ACK_STRENGTH> y_ack_arb[Ny];
(i:Nx:
x_ack_arb[i].in = _x_temp[i].a;
x_ack_arb[i].out = inx[i].a;
x_ack_arb[i].supply = supply;
)
(i:Ny:
y_ack_arb[i].in = _y_temp[i].a;
y_ack_arb[i].out = iny[i].a;
y_ack_arb[i].supply = supply;
)
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
bool _x_v,_in_x_v,_in_y_v,_x_a_B,_x_a;
A_2C2P_RB_X1 Y_ack_confirm();
Y_ack_confirm.p1 = _x_v;
Y_ack_confirm.p2 =_in_x_v;
Y_ack_confirm.c1 = _arb_out_y.r;
Y_ack_confirm.c2 = _x_a_B;
Y_ack_confirm.y = _arb_out_y.a;
Y_ack_confirm.vdd = supply.vdd;
Y_ack_confirm.vss = supply.vss;
Y_ack_confirm.reset_B = _reset_BX;
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
A_2C_RB_X1 X_ack_confirm();
X_ack_confirm.c1 = _arb_out_x.r;
X_ack_confirm.c2 = _x_a_B;
X_ack_confirm.vdd = supply.vdd;
X_ack_confirm.vss = supply.vss;
X_ack_confirm.pr_B = _reset_BX;
X_ack_confirm.sr_B = _reset_BX;
X_ack_confirm.y = _arb_out_x.a;
// X_req ORtree
bool _x_req_array[Nx], _x_v_B;
(i:Nx:_x_req_array[i] = inx[i].r;)
ortree<Nx> x_req_ortree(.in = _x_req_array, .supply = supply); //todo BUFF
INV_X1 not_x_req_ortree(.a = x_req_ortree.out, .y = _x_v_B);
INV_X1 not_x_req_ortree2(.a = _x_v_B,.y = _x_v);
//X_REQ validation
// bool _x_req_array[Nx],_x_v_B, _en;
// (i:Nx:_x_req_array[i] = x[i].r;)
// ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply);
// INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
bool _x_a_B2; // sorry
bool _en;
A_1C3P2P2N_R_X1 x_ack();
//branch1
x_ack.p4 = _in_x_v;
x_ack.p5 = _x_v_B;
//branch2
x_ack.p1 = _in_x_v;
x_ack.p2 = _in_y_v;
x_ack.p3 = _x_v;
//
x_ack.c1 = _en;
x_ack.n1 = out.v;
x_ack.n2 = _in_x_v;
//
x_ack.y = _x_a_B2;
//
x_ack.vdd = supply.vdd;
x_ack.vss = supply.vss;
x_ack.pr_B = _reset_BX;
x_ack.sr_B = _reset_BX;
INV_X1 not_x_ack(.a = _x_a_B2, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
INV_X1 not_x_ack2(.a = _x_a, .y = _x_a_B, .vdd = supply.vdd, .vss = supply.vss);
A_1C2P_X1 enabling(.p1 = out.a, .p2 = out.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss);
avMx1of2<(NxC + NyC)> _in_x;
// Encoders
bool x_acks[Nx];
Mx1of2<NxC> x_enc_out;
(i:Nx:x_acks[i] = inx[i].a;)
dualrail_encoder<NxC, Nx> x_encoder(.in = x_acks, .out = x_enc_out, .supply = supply);
bool y_acks[Ny];
Mx1of2<NyC> y_enc_out;
(i:Ny:y_acks[i] = iny[i].a;)
dualrail_encoder<NyC, Ny> y_encoder(.in = y_acks, .out = y_enc_out, .supply = supply);
// Valid trees
vtree<NxC> vtree_x(.in = x_enc_out, .out = _in_x_v, .supply = supply);
vtree<NyC> vtree_y(.in = y_enc_out, .out = _in_y_v, .supply = supply);
// Buffer func thing
Mx1of2<NxC + NyC> into_buffer;
(i:0..NxC-1:into_buffer.d[i] = x_enc_out.d[i];)
(i:0..NyC-1:into_buffer.d[i+NxC] = y_enc_out.d[i];)
AND2_X1 _in_xy_v(.a = _in_x_v, .b = _in_y_v, .vss = supply.vss, .vdd = supply.vdd);
buffer_s_func<NxC + NyC> buf_s_func(.in = into_buffer, .out = out,
.en = _en, .in_v = _in_xy_v.y, .supply = supply, .reset_B = reset_B);
}
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
@ -1133,6 +1003,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
// WARNUNG WARNUNG WARNUNG //
// @TODO
// This neuron hs design has a fat timing assumption.
// Say that the neuron has sent out both reqs, and is now receiving the acks.
// _x_a_B and _y_a_B are then low, and _req starts to be pulled down to reset the hs.