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regenned without pulldown delays

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This commit is contained in:
alexmadison 2022-06-20 16:10:35 +02:00
parent 8953fdafe6
commit 17d9d3da41
125 changed files with 277028 additions and 246222 deletions
test/unit_tests/texel_dualcore_glue
netlist.vnetlist_clean.v
split_modules
texel__dualcore__glue/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_37_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_39_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__2d__synapse__hs_315_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_39_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0delayprog_32_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit_330_730_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit_331_731_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit__msb_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit__msb_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dummy__neuron__core_358_790_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_313_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_329_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_330_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_331_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_332_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_37_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fork_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0merge_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0merge_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0nrn__hs__2d/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_315_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_358_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_364_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_38_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0register__wr__array_36_723_764_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_313_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_323_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_324_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_346_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_347_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_365_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_370_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_74_4/netlist
verilog.v
Show More

175403
test/unit_tests/texel_dualcore_glue/netlist.v

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175225
test/unit_tests/texel_dualcore_glue/netlist_clean.v

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58578
test/unit_tests/texel_dualcore_glue/split_modules/texel__dualcore__glue/netlist/verilog.v

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11848
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

12
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/verilog.v

@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0andtree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out,
output out;
// -- signals ---
wire Iin1 ;
wire Iin2 ;
wire Itmp4 ;
wire Iin0 ;
wire Iin3 ;
wire out ;
wire Itmp5 ;
wire Iin2 ;
wire Iin1 ;
wire Iin3 ;
wire Iin0 ;
wire Itmp4 ;
wire out ;
// --- instances
AND2_X1 Iand2s0 (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

10
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/verilog.v

@ -9,14 +9,14 @@ module tmpl_0_0dataflow__neuro_0_0andtree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Itmp5 ;
wire Itmp6 ;
wire Iin1 ;
wire Iin2 ;
wire Iin3 ;
wire Itmp6 ;
wire Iin0 ;
wire out ;
wire Iin3 ;
wire Iin2 ;
wire Iin4 ;
wire Itmp5 ;
wire out ;
// --- instances
AND3_X1 Iand3s0 (.y(Itmp6 ), .a(Iin2 ), .b(Iin3 ), .c(Iin4 ), .vdd(vdd), .vss(vss));

12
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/verilog.v

@ -10,16 +10,16 @@ module tmpl_0_0dataflow__neuro_0_0andtree_36_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin0 ;
wire out ;
wire Iin4 ;
wire Iin1 ;
wire Iin2 ;
wire out ;
wire Iin3 ;
wire Iin0 ;
wire Itmp8 ;
wire Itmp7 ;
wire Itmp6 ;
wire Iin2 ;
wire Iin1 ;
wire Iin5 ;
wire Itmp8 ;
wire Iin3 ;
// --- instances
AND3_X1 Iand3s0 (.y(out), .a(Itmp6 ), .b(Itmp7 ), .c(Itmp8 ), .vdd(vdd), .vss(vss));

28
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/verilog.v

@ -13,22 +13,22 @@ module tmpl_0_0dataflow__neuro_0_0andtree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin8 ;
wire Iin6 ;
wire Iin3 ;
wire Itmp9 ;
wire Itmp11 ;
wire Itmp14 ;
wire Iin2 ;
wire out ;
wire Iin0 ;
wire Itmp10 ;
wire Iin4 ;
wire Iin5 ;
wire Itmp12 ;
wire Itmp13 ;
wire Iin7 ;
wire Iin1 ;
wire Iin5 ;
wire Itmp14 ;
wire Iin0 ;
wire out ;
wire Iin2 ;
wire Iin4 ;
wire Itmp9 ;
wire Itmp12 ;
wire Itmp11 ;
wire Itmp13 ;
wire Iin8 ;
wire Iin3 ;
wire Iin7 ;
wire Itmp10 ;
// --- instances
AND3_X1 Iand3s0 (.y(Itmp12 ), .a(Iin6 ), .b(Iin7 ), .c(Iin8 ), .vdd(vdd), .vss(vss));

106
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/verilog.v

@ -62,66 +62,66 @@ module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d28_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d1_d0 ;
wire Isb_in ;
wire Iin_d_d28_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d5_d0 ;
wire Isb_in ;
wire Iin_d_d23_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d0_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

120
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/verilog.v

@ -66,70 +66,70 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d12_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d4_d0 ;
wire Isb_in ;
wire Iin_d_d28_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d31_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d_d31_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d27_d1 ;
wire Isb_in ;
wire Iin_d_d27_d0 ;
wire Iin_d_d3_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

112
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v

@ -66,70 +66,70 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d27_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d15_d0 ;
output Iout_d_d31_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d13_d1 ;
wire Isb_in ;
wire Iin_d_d26_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d4_d0 ;
wire Isb_in ;
wire Iin_d_d18_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d31_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d6_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

24
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v

@ -18,22 +18,22 @@ module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d6_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d1_d0 ;
wire Isb_in ;
wire Iin_d_d2_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d5_d0 ;
output Iout_d_d7_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d0_d0 ;
wire Isb_in ;
wire Iin_d_d6_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

6
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v

@ -9,14 +9,14 @@ module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d
input Iout_a ;
// -- signals ---
wire _y2_arb ;
output Iout_d_d0 ;
wire _y2_arb ;
wire Iin1_d_d0 ;
wire Iout_a ;
output Iin1_a ;
wire Iin2_d_d0 ;
wire _y1_arb ;
output Iin2_a ;
wire Iin1_d_d0 ;
wire Iin2_d_d0 ;
// --- instances
A_2C_B_X1 Iack_cell1 (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));

96
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/verilog.v

@ -35,64 +35,64 @@ module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 ,
input Iout_a ;
// -- signals ---
wire Itmp20_d_d0 ;
wire Iin7_d_d0 ;
wire Itmp28_d_d0 ;
wire Itmp15_d_d0 ;
output Iout_d_d0 ;
wire Itmp19_a ;
wire Iin8_d_d0 ;
wire Iin1_d_d0 ;
wire Itmp27_a ;
output Iin11_a ;
output Iin7_a ;
wire Itmp27_d_d0 ;
wire Iin14_d_d0 ;
wire Itmp18_a ;
wire Itmp15_d_d0 ;
output Iin1_a ;
wire Itmp23_d_d0 ;
output Iin6_a ;
wire Itmp21_a ;
wire Iin2_d_d0 ;
output Iin4_a ;
wire Itmp16_d_d0 ;
wire Iin4_d_d0 ;
wire Itmp16_a ;
wire Itmp24_a ;
wire Itmp23_a ;
wire Itmp21_d_d0 ;
output Iin14_a ;
wire Iin11_d_d0 ;
wire Itmp18_d_d0 ;
wire Iin0_d_d0 ;
wire Itmp25_a ;
wire Itmp19_d_d0 ;
output Iin12_a ;
wire Itmp17_d_d0 ;
output Iin5_a ;
wire Iin3_d_d0 ;
wire Itmp26_a ;
wire Itmp24_d_d0 ;
wire Iin9_d_d0 ;
wire Itmp15_a ;
wire Itmp28_a ;
wire Iin12_d_d0 ;
output Iin9_a ;
output Iin13_a ;
wire Itmp25_d_d0 ;
wire Itmp20_d_d0 ;
wire Itmp20_a ;
wire Iin8_d_d0 ;
wire Iin10_d_d0 ;
wire Iin5_d_d0 ;
wire Iin1_d_d0 ;
wire Itmp26_d_d0 ;
output Iin0_a ;
wire Iout_a ;
wire Iin14_d_d0 ;
wire Iin10_d_d0 ;
wire Iin3_d_d0 ;
wire Iin5_d_d0 ;
wire Itmp18_d_d0 ;
wire Itmp28_a ;
wire Itmp27_a ;
wire Itmp26_a ;
output Iin5_a ;
wire Itmp17_a ;
wire Iin7_d_d0 ;
output Iin10_a ;
output Iin8_a ;
output Iin14_a ;
output Iin11_a ;
wire Iin2_d_d0 ;
wire Itmp21_d_d0 ;
wire Itmp19_d_d0 ;
output Iin1_a ;
wire Itmp27_d_d0 ;
wire Iin6_d_d0 ;
output Iin4_a ;
wire Itmp24_a ;
output Iin3_a ;
output Iin2_a ;
wire Itmp21_a ;
output Iin13_a ;
wire Itmp16_d_d0 ;
wire Itmp25_a ;
output Iin9_a ;
wire Iin4_d_d0 ;
output Iin10_a ;
output Iin6_a ;
output Iin12_a ;
wire Iin11_d_d0 ;
wire Itmp28_d_d0 ;
wire Iin13_d_d0 ;
wire Itmp15_a ;
wire Iin12_d_d0 ;
wire Itmp16_a ;
wire Itmp17_a ;
wire Itmp20_a ;
output Iin7_a ;
wire Itmp18_a ;
wire Itmp24_d_d0 ;
wire Itmp23_a ;
wire Iin0_d_d0 ;
wire Iin9_d_d0 ;
wire Itmp26_d_d0 ;
wire Itmp25_d_d0 ;
wire Itmp17_d_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));

32
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/verilog.v

@ -17,28 +17,28 @@ module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 ,
input Iout_a ;
// -- signals ---
output Iin3_a ;
output Iin1_a ;
output Iin5_a ;
wire Iout_a ;
wire Itmp10_a ;
output Iout_d_d0 ;
wire Itmp6_a ;
wire Iin0_d_d0 ;
output Iin2_a ;
wire Itmp9_a ;
wire Itmp7_d_d0 ;
wire Iin1_d_d0 ;
wire Iin3_d_d0 ;
output Iin0_a ;
wire Itmp10_d_d0 ;
wire Iin2_d_d0 ;
wire Itmp7_a ;
wire Itmp9_d_d0 ;
output Iin4_a ;
wire Iout_a ;
output Iout_d_d0 ;
wire Iin2_d_d0 ;
wire Iin0_d_d0 ;
wire Iin4_d_d0 ;
output Iin0_a ;
output Iin4_a ;
wire Itmp6_a ;
wire Itmp7_d_d0 ;
output Iin3_a ;
wire Iin5_d_d0 ;
wire Itmp6_d_d0 ;
output Iin1_a ;
wire Itmp9_a ;
wire Iin1_d_d0 ;
wire Iin3_d_d0 ;
output Iin2_a ;
wire Itmp10_a ;
output Iin5_a ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp6_d_d0 ), .Iout_a (Itmp6_a ), .vdd(vdd), .vss(vss));

282
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/verilog.v

@ -110,156 +110,156 @@ module tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4(Iin_d0 , Iin_d1 , Iin_d2 ,
input reset_B;
// -- signals ---
wire Idly_cfg21 ;
wire I_inB5 ;
wire Iin_d26 ;
output Iout_d_d3_d0 ;
wire _reset_BX ;
wire I_inB27 ;
output Iout_d_d18_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d5_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d4_d1 ;
wire Iin_d7 ;
wire Iin_d9 ;
wire Iin_d28 ;
output Iout_d_d28_d1 ;
wire Iin_d18 ;
output Iout_d_d24_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d22_d1 ;
wire Iout_a ;
wire I_inB1 ;
wire Iin_d22 ;
wire Iin_d24 ;
output Iout_d_d14_d0 ;
wire I_inB6 ;
wire Iin_d15 ;
wire Iin_d29 ;
wire I_inB14 ;
wire Iin_d2 ;
wire I_inB24 ;
wire Iin_d13 ;
output Iout_d_d10_d0 ;
output Iout_d_d17_d1 ;
wire Iin_d8 ;
output Iout_d_d7_d1 ;
wire I_inB2 ;
wire Iin_d4 ;
wire Iin_d17 ;
output Iout_d_d4_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d28_d0 ;
wire Iin_d18 ;
output Iout_d_d6_d1 ;
output Iout_d_d23_d1 ;
wire I_inB29 ;
output Iout_d_d27_d0 ;
wire _en ;
wire If_buf_func31_c2 ;
output Iout_d_d20_d0 ;
output Iout_d_d13_d1 ;
wire Iout_v ;
wire Iin_d12 ;
wire I_inB13 ;
output Iout_d_d22_d1 ;
wire I_inB21 ;
wire I_inB30 ;
output Iout_d_d1_d0 ;
wire _req_slowfall ;
wire Iin_d16 ;
wire I_inB26 ;
output Iout_d_d15_d1 ;
wire I_inB16 ;
wire reset_B;
output Iout_d_d27_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d6 ;
output Iout_d_d13_d0 ;
output Iout_d_d26_d0 ;
wire I_inB0 ;
output Iout_d_d19_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d7 ;
wire Iin_d17 ;
output Iout_d_d30_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d19_d1 ;
output Iin_a ;
wire I_inB3 ;
wire I_inB4 ;
wire Iin_d6 ;
wire Iin_d27 ;
wire I_reqXX0 ;
output Iout_d_d0_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d25 ;
wire Iin_d26 ;
output Iout_d_d0_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d20_d1 ;
wire I_inB24 ;
wire Iin_d24 ;
output Iout_d_d30_d1 ;
wire I_inB29 ;
output Iout_d_d31_d0 ;
wire I_inB14 ;
wire I_inB28 ;
wire Iin_d30 ;
output Iout_d_d9_d1 ;
wire I_inB8 ;
wire Iin_d19 ;
output Iout_d_d10_d0 ;
wire I_inB7 ;
wire Iout_a ;
wire I_inB18 ;
wire Iin_d20 ;
output Iout_d_d2_d1 ;
wire I_inB9 ;
wire Iin_d21 ;
output Iout_d_d31_d1 ;
wire Idly_cfg0 ;
wire Idly_cfg1 ;
output Iout_d_d8_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d23_d1 ;
wire I_inB25 ;
output Iout_d_d28_d1 ;
wire Idly_cfg3 ;
output Iout_d_d14_d1 ;
wire Iin_d1 ;
output Iout_d_d31_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d30_d0 ;
wire I_inB7 ;
output Iout_d_d19_d1 ;
wire _req ;
wire _out_a_B ;
output Iout_d_d21_d1 ;
wire Idly_cfg1 ;
wire I_inB23 ;
wire Iin_d23 ;
wire I_inB25 ;
output Iout_d_d7_d1 ;
wire I_inB15 ;
wire Iin_d25 ;
wire Idly_cfg0 ;
output Iout_d_d8_d1 ;
wire Idly2_out ;
output Iout_d_d20_d1 ;
wire I_inB8 ;
wire I_reset_BXX0 ;
wire Idly_cfg3 ;
wire Iin_d5 ;
wire Iin_d19 ;
output Iout_d_d8_d0 ;
wire Iin_d8 ;
wire I_inB28 ;
output Iout_d_d12_d0 ;
wire Idly_cfg2 ;
wire Iin_d0 ;
wire I_inB4 ;
wire Iin_d20 ;
wire _reqX ;
wire Iin_d14 ;
output Iout_d_d0_d0 ;
output Iout_d_d9_d0 ;
output Iout_d_d19_d0 ;
wire I_reqXX0 ;
output Iout_d_d16_d0 ;
output Iout_d_d17_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d3 ;
wire Iin_d31 ;
output Iout_d_d15_d0 ;
output Iout_d_d31_d0 ;
wire Idly_cfg20 ;
wire I_inB18 ;
wire I_inB20 ;
output Iout_d_d3_d1 ;
wire I_inB17 ;
wire I_inB2 ;
wire Iin_d21 ;
output Iout_d_d11_d0 ;
wire I_inB19 ;
output Iout_d_d6_d0 ;
wire Iin_d27 ;
output Iout_d_d26_d1 ;
output Iout_d_d25_d1 ;
wire Iin_r ;
output Iout_d_d9_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d12_d1 ;
wire I_inB31 ;
wire Iin_d10 ;
output Iout_d_d11_d1 ;
output Iout_d_d21_d0 ;
wire I_inB0 ;
output Iout_d_d23_d0 ;
output Iout_d_d24_d1 ;
wire I_inB12 ;
output Iin_a ;
wire I_inB9 ;
wire I_inB11 ;
wire Iin_d11 ;
wire Iin_d30 ;
wire I_inB10 ;
wire I_inB3 ;
wire I_inB22 ;
output Iout_d_d29_d1 ;
wire I_reset_BXX0 ;
wire I_inB1 ;
output Iout_d_d13_d0 ;
output Iout_d_d24_d1 ;
output Iout_d_d13_d1 ;
wire Iout_v ;
wire I_inB5 ;
wire I_inB23 ;
wire _en ;
wire Iin_r ;
output Iout_d_d9_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d18_d1 ;
wire I_inB11 ;
output Iout_d_d22_d0 ;
wire I_inB17 ;
output Iout_d_d17_d0 ;
wire Iin_d3 ;
wire I_inB27 ;
output Iout_d_d5_d1 ;
wire _out_a_B ;
output Iout_d_d6_d0 ;
output Iout_d_d12_d1 ;
wire Ien_buf_out0 ;
wire Idly_cfg2 ;
wire Idly_cfg21 ;
output Iout_d_d21_d0 ;
wire Iin_d23 ;
output Iout_d_d17_d1 ;
output Iout_d_d11_d1 ;
wire _reqX ;
wire Iin_d15 ;
output Iout_d_d25_d0 ;
wire Iin_d0 ;
wire Iin_d13 ;
output Iout_d_d29_d0 ;
wire Idly2_out ;
wire Iin_d9 ;
wire I_inB30 ;
wire I_inB10 ;
wire Iin_d12 ;
output Iout_d_d26_d0 ;
wire reset_B;
wire Iin_d31 ;
wire _reset_BX ;
wire _req ;
wire Idly_cfg20 ;
wire I_inB16 ;
wire Iin_d29 ;
output Iout_d_d16_d0 ;
wire Iin_d2 ;
output Iout_d_d23_d0 ;
wire Iin_d5 ;
wire I_inB15 ;
output Iout_d_d14_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d16_d1 ;
wire I_inB31 ;
wire Iin_d16 ;
output Iout_d_d5_d0 ;
output Iout_d_d28_d0 ;
wire I_inB12 ;
wire Iin_d14 ;
output Iout_d_d3_d0 ;
output Iout_d_d15_d0 ;
wire I_inB13 ;
wire I_inB26 ;
wire Iin_d28 ;
output Iout_d_d25_d1 ;
wire Iin_d11 ;
output Iout_d_d1_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d12_d0 ;
wire Iin_d10 ;
wire If_buf_func31_c2 ;
wire _req_slowfall ;
wire I_inB20 ;
wire Iin_d22 ;
output Iout_d_d7_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

116
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/verilog.v

@ -60,70 +60,70 @@ module tmpl_0_0dataflow__neuro_0_0buffer_313_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
wire Iout_a ;
output Iout_d_d2_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d7_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d3_d1 ;
output Iout_d_d7_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d_d12_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d4_d1 ;
wire Ien_buf_out0 ;
wire Iin_d_d1_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d0_d1 ;
output Iin_a ;
output Iout_d_d0_d0 ;
wire Iout_v ;
wire Iin_d_d6_d1 ;
wire _in_v ;
output Iout_d_d9_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d0_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d11_d0 ;
wire _reset_BX ;
wire _out_a_B ;
wire Iin_d_d11_d0 ;
wire I_reset_BXX0 ;
output Iout_d_d1_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d10_d1 ;
output Iin_v ;
output Iout_d_d4_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d6_d0 ;
wire I_out_a_BX0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d12_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d8_d0 ;
wire Iin_d_d1_d1 ;
wire Iout_v ;
output Iin_a ;
output Iout_d_d8_d1 ;
output Iout_d_d4_d1 ;
wire Iout_a ;
wire _en ;
wire Iin_d_d12_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d1_d1 ;
wire Iin_d_d5_d1 ;
wire _reset_BX ;
wire I_out_a_BX0 ;
output Iout_d_d5_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d9_d0 ;
wire _in_v ;
output Iout_d_d4_d0 ;
output Iout_d_d9_d0 ;
wire Iin_d_d1_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d11_d1 ;
wire _out_a_B ;
output Iout_d_d10_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d11_d1 ;
wire Iin_d_d7_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d_d9_d1 ;
wire I_reset_BXX0 ;
wire Ien_buf_out0 ;
output Iout_d_d0_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d6_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d2_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d7_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d6_d1 ;
wire reset_B;
wire Iin_d_d10_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d7_d1 ;
wire _en ;
output Iout_d_d4_d1 ;
wire reset_B;
wire Iin_d_d9_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d4_d0 ;
output Iin_v ;
output Iout_d_d6_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d0_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

250
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/verilog.v

@ -124,134 +124,134 @@ module tmpl_0_0dataflow__neuro_0_0buffer_329_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d4_d1 ;
output Iout_d_d15_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d18_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d8_d1 ;
output Iout_d_d17_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d11_d0 ;
wire Iout_v ;
output Iout_d_d21_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d17_d0 ;
output Iout_d_d19_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d4_d0 ;
wire _in_v ;
output Iout_d_d7_d0 ;
output Iout_d_d23_d1 ;
wire Iin_d_d0_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d6_d1 ;
wire Iin_d_d12_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d4_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d14_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d24_d0 ;
wire _reset_BX ;
wire _out_a_B ;
output Iout_d_d21_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d28_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d9_d0 ;
output Iout_d_d2_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d28_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d5_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d11_d1 ;
wire Ien_buf_out0 ;
wire Iin_d_d8_d0 ;
output Iin_a ;
output Iout_d_d6_d0 ;
output Iout_d_d14_d1 ;
wire reset_B;
wire Iin_d_d18_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d2_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d16_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d7_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d26_d0 ;
output Iout_d_d24_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d15_d1 ;
output Iin_v ;
output Iout_d_d20_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d17_d1 ;
wire Iout_a ;
output Iout_d_d16_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d1_d1 ;
output Iout_d_d27_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d22_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d4_d1 ;
wire _en ;
output Iout_d_d24_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d8_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d13_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d9_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d3_d1 ;
wire _out_a_B ;
output Iout_d_d26_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d7_d1 ;
output Iout_d_d25_d0 ;
output Iout_d_d17_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d2_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d3_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d1_d1 ;
output Iout_d_d14_d1 ;
wire _reset_BX ;
output Iout_d_d20_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d21_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d_d19_d0 ;
output Iout_d_d12_d1 ;
wire Iin_d_d9_d0 ;
wire _in_v ;
wire I_out_a_BX0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d14_d0 ;
output Iout_d_d17_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d25_d1 ;
output Iout_d_d5_d1 ;
wire Ien_buf_out0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d25_d1 ;
output Iout_d_d24_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d8_d1 ;
wire Iout_v ;
output Iout_d_d5_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d4_d0 ;
wire I_reset_BXX0 ;
output Iout_d_d15_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d6_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d19_d1 ;
output Iin_a ;
output Iout_d_d18_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d6_d0 ;
output Iout_d_d11_d0 ;
wire Iout_a ;
output Iout_d_d28_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d10_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d9_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d23_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d3_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d15_d1 ;
wire Iin_d_d3_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d17_d1 ;
output Iin_v ;
output Iout_d_d8_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d18_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d0_d1 ;
output Iout_d_d24_d0 ;
wire reset_B;
wire Iin_d_d7_d0 ;
wire _en ;
output Iout_d_d26_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d13_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d22_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d20_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

240
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist/verilog.v

@ -128,138 +128,138 @@ module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d29_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d28_d0 ;
wire Iout_v ;
wire Iin_d_d14_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d_d16_d0 ;
output Iout_d_d23_d0 ;
output Iin_a ;
wire Iin_d_d3_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d21_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d19_d1 ;
output Iout_d_d5_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d14_d0 ;
wire Iin_d_d5_d0 ;
output Iout_d_d20_d0 ;
wire Iin_d_d14_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d2_d1 ;
output Iout_d_d25_d0 ;
wire Iout_a ;
wire Iin_d_d7_d1 ;
wire Iin_d_d24_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d8_d0 ;
output Iin_v ;
output Iout_d_d9_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d22_d1 ;
output Iout_d_d10_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d18_d1 ;
output Iout_d_d27_d1 ;
wire Iin_d_d6_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d21_d0 ;
output Iout_d_d24_d0 ;
wire Iin_d_d17_d0 ;
wire _out_a_B ;
wire Iout_v ;
wire Iin_d_d14_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d9_d0 ;
wire Iin_d_d27_d0 ;
wire reset_B;
output Iout_d_d14_d1 ;
wire _in_v ;
wire Iin_d_d28_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d29_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d12_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d_d12_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d23_d1 ;
wire Iout_a ;
wire Iin_d_d9_d0 ;
output Iout_d_d1_d0 ;
wire _out_a_B ;
wire _reset_BX ;
output Iout_d_d25_d1 ;
output Iout_d_d8_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d_d15_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d4_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d22_d1 ;
output Iout_d_d6_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d26_d0 ;
output Iout_d_d29_d1 ;
wire Iin_d_d28_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d18_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d15_d1 ;
wire _en ;
wire Iin_d_d7_d0 ;
wire Iin_d_d18_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d26_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d27_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d13_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d6_d0 ;
output Iout_d_d3_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d19_d0 ;
wire Iin_d_d6_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d25_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d24_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d4_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d6_d0 ;
output Iin_v ;
wire Iin_d_d2_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d24_d0 ;
wire I_out_a_BX0 ;
wire _in_v ;
wire Iin_d_d11_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d19_d0 ;
wire _en ;
wire _reset_BX ;
wire Iin_d_d28_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d16_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d4_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d14_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d15_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d13_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d_d19_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d8_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d7_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d22_d1 ;
output Iout_d_d12_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d20_d1 ;
output Iout_d_d5_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d20_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d29_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d25_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d27_d0 ;
output Iin_a ;
output Iout_d_d9_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d21_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d16_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d13_d1 ;
wire Iin_d_d0_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

254
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/verilog.v

@ -132,142 +132,142 @@ module tmpl_0_0dataflow__neuro_0_0buffer_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d25_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d6_d1 ;
output Iout_d_d28_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d22_d1 ;
output Iout_d_d26_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d27_d1 ;
wire Iout_v ;
wire Iin_d_d14_d1 ;
output Iout_d_d20_d0 ;
wire Iin_d_d11_d1 ;
output Iout_d_d21_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d17_d0 ;
wire Iin_d_d3_d0 ;
output Iout_d_d4_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d12_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d13_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d_d8_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d10_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d14_d0 ;
wire Iin_d_d19_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d27_d0 ;
output Iin_v ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d5_d0 ;
wire Iin_d_d17_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d13_d0 ;
wire Iin_d_d6_d0 ;
output Iout_d_d15_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d16_d0 ;
output Iout_d_d25_d0 ;
wire _in_v ;
wire Iin_d_d12_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d30_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d3_d0 ;
output Iout_d_d15_d1 ;
wire _reset_BX ;
wire Iin_d_d29_d0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d9_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d28_d1 ;
wire Iout_a ;
wire Iin_d_d13_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d4_d0 ;
wire _en ;
wire Iin_d_d0_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d12_d1 ;
wire _out_a_B ;
wire Iout_v ;
wire Iin_d_d1_d0 ;
output Iout_d_d25_d1 ;
output Iout_d_d27_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d21_d1 ;
wire Iin_d_d5_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d14_d0 ;
output Iout_d_d1_d1 ;
wire Iin_d_d12_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d29_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d22_d0 ;
wire reset_B;
output Iout_d_d24_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d17_d1 ;
output Iout_d_d30_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d8_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d7_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d30_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d5_d0 ;
wire _out_a_B ;
wire Iin_d_d8_d1 ;
wire Iin_d_d13_d0 ;
output Iout_d_d9_d1 ;
output Iout_d_d28_d1 ;
output Iin_a ;
wire Iin_d_d16_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d17_d0 ;
output Iin_a ;
wire _in_v ;
output Iout_d_d15_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d0_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d30_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d8_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d27_d0 ;
output Iin_v ;
wire Iin_d_d12_d1 ;
wire Iin_d_d25_d0 ;
output Iout_d_d15_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d4_d1 ;
output Iout_d_d23_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d30_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d16_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d26_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d10_d1 ;
output Iout_d_d6_d1 ;
output Iout_d_d13_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d3_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d7_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d19_d0 ;
wire Iin_d_d6_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d15_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d1_d0 ;
output Iout_d_d6_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d12_d0 ;
wire Iin_d_d9_d0 ;
wire reset_B;
output Iout_d_d22_d0 ;
output Iout_d_d23_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d20_d0 ;
output Iout_d_d2_d1 ;
wire _reset_BX ;
wire Iin_d_d2_d0 ;
output Iout_d_d12_d1 ;
wire Iin_d_d1_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d22_d0 ;
wire I_out_a_BX0 ;
wire _en ;
wire Iin_d_d5_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d10_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d18_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d18_d0 ;
wire Iout_a ;
wire Iin_d_d15_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

264
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/verilog.v

@ -136,146 +136,146 @@ module tmpl_0_0dataflow__neuro_0_0buffer_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
wire Iin_d_d3_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d19_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d9_d1 ;
wire reset_B;
output Iout_d_d2_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d20_d0 ;
output Iout_d_d31_d0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d28_d0 ;
output Iin_a ;
wire _reset_BX ;
output Iout_d_d29_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d19_d0 ;
wire Iin_d_d9_d1 ;
output Iout_d_d6_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d_d12_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d23_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d17_d0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d28_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d31_d1 ;
output Iout_d_d25_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d14_d1 ;
output Iout_d_d30_d0 ;
wire Iout_v ;
wire Iin_d_d9_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d6_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d29_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d19_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d19_d1 ;
wire Iout_a ;
wire Iin_d_d15_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d7_d0 ;
output Iout_d_d21_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d27_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d8_d0 ;
wire _out_a_B ;
wire Iin_d_d3_d0 ;
wire Iin_d_d13_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d27_d1 ;
wire _in_v ;
output Iout_d_d4_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d1_d0 ;
output Iout_d_d23_d0 ;
output Iin_v ;
wire Iin_d_d1_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d23_d1 ;
wire Iin_d_d20_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d30_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d30_d0 ;
output Iout_d_d24_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d_d31_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d30_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d31_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d24_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d0_d1 ;
wire _en ;
output Iout_d_d4_d0 ;
output Iout_d_d6_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d17_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d26_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d10_d1 ;
output Iout_d_d16_d0 ;
wire _reset_BX ;
wire reset_B;
output Iout_d_d3_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d19_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d_d7_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d19_d0 ;
output Iout_d_d20_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d15_d0 ;
wire Iout_a ;
wire Iin_d_d2_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d28_d1 ;
output Iout_d_d6_d1 ;
output Iout_d_d12_d0 ;
wire Iin_d_d13_d1 ;
output Iout_d_d2_d1 ;
wire Iin_d_d3_d1 ;
output Iout_d_d7_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d30_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d_d30_d1 ;
output Iout_d_d31_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d27_d1 ;
wire Iin_d_d17_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d13_d1 ;
output Iout_d_d8_d1 ;
output Iin_v ;
wire Iin_d_d12_d1 ;
wire Iin_d_d21_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d31_d1 ;
output Iout_d_d15_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d_d22_d1 ;
output Iout_d_d23_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d19_d1 ;
output Iout_d_d26_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d17_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d1_d0 ;
wire _in_v ;
output Iout_d_d0_d1 ;
wire Iout_v ;
wire Iin_d_d5_d1 ;
wire Iin_d_d31_d0 ;
wire Iin_d_d31_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d_d20_d1 ;
output Iout_d_d6_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d24_d1 ;
wire Iin_d_d13_d0 ;
output Iout_d_d11_d1 ;
wire _en ;
wire Iin_d_d25_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d5_d0 ;
output Iout_d_d17_d1 ;
output Iout_d_d25_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d13_d0 ;
wire Iin_d_d14_d0 ;
output Iin_a ;
wire I_out_a_BX0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d11_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

72
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/verilog.v

@ -36,46 +36,46 @@ module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
input reset_B;
// -- signals ---
wire Iin_d_d4_d1 ;
output Iout_d_d6_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d1_d0 ;
wire _reset_BX ;
output Iin_a ;
output Iout_d_d0_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d5_d0 ;
output Iin_v ;
wire I_out_a_BX0 ;
wire _in_v ;
wire Iin_d_d0_d0 ;
wire Iout_v ;
wire Iin_d_d6_d0 ;
wire _out_a_B ;
output Iout_d_d1_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
wire _en ;
wire Iin_d_d5_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d4_d1 ;
wire reset_B;
output Iout_d_d2_d0 ;
wire I_reset_BXX0 ;
output Iout_d_d3_d1 ;
wire Ien_buf_out0 ;
wire Iout_a ;
wire Iin_d_d1_d1 ;
wire _out_a_B ;
output Iout_d_d0_d1 ;
output Iin_a ;
wire Iin_d_d5_d0 ;
output Iout_d_d2_d0 ;
wire I_out_a_BX0 ;
wire _en ;
wire Iin_d_d2_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d1_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d0_d0 ;
wire I_reset_BXX0 ;
output Iout_d_d4_d0 ;
wire Iout_v ;
output Iin_v ;
wire _in_v ;
wire Iin_d_d6_d0 ;
wire Iin_d_d2_d1 ;
wire _reset_BX ;
output Iout_d_d0_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d3_d1 ;
output Iout_d_d4_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d2_d1 ;
wire reset_B;
wire Iin_d_d3_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d3_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

38
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/verilog.v

@ -18,28 +18,28 @@ module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
// -- signals ---
wire out ;
wire Itmp21 ;
wire Iin1 ;
wire Iin6 ;
wire Itmp16 ;
wire Itmp14 ;
wire Itmp13 ;
wire Iin8 ;
wire Itmp18 ;
wire Iin11 ;
wire Iin2 ;
wire Iin12 ;
wire Iin4 ;
wire Iin3 ;
wire Iin1 ;
wire Itmp18 ;
wire Itmp20 ;
wire Iin0 ;
wire Iin9 ;
wire Itmp16 ;
wire Iin12 ;
wire Itmp21 ;
wire Iin2 ;
wire Itmp13 ;
wire Iin11 ;
wire Iin4 ;
wire Itmp15 ;
wire Itmp17 ;
wire Iin10 ;
wire Iin5 ;
wire Itmp19 ;
wire Iin7 ;
wire Iin0 ;
wire Iin10 ;
wire Itmp20 ;
wire Itmp17 ;
wire Iin9 ;
wire Iin5 ;
wire Itmp15 ;
wire Iin6 ;
wire Itmp14 ;
wire Iin8 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp13 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

68
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/verilog.v

@ -27,48 +27,48 @@ module tmpl_0_0dataflow__neuro_0_0ctree_323_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp28 ;
wire Iin9 ;
wire Iin3 ;
wire Itmp35 ;
wire out ;
wire Itmp31 ;
wire Iin10 ;
wire Itmp23 ;
wire Iin14 ;
wire Itmp30 ;
wire Iin22 ;
wire Itmp32 ;
wire Itmp33 ;
wire Itmp38 ;
wire Iin13 ;
wire Iin18 ;
wire Iin8 ;
wire Iin12 ;
wire Itmp24 ;
wire Itmp27 ;
wire Iin1 ;
wire out ;
wire Itmp25 ;
wire Itmp28 ;
wire Iin17 ;
wire Iin15 ;
wire Itmp31 ;
wire Itmp29 ;
wire Iin11 ;
wire Itmp33 ;
wire Iin6 ;
wire Itmp34 ;
wire Iin15 ;
wire Iin13 ;
wire Iin2 ;
wire Itmp38 ;
wire Itmp25 ;
wire Itmp40 ;
wire Itmp37 ;
wire Itmp24 ;
wire Itmp36 ;
wire Iin7 ;
wire Iin17 ;
wire Iin20 ;
wire Iin4 ;
wire Iin14 ;
wire Iin1 ;
wire Iin0 ;
wire Iin21 ;
wire Iin7 ;
wire Iin2 ;
wire Itmp37 ;
wire Iin19 ;
wire Itmp39 ;
wire Itmp30 ;
wire Itmp26 ;
wire Iin5 ;
wire Iin18 ;
wire Itmp27 ;
wire Itmp32 ;
wire Iin4 ;
wire Iin20 ;
wire Itmp35 ;
wire Itmp34 ;
wire Iin6 ;
wire Itmp40 ;
wire Iin16 ;
wire Iin9 ;
wire Itmp26 ;
wire Iin0 ;
wire Iin12 ;
wire Iin10 ;
wire Itmp23 ;
wire Itmp39 ;
wire Iin5 ;
wire Iin3 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp23 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

90
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/verilog.v

@ -33,60 +33,60 @@ module tmpl_0_0dataflow__neuro_0_0ctree_329_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp49 ;
wire Itmp41 ;
wire Itmp40 ;
wire Iin19 ;
wire Iin17 ;
wire Itmp44 ;
wire Iin24 ;
wire Iin12 ;
wire Iin27 ;
wire Iin9 ;
wire Iin7 ;
wire Iin5 ;
wire Itmp48 ;
wire Itmp32 ;
wire Iin1 ;
wire Iin13 ;
wire Itmp33 ;
wire Itmp39 ;
wire Iin18 ;
wire Itmp36 ;
wire Itmp35 ;
wire Itmp34 ;
wire Iin2 ;
wire Iin26 ;
wire Iin23 ;
wire Iin10 ;
wire Itmp51 ;
wire Itmp37 ;
wire Iin3 ;
wire Iin14 ;
wire Iin8 ;
wire Itmp29 ;
wire out ;
wire Itmp50 ;
wire Iin15 ;
wire Itmp46 ;
wire Iin6 ;
wire Itmp52 ;
wire Itmp42 ;
wire Iin9 ;
wire Iin27 ;
wire Itmp51 ;
wire Itmp45 ;
wire Iin16 ;
wire Iin3 ;
wire Iin2 ;
wire Iin1 ;
wire Itmp41 ;
wire Iin26 ;
wire Itmp42 ;
wire Itmp35 ;
wire Iin23 ;
wire Iin20 ;
wire Iin7 ;
wire Itmp48 ;
wire Iin11 ;
wire Itmp31 ;
wire Iin19 ;
wire Iin13 ;
wire Itmp32 ;
wire Iin28 ;
wire Iin25 ;
wire Iin15 ;
wire Itmp36 ;
wire Iin22 ;
wire Iin21 ;
wire Itmp30 ;
wire Itmp47 ;
wire Itmp43 ;
wire Iin20 ;
wire Iin0 ;
wire Itmp38 ;
wire Itmp50 ;
wire Iin18 ;
wire Itmp29 ;
wire Itmp39 ;
wire Iin14 ;
wire Iin8 ;
wire Itmp46 ;
wire Itmp31 ;
wire Iin25 ;
wire Iin6 ;
wire Itmp47 ;
wire Iin4 ;
wire Itmp44 ;
wire Iin12 ;
wire Iin0 ;
wire Iin16 ;
wire Iin5 ;
wire Iin24 ;
wire Itmp40 ;
wire Itmp30 ;
wire Itmp52 ;
wire out ;
wire Itmp49 ;
wire Itmp43 ;
wire Itmp34 ;
wire Iin17 ;
wire Iin10 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp29 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

100
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/verilog.v

@ -34,62 +34,62 @@ module tmpl_0_0dataflow__neuro_0_0ctree_330_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin27 ;
wire Itmp34 ;
wire Itmp45 ;
wire Itmp42 ;
wire Iin13 ;
wire Iin10 ;
wire Iin3 ;
wire Itmp53 ;
wire Iin23 ;
wire Iin20 ;
wire Iin17 ;
wire Itmp39 ;
wire Itmp30 ;
wire Iin26 ;
wire Itmp35 ;
wire Iin6 ;
wire Itmp54 ;
wire Iin22 ;
wire Itmp40 ;
wire Itmp41 ;
wire Iin19 ;
wire Itmp43 ;
wire Iin8 ;
wire Itmp33 ;
wire Iin4 ;
wire Itmp31 ;
wire Itmp49 ;
wire Iin24 ;
wire Iin21 ;
wire Iin2 ;
wire Iin9 ;
wire Iin25 ;
wire Iin15 ;
wire out ;
wire Itmp48 ;
wire Iin14 ;
wire Itmp36 ;
wire Itmp37 ;
wire Iin29 ;
wire Itmp44 ;
wire Iin0 ;
wire Itmp51 ;
wire Iin18 ;
wire Iin16 ;
wire Iin11 ;
wire Iin5 ;
wire Itmp52 ;
wire Itmp31 ;
wire Iin25 ;
wire Iin14 ;
wire Itmp54 ;
wire Iin28 ;
wire Itmp47 ;
wire Itmp38 ;
wire Itmp43 ;
wire Iin17 ;
wire Iin11 ;
wire Itmp52 ;
wire Iin8 ;
wire Itmp34 ;
wire Itmp48 ;
wire Itmp45 ;
wire Iin19 ;
wire Iin13 ;
wire Itmp32 ;
wire Iin12 ;
wire Iin1 ;
wire Iin0 ;
wire Iin6 ;
wire out ;
wire Iin27 ;
wire Iin26 ;
wire Iin9 ;
wire Itmp38 ;
wire Itmp50 ;
wire Itmp47 ;
wire Itmp35 ;
wire Itmp46 ;
wire Iin21 ;
wire Iin5 ;
wire Itmp51 ;
wire Itmp53 ;
wire Itmp49 ;
wire Iin4 ;
wire Iin2 ;
wire Iin23 ;
wire Iin22 ;
wire Iin10 ;
wire Itmp42 ;
wire Iin7 ;
wire Iin1 ;
wire Iin3 ;
wire Itmp41 ;
wire Itmp40 ;
wire Iin16 ;
wire Iin29 ;
wire Iin12 ;
wire Itmp36 ;
wire Itmp33 ;
wire Itmp30 ;
wire Iin20 ;
wire Iin18 ;
wire Itmp44 ;
wire Itmp39 ;
wire Iin15 ;
wire Iin24 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp30 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

98
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/verilog.v

@ -35,63 +35,63 @@ module tmpl_0_0dataflow__neuro_0_0ctree_331_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin20 ;
wire Iin6 ;
wire Itmp49 ;
wire Iin18 ;
wire Iin0 ;
wire Iin30 ;
wire Iin17 ;
wire Itmp38 ;
wire Itmp47 ;
wire Itmp40 ;
wire Iin14 ;
wire Iin11 ;
wire Itmp31 ;
wire Iin29 ;
wire Iin26 ;
wire Iin19 ;
wire Iin5 ;
wire Iin22 ;
wire Itmp33 ;
wire Itmp37 ;
wire out ;
wire Itmp54 ;
wire Iin7 ;
wire Itmp41 ;
wire Itmp39 ;
wire Itmp32 ;
wire Itmp34 ;
wire Iin4 ;
wire Itmp45 ;
wire Itmp51 ;
wire Itmp48 ;
wire Iin21 ;
wire Itmp36 ;
wire Itmp35 ;
wire Iin9 ;
wire Itmp44 ;
wire Iin20 ;
wire Iin22 ;
wire Itmp42 ;
wire Iin8 ;
wire Iin16 ;
wire Itmp35 ;
wire Iin28 ;
wire Iin15 ;
wire Itmp53 ;
wire Itmp46 ;
wire Iin10 ;
wire Iin2 ;
wire Iin24 ;
wire Itmp36 ;
wire Itmp50 ;
wire Iin25 ;
wire Itmp52 ;
wire Iin23 ;
wire Iin13 ;
wire Iin3 ;
wire Iin1 ;
wire Itmp55 ;
wire Iin19 ;
wire Itmp33 ;
wire Itmp49 ;
wire Itmp38 ;
wire Itmp34 ;
wire Itmp43 ;
wire Iin10 ;
wire Itmp48 ;
wire Iin15 ;
wire Iin25 ;
wire Iin14 ;
wire Iin8 ;
wire Itmp55 ;
wire Iin18 ;
wire Itmp40 ;
wire Itmp37 ;
wire Iin3 ;
wire Itmp31 ;
wire out ;
wire Itmp45 ;
wire Itmp53 ;
wire Iin12 ;
wire Iin6 ;
wire Iin5 ;
wire Iin16 ;
wire Iin13 ;
wire Iin1 ;
wire Itmp32 ;
wire Iin4 ;
wire Iin29 ;
wire Itmp50 ;
wire Itmp46 ;
wire Iin7 ;
wire Iin0 ;
wire Iin2 ;
wire Iin26 ;
wire Iin30 ;
wire Itmp41 ;
wire Itmp52 ;
wire Iin17 ;
wire Itmp39 ;
wire Iin11 ;
wire Itmp54 ;
wire Itmp47 ;
wire Iin27 ;
wire Iin21 ;
wire Itmp51 ;
wire Iin23 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp31 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

120
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/verilog.v

@ -36,69 +36,69 @@ module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp40 ;
wire Itmp55 ;
wire Iin18 ;
wire Itmp41 ;
wire Itmp60 ;
wire Iin29 ;
wire Iin27 ;
wire Itmp44 ;
wire Iin3 ;
wire Itmp59 ;
wire Itmp52 ;
wire Iin26 ;
wire Itmp38 ;
wire Iin5 ;
wire Iin24 ;
wire Iin22 ;
wire Iin16 ;
wire Iin9 ;
wire Iin2 ;
wire Itmp58 ;
wire Itmp42 ;
wire Itmp49 ;
wire Iin25 ;
wire Itmp43 ;
wire Itmp61 ;
wire Itmp47 ;
wire Iin4 ;
wire Iin1 ;
wire Itmp46 ;
wire Iin21 ;
wire Itmp32 ;
wire Iin17 ;
wire Iin10 ;
wire Itmp33 ;
wire Iin11 ;
wire Itmp36 ;
wire Iin7 ;
wire Itmp56 ;
wire Itmp54 ;
wire Itmp50 ;
wire Iin31 ;
wire Iin23 ;
wire Iin19 ;
wire Itmp45 ;
wire Iin15 ;
wire Itmp39 ;
wire out ;
wire Iin14 ;
wire Iin8 ;
wire Iin0 ;
wire Iin13 ;
wire Itmp57 ;
wire Itmp35 ;
wire Itmp34 ;
wire Itmp53 ;
wire Iin20 ;
wire Itmp51 ;
wire Itmp48 ;
wire Iin30 ;
wire Iin12 ;
wire Iin6 ;
wire Iin28 ;
wire Itmp61 ;
wire Iin29 ;
wire Itmp43 ;
wire Itmp34 ;
wire Itmp56 ;
wire Iin27 ;
wire Iin18 ;
wire Itmp40 ;
wire Iin10 ;
wire Itmp35 ;
wire Iin25 ;
wire Iin13 ;
wire Itmp60 ;
wire Iin15 ;
wire Itmp33 ;
wire Iin31 ;
wire Iin2 ;
wire Iin22 ;
wire Itmp45 ;
wire Itmp38 ;
wire Iin3 ;
wire Iin17 ;
wire Itmp39 ;
wire Itmp36 ;
wire Itmp59 ;
wire Itmp51 ;
wire Iin0 ;
wire Iin19 ;
wire out ;
wire Itmp47 ;
wire Itmp44 ;
wire Iin20 ;
wire Iin9 ;
wire Iin1 ;
wire Itmp49 ;
wire Iin23 ;
wire Itmp58 ;
wire Itmp41 ;
wire Iin12 ;
wire Iin7 ;
wire Itmp46 ;
wire Itmp48 ;
wire Iin24 ;
wire Iin11 ;
wire Itmp55 ;
wire Itmp54 ;
wire Iin30 ;
wire Iin4 ;
wire Itmp52 ;
wire Iin16 ;
wire Iin21 ;
wire Itmp42 ;
wire Iin5 ;
wire Iin14 ;
wire Itmp53 ;
wire Itmp37 ;
wire Iin6 ;
wire Itmp50 ;
wire Iin26 ;
wire Iin8 ;
wire Itmp32 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp32 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

6
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_34_4/netlist/verilog.v

@ -9,12 +9,12 @@ module tmpl_0_0dataflow__neuro_0_0ctree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vd
// -- signals ---
wire Itmp4 ;
wire Itmp5 ;
wire Iin3 ;
wire Iin2 ;
wire Iin0 ;
wire Itmp5 ;
wire out ;
wire Iin2 ;
wire Iin1 ;
wire Iin3 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp4 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

14
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_37_4/netlist/verilog.v

@ -11,17 +11,17 @@ module tmpl_0_0dataflow__neuro_0_0ctree_37_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin2 ;
wire out ;
wire Iin5 ;
wire Itmp8 ;
wire Itmp7 ;
wire Iin6 ;
wire Itmp9 ;
wire Iin1 ;
wire Itmp7 ;
wire Iin5 ;
wire Iin4 ;
wire Iin0 ;
wire Iin3 ;
wire Iin1 ;
wire Iin4 ;
wire Iin6 ;
wire Iin2 ;
wire out ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp7 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

24
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_39_4/netlist/verilog.v

@ -13,22 +13,22 @@ module tmpl_0_0dataflow__neuro_0_0ctree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin7 ;
wire Itmp10 ;
wire Iin4 ;
wire Iin6 ;
wire Iin5 ;
wire Itmp13 ;
wire Iin3 ;
wire Iin0 ;
wire Itmp14 ;
wire out ;
wire Iin3 ;
wire Iin4 ;
wire Iin1 ;
wire Iin8 ;
wire Itmp11 ;
wire Itmp9 ;
wire Itmp12 ;
wire Iin7 ;
wire Iin2 ;
wire Itmp12 ;
wire Iin6 ;
wire Itmp13 ;
wire Iin5 ;
wire out ;
wire Itmp11 ;
wire Iin8 ;
wire Iin0 ;
wire Itmp10 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp9 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

1771
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

21606
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__2d__synapse__hs_315_7348_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

160
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4/netlist/verilog.v

@ -79,93 +79,93 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4(Iin_d0_d0 , Iin_d0_
// -- signals ---
output Iout57 ;
output Iout15 ;
output Iout17 ;
wire Iin_d1_d0 ;
output Iout20 ;
wire Iatree63_in0 ;
wire Iatree55_in3 ;
output Iout59 ;
output Iout29 ;
output Iout18 ;
output Iout2 ;
output Iout54 ;
output Iout51 ;
output Iout36 ;
output Iout60 ;
output Iout52 ;
output Iout6 ;
output Iout5 ;
wire Iatree59_in2 ;
wire Iin_d5_d0 ;
wire Iin_d3_d1 ;
output Iout31 ;
output Iout14 ;
output Iout50 ;
wire Iatree55_in3 ;
output Iout41 ;
output Iout11 ;
wire Iin_d1_d0 ;
output Iout51 ;
output Iout4 ;
output Iout47 ;
wire Iin_d0_d1 ;
output Iout36 ;
wire Iatree63_in5 ;
wire Iatree63_in1 ;
output Iout61 ;
output Iout37 ;
output Iout28 ;
wire Iin_d5_d1 ;
output Iout19 ;
output Iout2 ;
output Iout39 ;
output Iout42 ;
output Iout35 ;
output Iout1 ;
wire Iin_d1_d1 ;
output Iout59 ;
output Iout47 ;
output Iout44 ;
output Iout21 ;
output Iout3 ;
output Iout55 ;
output Iout54 ;
wire Iatree63_in2 ;
output Iout48 ;
output Iout20 ;
wire Iin_d2_d0 ;
output Iout63 ;
output Iout57 ;
output Iout9 ;
output Iout62 ;
output Iout16 ;
output Iout15 ;
output Iout58 ;
output Iout45 ;
output Iout29 ;
wire Iatree63_in4 ;
wire Iatree31_in5 ;
wire Iin_d5_d1 ;
output Iout53 ;
output Iout43 ;
output Iout30 ;
output Iout22 ;
output Iout13 ;
output Iout7 ;
wire Iin_d4_d0 ;
output Iout33 ;
output Iout0 ;
output Iout56 ;
output Iout32 ;
output Iout25 ;
output Iout8 ;
wire Iatree63_in3 ;
output Iout38 ;
output Iout26 ;
output Iout12 ;
wire Iatree61_in1 ;
wire Iin_d0_d0 ;
wire Iin_d2_d1 ;
output Iout18 ;
output Iout34 ;
wire Iin_d4_d1 ;
output Iout23 ;
output Iout17 ;
output Iout10 ;
output Iout27 ;
output Iout14 ;
wire Iatree63_in0 ;
wire Iin_d3_d0 ;
output Iout49 ;
output Iout46 ;
output Iout40 ;
output Iout24 ;
wire Iin_d0_d0 ;
wire Iatree63_in4 ;
wire Iin_d0_d1 ;
output Iout45 ;
output Iout22 ;
wire Iatree63_in2 ;
output Iout50 ;
wire Iatree31_in5 ;
output Iout37 ;
wire Iin_d5_d0 ;
wire Iin_d4_d0 ;
output Iout35 ;
output Iout25 ;
output Iout6 ;
wire Iin_d3_d0 ;
output Iout62 ;
output Iout53 ;
output Iout33 ;
output Iout26 ;
output Iout5 ;
output Iout0 ;
output Iout52 ;
output Iout13 ;
wire Iin_d2_d1 ;
wire Iatree63_in1 ;
output Iout63 ;
output Iout58 ;
output Iout44 ;
wire Iatree63_in5 ;
wire Iin_d3_d1 ;
output Iout48 ;
output Iout38 ;
output Iout34 ;
output Iout32 ;
wire Iatree47_in4 ;
output Iout55 ;
output Iout39 ;
wire Iatree61_in1 ;
output Iout11 ;
output Iout60 ;
output Iout43 ;
output Iout27 ;
output Iout12 ;
output Iout8 ;
wire Iin_d1_d1 ;
output Iout56 ;
output Iout49 ;
output Iout30 ;
output Iout10 ;
output Iout41 ;
output Iout16 ;
output Iout21 ;
wire Iatree59_in2 ;
output Iout42 ;
output Iout19 ;
wire Iin_d4_d1 ;
output Iout61 ;
output Iout9 ;
output Iout1 ;
output Iout46 ;
output Iout23 ;
output Iout3 ;
wire Iatree63_in3 ;
output Iout7 ;
wire Iatree62_in0 ;
// --- instances

38
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist/verilog.v

@ -16,32 +16,32 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4(Iin_d0_d0 , Iin_
// -- signals ---
wire Ien_ands_f1_y ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout0 ;
wire Ien_ands_t0_y ;
wire Idecoder_final_refresh_d0_d0 ;
wire Iin_d1_d1 ;
wire Idecoder_final_refresh_d1_d0 ;
wire Iin_d2_d1 ;
wire Ien_ands_t2_y ;
wire Ien_ands_f0_y ;
wire Iin_d2_d0 ;
wire Ien_ands_t1_y ;
wire Idecoder_final_refresh_d2_d0 ;
wire Idecoder_final_refresh_d2_d1 ;
output Iout5 ;
wire Iin_d0_d1 ;
output Iout4 ;
wire en;
output Iout2 ;
wire Iin_d0_d0 ;
wire Isb_en_out0 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout3 ;
wire Iin_d1_d0 ;
output Iout4 ;
wire Iin_d2_d1 ;
wire Idecoder_final_refresh_d1_d0 ;
output Iout5 ;
wire Idecoder_final_refresh_d0_d0 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Ien_ands_t2_y ;
wire Idecoder_final_refresh_d1_d1 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout1 ;
wire Ien_ands_f2_y ;
wire Iin_d0_d1 ;
wire Ien_ands_t1_y ;
wire Ien_ands_f1_y ;
wire Iin_d0_d0 ;
wire Iin_d2_d0 ;
output Iout2 ;
wire Idecoder_final_refresh_d2_d0 ;
wire Iin_d1_d1 ;
wire Isb_en_out0 ;
output Iout0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .vdd(vdd), .vss(vss));

106
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist/verilog.v

@ -44,68 +44,68 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4(Iin_d0_d0 , Iin
// -- signals ---
wire Iin_d2_d0 ;
output Iout4 ;
wire Ien_ands_f0_y ;
wire Iin_d1_d0 ;
wire Ien_ands_t0_y ;
wire Iin_d0_d0 ;
wire Idecoder_final_refresh_d4_d1 ;
wire en;
output Iout6 ;
wire Ien_ands_f4_y ;
wire Ien_ands_t4_y ;
wire Ien_ands_t1_y ;
output Iout22 ;
wire Iin_d0_d0 ;
wire Idecoder_final_refresh_d3_d0 ;
output Iout20 ;
wire Iin_d3_d0 ;
wire Idecoder_final_refresh_d3_d1 ;
output Iout10 ;
wire Iin_d4_d1 ;
wire Iin_d1_d1 ;
output Iout2 ;
wire Isb_en_out0 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout23 ;
wire Ien_ands_f2_y ;
wire Idecoder_final_refresh_d2_d0 ;
wire Ien_ands_t3_y ;
wire Iin_d4_d0 ;
wire Iin_d3_d1 ;
wire Idecoder_final_refresh_d1_d0 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout25 ;
output Iout24 ;
output Iout29 ;
output Iout7 ;
output Iout4 ;
wire Iin_d0_d1 ;
wire Ien_ands_t4_y ;
wire Ien_ands_t2_y ;
wire Iin_d4_d0 ;
wire Idecoder_final_refresh_d0_d1 ;
wire Idecoder_final_refresh_d1_d0 ;
output Iout26 ;
output Iout0 ;
wire Iin_d3_d0 ;
output Iout13 ;
output Iout17 ;
output Iout10 ;
wire Iin_d3_d1 ;
output Iout15 ;
output Iout5 ;
output Iout24 ;
wire Ien_ands_f2_y ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout20 ;
output Iout18 ;
output Iout16 ;
output Iout3 ;
output Iout2 ;
output Iout8 ;
wire Ien_ands_f1_y ;
output Iout9 ;
output Iout7 ;
wire Idecoder_final_refresh_d4_d0 ;
wire Iin_d1_d1 ;
output Iout21 ;
output Iout27 ;
output Iout14 ;
wire Ien_ands_f3_y ;
output Iout18 ;
output Iout22 ;
output Iout13 ;
wire Ien_ands_t3_y ;
wire en;
output Iout6 ;
output Iout1 ;
wire Iin_d2_d1 ;
output Iout28 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout26 ;
wire Iin_d0_d1 ;
wire Idecoder_final_refresh_d2_d1 ;
output Iout17 ;
output Iout16 ;
output Iout11 ;
output Iout12 ;
output Iout5 ;
output Iout19 ;
output Iout15 ;
output Iout3 ;
output Iout29 ;
output Iout0 ;
output Iout9 ;
wire Iin_d4_d1 ;
wire Idecoder_final_refresh_d3_d1 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Ien_ands_f4_y ;
wire Ien_ands_f3_y ;
output Iout12 ;
wire Idecoder_final_refresh_d4_d0 ;
wire Ien_ands_t1_y ;
output Iout14 ;
wire Iin_d2_d1 ;
output Iout27 ;
wire Ien_ands_f0_y ;
wire Iin_d1_d0 ;
output Iout28 ;
output Iout25 ;
wire Ien_ands_t0_y ;
wire Iin_d2_d0 ;
wire Isb_en_out0 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout23 ;
output Iout11 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .vdd(vdd), .vss(vss));

188
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4/netlist/verilog.v

@ -76,104 +76,104 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4(Iin_d0_d0 , Iin
// -- signals ---
wire Iin_d2_d0 ;
wire Ien_ands_f3_y ;
wire Ien_ands_t0_y ;
output Iout12 ;
output Iout45 ;
wire Ien_ands_f5_y ;
output Iout31 ;
output Iout15 ;
wire Ien_ands_t5_y ;
wire Ien_ands_t3_y ;
output Iout56 ;
output Iout28 ;
output Iout2 ;
output Iout1 ;
output Iout5 ;
output Iout52 ;
output Iout3 ;
output Iout0 ;
wire Iin_d0_d0 ;
output Iout51 ;
output Iout34 ;
output Iout6 ;
wire Ien_ands_t4_y ;
wire Iin_d3_d0 ;
wire Idecoder_final_refresh_d4_d1 ;
wire Idecoder_final_refresh_d3_d1 ;
output Iout36 ;
output Iout29 ;
output Iout23 ;
wire Isb_en_out0 ;
wire en;
output Iout55 ;
output Iout54 ;
output Iout35 ;
wire Ien_ands_t2_y ;
output Iout47 ;
wire Iin_d4_d0 ;
output Iout42 ;
output Iout27 ;
output Iout25 ;
wire Idecoder_final_refresh_d4_d0 ;
wire Ien_ands_t1_y ;
wire Iin_d2_d1 ;
output Iout58 ;
output Iout49 ;
output Iout40 ;
output Iout20 ;
wire Idecoder_final_refresh_d5_d1 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout48 ;
output Iout39 ;
output Iout17 ;
output Iout44 ;
output Iout38 ;
output Iout33 ;
output Iout32 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout57 ;
wire Idecoder_final_refresh_d1_d0 ;
output Iout30 ;
output Iout19 ;
output Iout11 ;
output Iout4 ;
output Iout50 ;
wire Iin_d5_d0 ;
wire Idecoder_final_refresh_d2_d1 ;
output Iout18 ;
wire Iin_d3_d1 ;
output Iout37 ;
output Iout16 ;
wire Ien_ands_t5_y ;
output Iout55 ;
output Iout52 ;
output Iout28 ;
wire Idecoder_final_refresh_d5_d0 ;
output Iout48 ;
output Iout46 ;
output Iout22 ;
output Iout10 ;
wire Iin_d4_d1 ;
output Iout26 ;
output Iout24 ;
output Iout22 ;
wire Iin_d1_d0 ;
wire Idecoder_final_refresh_d3_d0 ;
output Iout13 ;
wire Iin_d1_d1 ;
output Iout53 ;
output Iout59 ;
output Iout7 ;
wire Ien_ands_f1_y ;
wire Idecoder_final_refresh_d1_d0 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout14 ;
output Iout9 ;
output Iout41 ;
output Iout21 ;
wire Ien_ands_f0_y ;
wire Iin_d5_d1 ;
wire Idecoder_final_refresh_d2_d0 ;
output Iout43 ;
output Iout8 ;
wire Iin_d0_d1 ;
wire Idecoder_final_refresh_d5_d0 ;
output Iout46 ;
wire Ien_ands_f4_y ;
wire Iin_d3_d1 ;
output Iout42 ;
output Iout29 ;
output Iout5 ;
wire Ien_ands_t1_y ;
wire Iin_d2_d0 ;
wire Ien_ands_f5_y ;
wire Ien_ands_f2_y ;
wire Ien_ands_f0_y ;
wire Idecoder_final_refresh_d3_d1 ;
wire Idecoder_final_refresh_d2_d1 ;
output Iout31 ;
output Iout20 ;
output Iout11 ;
output Iout6 ;
output Iout24 ;
output Iout59 ;
output Iout43 ;
output Iout37 ;
output Iout23 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout41 ;
wire Iin_d5_d0 ;
output Iout27 ;
output Iout19 ;
output Iout8 ;
wire Ien_ands_t3_y ;
wire Ien_ands_f3_y ;
output Iout54 ;
output Iout18 ;
output Iout50 ;
output Iout32 ;
output Iout13 ;
output Iout4 ;
wire Ien_ands_f4_y ;
wire Ien_ands_t2_y ;
wire en;
wire Idecoder_final_refresh_d5_d1 ;
wire Idecoder_final_refresh_d4_d1 ;
output Iout21 ;
wire Isb_en_out0 ;
output Iout45 ;
output Iout36 ;
output Iout14 ;
output Iout12 ;
wire Ien_ands_t4_y ;
wire Idecoder_final_refresh_d2_d0 ;
output Iout39 ;
wire Ien_ands_t0_y ;
wire Idecoder_final_refresh_d4_d0 ;
wire Idecoder_final_refresh_d3_d0 ;
output Iout58 ;
output Iout34 ;
output Iout33 ;
output Iout3 ;
output Iout47 ;
output Iout35 ;
wire Iin_d4_d0 ;
wire Iin_d0_d1 ;
wire Iin_d3_d0 ;
output Iout56 ;
output Iout40 ;
output Iout1 ;
wire Iin_d1_d1 ;
output Iout57 ;
output Iout16 ;
output Iout2 ;
output Iout17 ;
output Iout7 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout0 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout49 ;
output Iout26 ;
output Iout25 ;
output Iout15 ;
wire Iin_d1_d0 ;
wire Iin_d2_d1 ;
output Iout53 ;
output Iout51 ;
output Iout9 ;
wire Iin_d0_d0 ;
wire Iin_d5_d1 ;
output Iout44 ;
output Iout38 ;
wire Ien_ands_f1_y ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iin_d5_d0 (Ien_ands_f5_y ), .Iin_d5_d1 (Ien_ands_t5_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Iout30 (Iout30 ), .Iout31 (Iout31 ), .Iout32 (Iout32 ), .Iout33 (Iout33 ), .Iout34 (Iout34 ), .Iout35 (Iout35 ), .Iout36 (Iout36 ), .Iout37 (Iout37 ), .Iout38 (Iout38 ), .Iout39 (Iout39 ), .Iout40 (Iout40 ), .Iout41 (Iout41 ), .Iout42 (Iout42 ), .Iout43 (Iout43 ), .Iout44 (Iout44 ), .Iout45 (Iout45 ), .Iout46 (Iout46 ), .Iout47 (Iout47 ), .Iout48 (Iout48 ), .Iout49 (Iout49 ), .Iout50 (Iout50 ), .Iout51 (Iout51 ), .Iout52 (Iout52 ), .Iout53 (Iout53 ), .Iout54 (Iout54 ), .Iout55 (Iout55 ), .Iout56 (Iout56 ), .Iout57 (Iout57 ), .Iout58 (Iout58 ), .Iout59 (Iout59 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .Ifinal_refresh_d5_d0 (Idecoder_final_refresh_d5_d0 ), .Ifinal_refresh_d5_d1 (Idecoder_final_refresh_d5_d1 ), .vdd(vdd), .vss(vss));

792
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_39_7348_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

26
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4/netlist/verilog.v

@ -21,23 +21,23 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4(Iin_d0_d0 ,
// -- signals ---
output Iout3 ;
wire Iin_d1_d1 ;
output Ifinal_refresh_d2_d0 ;
output Iout2 ;
wire Iin_d0_d0 ;
output Iout4 ;
wire Iin_d1_d0 ;
output Ifinal_refresh_d1_d1 ;
output Iout0 ;
output Iout3 ;
wire Iin_d0_d1 ;
wire Iin_d1_d1 ;
output Iout1 ;
output Iout2 ;
output Iout5 ;
output Ifinal_refresh_d0_d0 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d0_d1 ;
output Ifinal_refresh_d0_d1 ;
output Iout4 ;
output Iout0 ;
wire Iin_d2_d0 ;
wire Iin_d0_d0 ;
output Iout1 ;
wire Iin_d2_d1 ;
output Ifinal_refresh_d2_d1 ;
wire Iin_d2_d1 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d2_d0 ;
output Ifinal_refresh_d2_d0 ;
output Ifinal_refresh_d1_d0 ;
// --- instances

56
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4/netlist/verilog.v

@ -34,37 +34,37 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4(Iin_d0_d0
// -- signals ---
wire Iin_d3_d0 ;
output Ifinal_refresh_d1_d0 ;
output Iout13 ;
output Iout1 ;
wire Iin_d1_d0 ;
output Iout14 ;
wire Iin_d2_d0 ;
wire Iin_d3_d1 ;
output Ifinal_refresh_d1_d1 ;
output Ifinal_refresh_d2_d0 ;
output Iout6 ;
output Ifinal_refresh_d3_d1 ;
output Iout3 ;
output Iout10 ;
output Ifinal_refresh_d3_d0 ;
output Iout8 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d0_d0 ;
output Ifinal_refresh_d0_d0 ;
wire Iin_d1_d1 ;
output Iout7 ;
output Iout11 ;
output Iout0 ;
wire Iin_d2_d1 ;
output Iout9 ;
output Iout12 ;
output Iout4 ;
output Ifinal_refresh_d2_d1 ;
output Iout2 ;
wire Iin_d1_d0 ;
output Iout5 ;
output Iout8 ;
wire Iin_d3_d1 ;
output Iout9 ;
output Iout3 ;
output Iout6 ;
output Iout0 ;
output Ifinal_refresh_d1_d0 ;
wire Iin_d2_d0 ;
wire Iin_d1_d1 ;
output Ifinal_refresh_d1_d1 ;
output Ifinal_refresh_d3_d0 ;
output Ifinal_refresh_d2_d1 ;
output Iout7 ;
output Iout4 ;
output Ifinal_refresh_d0_d1 ;
output Iout14 ;
output Ifinal_refresh_d2_d0 ;
output Iout1 ;
output Ifinal_refresh_d0_d0 ;
output Iout2 ;
output Iout13 ;
output Iout10 ;
output Iout11 ;
output Ifinal_refresh_d3_d1 ;
wire Iin_d3_d0 ;
wire Iin_d2_d1 ;
wire Iin_d0_d1 ;
output Iout12 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

92
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4/netlist/verilog.v

@ -53,56 +53,56 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4(Iin_d0_d0
// -- signals ---
output Iout14 ;
output Iout12 ;
output Ifinal_refresh_d2_d0 ;
output Iout3 ;
output Ifinal_refresh_d1_d0 ;
output Iout21 ;
output Ifinal_refresh_d3_d1 ;
output Iout2 ;
output Ifinal_refresh_d0_d0 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d4_d0 ;
output Iout20 ;
wire Iin_d3_d0 ;
output Iout19 ;
output Ifinal_refresh_d4_d1 ;
output Iout11 ;
output Ifinal_refresh_d4_d0 ;
wire Iin_d0_d1 ;
wire Iin_d1_d1 ;
output Iout10 ;
wire Iin_d2_d0 ;
output Ifinal_refresh_d2_d1 ;
output Ifinal_refresh_d1_d1 ;
output Ifinal_refresh_d3_d0 ;
output Iout27 ;
output Iout17 ;
output Iout7 ;
output Iout0 ;
wire Iin_d0_d0 ;
output Iout8 ;
output Iout9 ;
output Iout5 ;
output Iout15 ;
output Iout24 ;
output Iout26 ;
output Iout18 ;
wire Iin_d4_d1 ;
wire Iin_d2_d1 ;
output Iout4 ;
wire Iin_d3_d1 ;
output Iout23 ;
output Iout22 ;
output Iout16 ;
output Iout1 ;
output Iout29 ;
output Iout25 ;
output Iout28 ;
wire Iin_d1_d0 ;
output Iout13 ;
output Iout28 ;
output Iout25 ;
output Iout26 ;
output Iout5 ;
output Iout3 ;
wire Iin_d2_d1 ;
output Ifinal_refresh_d2_d1 ;
wire Iin_d1_d1 ;
output Iout11 ;
output Ifinal_refresh_d1_d1 ;
output Iout23 ;
wire Iin_d4_d0 ;
wire Iin_d3_d0 ;
wire Iin_d4_d1 ;
output Iout8 ;
output Iout7 ;
output Ifinal_refresh_d2_d0 ;
output Iout15 ;
output Iout16 ;
output Ifinal_refresh_d0_d1 ;
output Ifinal_refresh_d4_d1 ;
wire Iin_d0_d1 ;
output Ifinal_refresh_d1_d0 ;
output Iout0 ;
output Iout19 ;
output Iout14 ;
wire Iin_d3_d1 ;
output Iout6 ;
output Ifinal_refresh_d3_d1 ;
output Ifinal_refresh_d0_d0 ;
output Iout10 ;
output Iout9 ;
output Iout24 ;
output Iout20 ;
output Iout12 ;
output Iout1 ;
output Ifinal_refresh_d3_d0 ;
wire Iin_d0_d0 ;
output Iout27 ;
output Iout29 ;
output Iout2 ;
output Iout17 ;
output Ifinal_refresh_d4_d0 ;
output Iout21 ;
output Iout13 ;
output Iout4 ;
output Iout18 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

160
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4/netlist/verilog.v

@ -87,90 +87,90 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4(Iin_d0_d0
// -- signals ---
output Iout27 ;
output Iout54 ;
output Iout42 ;
wire Iin_d5_d1 ;
output Iout39 ;
output Iout22 ;
output Iout13 ;
output Ifinal_refresh_d5_d0 ;
output Iout5 ;
output Ifinal_refresh_d0_d0 ;
wire Iin_d5_d0 ;
output Iout56 ;
output Iout44 ;
output Ifinal_refresh_d1_d0 ;
output Iout59 ;
output Iout35 ;
output Iout6 ;
output Iout30 ;
output Iout10 ;
output Iout2 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d2_d1 ;
output Iout58 ;
output Iout38 ;
output Iout23 ;
output Iout18 ;
output Ifinal_refresh_d2_d0 ;
output Iout53 ;
output Ifinal_refresh_d4_d1 ;
output Iout32 ;
output Iout19 ;
output Iout15 ;
wire Iin_d4_d1 ;
wire Iin_d1_d1 ;
output Iout55 ;
output Iout43 ;
output Iout26 ;
output Iout40 ;
output Iout1 ;
output Iout14 ;
output Iout31 ;
output Iout4 ;
output Iout57 ;
output Iout34 ;
output Iout29 ;
output Iout12 ;
output Ifinal_refresh_d4_d0 ;
output Iout11 ;
output Ifinal_refresh_d3_d1 ;
wire Iin_d0_d1 ;
wire Iin_d3_d0 ;
output Iout41 ;
output Ifinal_refresh_d5_d1 ;
output Iout21 ;
output Iout20 ;
output Iout45 ;
output Ifinal_refresh_d2_d1 ;
output Iout0 ;
output Iout52 ;
output Iout25 ;
output Iout46 ;
output Iout7 ;
output Iout3 ;
output Iout51 ;
output Iout50 ;
output Iout49 ;
output Iout33 ;
output Iout24 ;
output Iout16 ;
output Ifinal_refresh_d1_d1 ;
output Iout36 ;
output Iout9 ;
output Iout8 ;
output Ifinal_refresh_d3_d0 ;
wire Iin_d4_d0 ;
wire Iin_d1_d0 ;
wire Iin_d0_d0 ;
output Iout48 ;
output Iout37 ;
output Iout28 ;
output Iout17 ;
wire Iin_d2_d0 ;
output Iout54 ;
output Iout16 ;
output Iout57 ;
output Ifinal_refresh_d4_d1 ;
output Iout1 ;
output Iout45 ;
output Iout24 ;
output Iout13 ;
output Iout12 ;
output Iout10 ;
output Iout4 ;
wire Iin_d3_d1 ;
wire Iin_d2_d1 ;
wire Iin_d1_d0 ;
output Iout40 ;
output Iout32 ;
output Iout50 ;
output Iout11 ;
output Iout6 ;
output Iout29 ;
output Ifinal_refresh_d0_d0 ;
output Iout25 ;
output Iout51 ;
output Iout15 ;
output Ifinal_refresh_d4_d0 ;
output Iout47 ;
output Iout39 ;
output Iout36 ;
output Iout26 ;
output Iout18 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d5_d0 ;
output Iout7 ;
output Ifinal_refresh_d5_d0 ;
wire Iin_d5_d1 ;
wire Iin_d4_d0 ;
output Iout38 ;
output Iout27 ;
wire Iin_d4_d1 ;
output Iout31 ;
wire Iin_d3_d0 ;
output Iout53 ;
output Iout42 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d2_d0 ;
output Iout49 ;
output Iout35 ;
output Iout30 ;
output Iout20 ;
output Iout58 ;
output Iout41 ;
output Ifinal_refresh_d2_d1 ;
output Iout43 ;
output Iout23 ;
output Ifinal_refresh_d5_d1 ;
output Iout28 ;
output Iout22 ;
output Ifinal_refresh_d3_d0 ;
output Iout48 ;
output Iout3 ;
output Iout33 ;
output Iout2 ;
output Ifinal_refresh_d1_d0 ;
output Iout55 ;
output Iout0 ;
output Iout44 ;
output Iout34 ;
output Iout9 ;
output Iout37 ;
output Iout21 ;
output Iout17 ;
output Iout59 ;
output Iout46 ;
output Iout19 ;
output Ifinal_refresh_d3_d1 ;
output Iout5 ;
wire Iin_d0_d0 ;
wire Iin_d1_d1 ;
output Iout56 ;
output Iout14 ;
wire Iin_d0_d1 ;
output Ifinal_refresh_d2_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

852
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4/netlist/verilog.v

@ -387,444 +387,444 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4(Iin_d0_d0
// -- signals ---
wire Iin_tX29_a ;
output Iout197 ;
wire Iin_d3_d0 ;
output Iout239 ;
wire Iin_tX12_a ;
wire Iin_fX12_a ;
output Iout344 ;
output Iout331 ;
output Iout63 ;
wire Iin_fX32_a ;
wire Iin_d2_d1 ;
output Iout71 ;
output Iout176 ;
output Iout201 ;
output Ifinal_refresh_d7_d1 ;
output Iout333 ;
output Iout241 ;
output Iout45 ;
output Iout339 ;
output Iout315 ;
wire Iin_tX35_a ;
output Iout53 ;
output Iout160 ;
output Iout185 ;
output Iout52 ;
output Iout342 ;
output Iout256 ;
output Iout69 ;
output Iout330 ;
output Iout96 ;
output Iout77 ;
output Iout75 ;
output Iout38 ;
output Iout33 ;
output Iout146 ;
output Iout178 ;
wire Iin_fX30_a ;
output Iout204 ;
output Iout208 ;
wire Iin_tX14_a ;
output Iout174 ;
output Iout274 ;
output Iout15 ;
output Iout102 ;
wire Iin_fX29_a ;
output Iout289 ;
output Iout64 ;
output Iout35 ;
wire Iin_fX9_a ;
wire Iin_d6_d0 ;
output Iout284 ;
output Iout84 ;
wire Iin_fX23_a ;
output Iout327 ;
output Iout293 ;
output Iout254 ;
output Iout7 ;
output Iout131 ;
output Iout172 ;
output Iout306 ;
output Iout67 ;
wire Iin_fX24_a ;
output Ifinal_refresh_d5_d0 ;
output Iout68 ;
output Iout196 ;
wire Iin_tX30_a ;
output Iout209 ;
output Iout318 ;
output Iout275 ;
output Iout214 ;
output Iout95 ;
output Iout65 ;
output Iout22 ;
output Ifinal_refresh_d2_d0 ;
output Iout233 ;
wire Iin_tX21_a ;
output Iout118 ;
output Iout191 ;
output Ifinal_refresh_d2_d1 ;
output Iout247 ;
output Iout80 ;
output Iout76 ;
output Iout328 ;
output Iout285 ;
output Iout44 ;
output Iout115 ;
output Iout130 ;
output Iout309 ;
wire Iin_tX23_a ;
output Iout14 ;
output Iout103 ;
wire Iin_d1_d1 ;
output Iout260 ;
output Iout81 ;
output Iout29 ;
output Iout148 ;
output Iout216 ;
output Iout91 ;
output Iout62 ;
output Iout104 ;
output Iout343 ;
output Iout335 ;
output Iout325 ;
wire Iin_d7_d0 ;
output Iout319 ;
output Iout17 ;
output Iout4 ;
output Iout273 ;
output Iout107 ;
output Iout120 ;
output Iout288 ;
output Iout226 ;
output Iout286 ;
output Iout213 ;
output Iout82 ;
output Iout13 ;
output Ifinal_refresh_d1_d0 ;
output Iout278 ;
output Iout250 ;
output Iout49 ;
output Iout132 ;
output Iout200 ;
wire Iin_d0_d0 ;
output Iout341 ;
output Iout262 ;
output Iout51 ;
output Iout126 ;
output Iout147 ;
output Iout272 ;
output Iout97 ;
output Iout90 ;
wire Iin_fX17_a ;
output Iout313 ;
output Iout158 ;
output Iout34 ;
output Iout133 ;
output Iout334 ;
output Ifinal_refresh_d6_d0 ;
output Iout42 ;
output Iout108 ;
output Iout94 ;
output Iout222 ;
wire Iin_fX18_a ;
output Iout86 ;
output Iout128 ;
output Iout167 ;
output Iout300 ;
output Iout161 ;
wire Iin_d3_d1 ;
output Iout99 ;
wire Iin_tX28_a ;
output Iout280 ;
output Iout83 ;
wire Iin_fX31_a ;
output Iout30 ;
output Iout347 ;
output Iout236 ;
wire Iin_tX20_a ;
output Iout23 ;
output Iout10 ;
output Iout5 ;
output Iout117 ;
output Iout206 ;
wire Iin_d8_d0 ;
output Iout50 ;
output Iout190 ;
output Iout264 ;
output Iout251 ;
output Iout16 ;
output Iout287 ;
output Iout235 ;
output Iout255 ;
output Iout225 ;
output Iout124 ;
wire Iin_tX34_a ;
output Iout192 ;
wire Iin_d0_d1 ;
output Iout301 ;
output Iout282 ;
wire Iin_fX22_a ;
output Iout111 ;
output Iout198 ;
output Iout336 ;
output Iout238 ;
output Iout156 ;
output Iout171 ;
output Iout184 ;
output Iout230 ;
output Iout140 ;
wire Iin_tX17_a ;
output Iout18 ;
output Iout2 ;
output Iout153 ;
output Iout304 ;
output Iout183 ;
output Iout302 ;
output Iout186 ;
output Iout252 ;
output Iout227 ;
wire Iin_tX13_a ;
output Iout6 ;
output Ifinal_refresh_d4_d1 ;
output Iout243 ;
output Iout210 ;
output Iout47 ;
output Iout135 ;
output Iout144 ;
output Iout314 ;
output Iout149 ;
output Iout87 ;
wire Iin_tX25_a ;
output Iout155 ;
output Iout207 ;
output Iout290 ;
output Iout277 ;
output Iout100 ;
wire Iin_tX31_a ;
wire Iin_d4_d0 ;
output Iout267 ;
output Iout73 ;
output Iout48 ;
output Iout177 ;
output Iout205 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_fX34_a ;
wire Iin_tX18_a ;
output Iout46 ;
output Iout159 ;
output Iout266 ;
output Iout116 ;
output Iout127 ;
wire Iin_fX27_a ;
output Iout269 ;
output Iout78 ;
output Iout170 ;
output Iout310 ;
output Iout79 ;
wire Iin_fX15_a ;
output Iout203 ;
output Iout258 ;
output Iout229 ;
output Iout154 ;
output Iout182 ;
output Iout320 ;
output Iout106 ;
output Ifinal_refresh_d6_d1 ;
output Iout189 ;
output Iout265 ;
output Iout215 ;
output Iout25 ;
output Iout188 ;
output Iout279 ;
wire Iin_tX16_a ;
output Iout323 ;
output Iout297 ;
output Iout41 ;
output Iout164 ;
output Ifinal_refresh_d7_d0 ;
output Iout212 ;
output Iout305 ;
output Iout223 ;
output Iout57 ;
output Iout32 ;
output Iout311 ;
wire Iin_fX10_a ;
output Iout113 ;
output Iout312 ;
output Iout299 ;
output Ifinal_refresh_d8_d1 ;
output Iout270 ;
wire Iin_fX26_a ;
output Iout92 ;
output Iout61 ;
output Iout89 ;
output Iout101 ;
output Iout157 ;
output Iout202 ;
output Iout19 ;
output Iout137 ;
output Iout179 ;
wire Iin_d7_d1 ;
output Iout1 ;
output Iout37 ;
output Iout307 ;
output Iout263 ;
wire Iin_tX9_a ;
output Iout141 ;
output Iout345 ;
output Iout23 ;
output Iout180 ;
output Ifinal_refresh_d4_d0 ;
output Iout66 ;
output Iout125 ;
output Iout138 ;
output Iout316 ;
output Iout58 ;
output Iout142 ;
output Iout150 ;
output Iout181 ;
output Iout193 ;
output Ifinal_refresh_d3_d1 ;
wire Iin_tX24_a ;
output Iout72 ;
output Iout59 ;
output Iout332 ;
output Iout221 ;
output Iout122 ;
output Iout173 ;
output Iout244 ;
output Iout36 ;
output Iout144 ;
output Iout204 ;
output Iout341 ;
output Iout267 ;
output Iout241 ;
output Iout218 ;
output Iout28 ;
output Iout143 ;
output Iout211 ;
output Iout346 ;
output Iout321 ;
output Iout12 ;
output Iout3 ;
wire Iin_fX16_a ;
output Iout224 ;
output Iout166 ;
output Iout272 ;
output Iout124 ;
wire Iin_tX17_a ;
wire Iin_d2_d1 ;
output Iout186 ;
output Iout164 ;
wire Iin_fX30_a ;
output Iout49 ;
output Iout6 ;
output Iout88 ;
output Iout75 ;
output Iout26 ;
output Iout275 ;
output Iout97 ;
wire Iin_fX27_a ;
wire Iin_tX33_a ;
output Ifinal_refresh_d0_d0 ;
wire Iin_tX32_a ;
output Iout139 ;
output Iout152 ;
output Iout295 ;
output Iout256 ;
output Iout232 ;
output Iout320 ;
output Ifinal_refresh_d6_d1 ;
output Iout316 ;
output Iout290 ;
output Iout59 ;
wire Iin_fX14_a ;
output Iout205 ;
output Iout325 ;
output Ifinal_refresh_d6_d0 ;
wire Iin_fX16_a ;
wire Iin_tX29_a ;
output Iout314 ;
output Iout270 ;
output Iout81 ;
wire Iin_tX28_a ;
output Iout100 ;
output Iout74 ;
wire Iin_fX10_a ;
output Iout250 ;
output Iout244 ;
wire Iin_tX34_a ;
output Iout56 ;
output Iout43 ;
wire Iin_fX24_a ;
wire Iin_d5_d0 ;
output Iout257 ;
output Iout140 ;
wire Iin_fX28_a ;
output Iout253 ;
output Iout77 ;
output Iout54 ;
output Iout149 ;
output Iout286 ;
wire Iin_fX12_a ;
output Iout133 ;
output Iout296 ;
output Iout283 ;
output Iout8 ;
output Iout117 ;
output Iout221 ;
wire Iin_fX23_a ;
output Iout319 ;
output Iout222 ;
output Iout142 ;
output Iout347 ;
output Iout298 ;
output Iout248 ;
output Iout235 ;
output Iout127 ;
output Iout148 ;
wire Iin_d4_d0 ;
output Iout276 ;
output Iout330 ;
output Iout254 ;
output Iout252 ;
output Iout32 ;
output Iout71 ;
output Iout28 ;
wire Iin_tX9_a ;
output Ifinal_refresh_d8_d0 ;
output Ifinal_refresh_d2_d1 ;
output Iout288 ;
output Iout135 ;
output Iout329 ;
output Iout220 ;
output Iout22 ;
output Iout318 ;
output Ifinal_refresh_d1_d1 ;
output Iout279 ;
output Iout20 ;
output Iout145 ;
output Iout190 ;
output Ifinal_refresh_d3_d1 ;
output Iout273 ;
output Iout24 ;
output Iout11 ;
output Iout175 ;
output Ifinal_refresh_d5_d1 ;
wire Iin_fX11_a ;
output Iout322 ;
output Iout259 ;
wire Iin_tX10_a ;
output Iout169 ;
output Iout194 ;
output Iout248 ;
output Iout232 ;
output Iout219 ;
wire Iin_fX17_a ;
output Iout119 ;
output Iout136 ;
wire Iin_tX26_a ;
output Iout268 ;
output Iout261 ;
wire Iin_tX19_a ;
output Iout54 ;
output Iout26 ;
output Iout145 ;
output Iout187 ;
output Iout308 ;
wire Iin_tX11_a ;
output Iout0 ;
output Iout109 ;
output Iout163 ;
wire Iin_d2_d0 ;
output Iout60 ;
wire Iin_fX35_a ;
output Iout220 ;
wire Iin_tX22_a ;
output Iout123 ;
output Iout245 ;
output Iout217 ;
output Iout8 ;
wire Iin_d8_d1 ;
output Iout98 ;
output Iout85 ;
output Iout281 ;
output Iout21 ;
output Iout112 ;
output Iout114 ;
wire Iin_fX28_a ;
output Iout276 ;
output Iout43 ;
wire Iin_d5_d0 ;
wire Iin_d4_d1 ;
output Iout246 ;
wire Iin_fX21_a ;
wire Iin_fX13_a ;
output Ifinal_refresh_d0_d1 ;
wire Iin_tX15_a ;
wire Iin_fX14_a ;
output Iout56 ;
output Iout231 ;
output Iout40 ;
output Iout27 ;
output Iout20 ;
wire Iin_d1_d0 ;
wire Iin_fX25_a ;
wire Iin_fX20_a ;
output Iout55 ;
output Iout105 ;
output Iout168 ;
output Iout257 ;
output Iout237 ;
output Iout31 ;
output Iout9 ;
output Iout162 ;
wire Iin_d6_d1 ;
output Iout337 ;
output Iout324 ;
output Iout340 ;
output Iout329 ;
output Iout292 ;
output Ifinal_refresh_d8_d0 ;
wire Iin_fX33_a ;
output Iout70 ;
output Iout129 ;
output Iout303 ;
output Iout240 ;
output Iout74 ;
output Iout317 ;
output Iout151 ;
wire Iin_d5_d1 ;
output Iout169 ;
output Iout280 ;
output Iout236 ;
output Iout35 ;
output Iout132 ;
output Iout247 ;
wire Iin_fX26_a ;
output Iout146 ;
output Iout141 ;
output Iout305 ;
output Iout271 ;
output Iout134 ;
output Iout326 ;
output Iout298 ;
output Iout296 ;
output Iout228 ;
output Iout165 ;
wire Iin_fX19_a ;
output Iout88 ;
wire Iin_tX27_a ;
output Iout195 ;
output Iout294 ;
output Iout291 ;
output Iout249 ;
output Iout39 ;
output Iout110 ;
output Iout121 ;
output Iout199 ;
output Iout253 ;
output Iout242 ;
output Iout93 ;
output Iout246 ;
output Iout219 ;
output Iout73 ;
output Iout101 ;
output Iout198 ;
wire Iin_tX30_a ;
output Iout300 ;
output Iout231 ;
output Iout155 ;
output Iout168 ;
output Iout192 ;
output Iout87 ;
output Iout29 ;
output Iout108 ;
output Iout344 ;
output Iout86 ;
output Iout7 ;
output Iout61 ;
output Iout33 ;
output Iout114 ;
output Iout128 ;
output Iout53 ;
output Iout157 ;
output Iout171 ;
output Iout310 ;
output Iout268 ;
output Iout243 ;
output Iout113 ;
output Iout161 ;
output Iout346 ;
output Iout226 ;
output Iout51 ;
output Iout1 ;
output Iout260 ;
output Iout63 ;
output Iout162 ;
output Iout333 ;
output Iout90 ;
output Iout139 ;
output Iout304 ;
output Ifinal_refresh_d3_d0 ;
output Iout36 ;
output Iout338 ;
output Iout283 ;
output Iout230 ;
output Iout92 ;
output Iout111 ;
output Iout202 ;
output Iout281 ;
wire Iin_tX24_a ;
output Iout57 ;
output Iout317 ;
output Iout289 ;
wire Iin_fX18_a ;
output Iout30 ;
wire Iin_tX21_a ;
output Iout185 ;
wire Iin_d5_d1 ;
wire Iin_d0_d1 ;
output Iout240 ;
output Iout167 ;
output Iout178 ;
output Iout259 ;
output Iout238 ;
output Iout278 ;
wire Iin_tX22_a ;
output Iout191 ;
output Iout323 ;
wire Iin_fX20_a ;
output Iout82 ;
output Iout69 ;
output Iout179 ;
wire Iin_fX33_a ;
output Iout165 ;
output Iout206 ;
output Iout324 ;
output Iout64 ;
output Iout110 ;
output Iout287 ;
output Iout14 ;
output Iout116 ;
output Iout201 ;
output Iout291 ;
output Iout263 ;
wire Iin_tX12_a ;
output Iout181 ;
output Iout242 ;
wire Iin_tX18_a ;
output Iout138 ;
output Iout176 ;
output Iout301 ;
output Iout233 ;
wire Iin_tX11_a ;
wire Iin_fX32_a ;
output Iout208 ;
output Iout311 ;
output Iout212 ;
output Iout25 ;
output Iout303 ;
output Iout173 ;
wire Iin_fX29_a ;
output Ifinal_refresh_d7_d0 ;
output Iout93 ;
output Iout293 ;
output Iout249 ;
output Iout224 ;
output Iout125 ;
output Iout172 ;
wire Iin_d8_d1 ;
wire Iin_d7_d1 ;
output Iout229 ;
output Iout223 ;
output Iout39 ;
output Iout264 ;
output Iout68 ;
wire Iin_d8_d0 ;
output Iout213 ;
output Iout107 ;
output Iout137 ;
output Iout228 ;
output Iout21 ;
output Iout118 ;
output Iout210 ;
wire Iin_fX22_a ;
output Iout3 ;
output Ifinal_refresh_d8_d1 ;
output Iout234 ;
output Iout195 ;
output Iout262 ;
wire Iin_fX19_a ;
output Iout47 ;
output Iout31 ;
wire Iin_fX13_a ;
output Iout131 ;
output Iout166 ;
output Iout328 ;
output Iout315 ;
output Iout265 ;
wire Iin_fX21_a ;
output Iout76 ;
output Iout154 ;
output Iout216 ;
output Iout196 ;
output Iout203 ;
output Iout10 ;
output Iout189 ;
output Iout197 ;
output Iout321 ;
output Iout308 ;
output Iout340 ;
output Iout215 ;
output Iout13 ;
output Iout103 ;
output Iout343 ;
output Iout45 ;
output Iout12 ;
output Iout163 ;
output Ifinal_refresh_d4_d1 ;
output Ifinal_refresh_d2_d0 ;
output Iout285 ;
wire Iin_tX23_a ;
output Iout17 ;
wire Iin_fX15_a ;
output Iout85 ;
output Iout41 ;
output Iout37 ;
output Iout62 ;
wire Iin_tX13_a ;
output Iout170 ;
output Iout295 ;
output Iout277 ;
wire Iin_fX9_a ;
output Iout156 ;
wire Iin_d7_d0 ;
wire Iin_d6_d0 ;
output Iout27 ;
output Iout214 ;
output Iout65 ;
output Iout334 ;
output Iout322 ;
output Iout274 ;
output Iout261 ;
output Iout225 ;
wire Iin_tX20_a ;
output Iout98 ;
output Iout2 ;
wire Iin_tX25_a ;
output Iout19 ;
output Iout122 ;
output Iout183 ;
wire Iin_fX31_a ;
output Iout312 ;
output Iout245 ;
output Iout66 ;
wire Iin_tX35_a ;
output Iout58 ;
wire Iin_tX16_a ;
output Ifinal_refresh_d4_d0 ;
output Iout99 ;
output Iout50 ;
output Iout174 ;
wire Iin_fX35_a ;
output Iout269 ;
output Iout52 ;
output Iout4 ;
output Iout345 ;
output Iout302 ;
output Iout95 ;
wire Iin_tX15_a ;
output Iout40 ;
output Iout153 ;
output Ifinal_refresh_d7_d1 ;
output Iout332 ;
output Iout84 ;
output Iout152 ;
wire Iin_d2_d0 ;
wire Iin_fX11_a ;
output Iout115 ;
output Iout177 ;
wire Iin_tX27_a ;
wire Iin_d0_d0 ;
wire Iin_tX26_a ;
output Ifinal_refresh_d0_d1 ;
output Iout217 ;
output Iout120 ;
output Iout184 ;
output Iout342 ;
output Iout200 ;
wire Iin_d4_d1 ;
output Iout158 ;
output Iout83 ;
output Iout46 ;
wire Iin_tX10_a ;
output Iout188 ;
output Iout15 ;
output Iout182 ;
output Iout338 ;
output Iout258 ;
output Iout38 ;
output Iout106 ;
output Iout134 ;
wire Iin_d6_d1 ;
output Iout48 ;
output Iout327 ;
output Iout309 ;
output Iout147 ;
output Iout299 ;
output Iout251 ;
output Iout55 ;
output Iout209 ;
wire Iin_d3_d1 ;
output Iout313 ;
output Iout335 ;
output Iout89 ;
output Iout112 ;
output Iout151 ;
output Iout339 ;
output Ifinal_refresh_d1_d0 ;
output Iout109 ;
output Iout175 ;
output Iout326 ;
output Ifinal_refresh_d5_d0 ;
output Iout266 ;
output Iout42 ;
output Iout297 ;
output Iout282 ;
wire Iin_fX25_a ;
output Iout72 ;
output Iout5 ;
output Iout126 ;
output Ifinal_refresh_d0_d0 ;
output Iout255 ;
output Iout105 ;
output Iout336 ;
output Iout79 ;
output Iout44 ;
output Iout187 ;
output Iout307 ;
output Iout18 ;
output Iout150 ;
output Iout199 ;
output Iout130 ;
wire Iin_tX31_a ;
wire Iin_d1_d0 ;
output Iout284 ;
wire Iin_tX32_a ;
output Iout96 ;
output Iout78 ;
output Iout121 ;
output Iout207 ;
output Iout337 ;
output Iout294 ;
output Iout91 ;
output Iout70 ;
output Iout104 ;
wire Iin_d1_d1 ;
output Iout292 ;
output Iout239 ;
output Iout227 ;
output Iout211 ;
output Iout160 ;
output Iout94 ;
output Iout80 ;
wire Iin_tX14_a ;
output Iout123 ;
output Iout136 ;
output Ifinal_refresh_d5_d1 ;
output Iout237 ;
output Iout60 ;
output Iout34 ;
wire Iin_d3_d0 ;
output Iout331 ;
output Iout67 ;
output Iout9 ;
output Iout194 ;
output Iout306 ;
wire Iin_tX19_a ;
output Iout0 ;
output Iout129 ;
output Iout159 ;
output Iout16 ;
output Iout102 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_39_4 Iatree0 (.Iin0 (Iin_fX9_a ), .Iin1 (Iin_fX10_a ), .Iin2 (Iin_fX11_a ), .Iin3 (Iin_fX12_a ), .Iin4 (Iin_fX13_a ), .Iin5 (Iin_fX14_a ), .Iin6 (Iin_fX15_a ), .Iin7 (Iin_fX16_a ), .Iin8 (Iin_fX17_a ), .out(Iout0 ), .vdd(vdd), .vss(vss));

12
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_32_4/netlist/verilog.v

@ -7,16 +7,16 @@ module tmpl_0_0dataflow__neuro_0_0delayprog_32_4(out, in, Is0 , Is1 , vdd, vss);
input Is1 ;
// -- signals ---
wire Idly0_y ;
wire Is1 ;
wire Idly0_a ;
wire Idly2_a ;
wire Idly2_y ;
wire out ;
wire in;
wire Is0 ;
wire Idly2_a ;
wire Idly1_a ;
wire Idly0_y ;
wire I_a1 ;
wire Idly2_y ;
wire Idly0_a ;
wire out ;
wire Is1 ;
// --- instances
AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));

40
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/verilog.v

@ -10,33 +10,33 @@ module tmpl_0_0dataflow__neuro_0_0delayprog_34_4(out, in, Is0 , Is1 , Is2 , Is3
// -- signals ---
wire Idly11_a ;
wire Idly6_a ;
wire Idly9_a ;
wire Is2 ;
wire Idly14_a ;
wire Idly14_y ;
wire Idly13_a ;
wire I_a1 ;
wire Idly4_a ;
wire Idly7_a ;
wire Idly1_a ;
wire Idly5_a ;
wire Idly2_y ;
wire Idly14_a ;
wire Idly9_a ;
wire in;
wire Idly12_a ;
wire Idly10_a ;
wire out ;
wire Idly13_a ;
wire I_a3 ;
wire Idly3_a ;
wire Idly0_a ;
wire Idly2_a ;
wire Idly14_y ;
wire Idly6_y ;
wire Is0 ;
wire Is1 ;
wire I_a1 ;
wire out ;
wire Idly6_a ;
wire I_a2 ;
wire Idly10_a ;
wire Idly0_y ;
wire Idly8_a ;
wire Is3 ;
wire in;
wire Idly3_a ;
wire Idly0_y ;
wire Idly12_a ;
wire Idly6_y ;
wire Idly1_a ;
wire Idly4_a ;
wire Idly2_y ;
wire I_a3 ;
wire Idly2_a ;
wire Idly7_a ;
wire Is2 ;
// --- instances
AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));

396
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0demux_330_4/netlist/verilog.v

@ -193,209 +193,209 @@ module tmpl_0_0dataflow__neuro_0_0demux_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
// -- signals ---
output Iout1_d_d1_d0 ;
wire Iout1_a ;
output Iout2_d_d13_d1 ;
output Iout1_d_d28_d1 ;
wire Iin_d_d23_d0 ;
wire I_reset_BXX0 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d0_d1 ;
wire Iout1_v ;
output Iout2_d_d4_d1 ;
wire Iin_d_d20_d1 ;
output Iout1_d_d5_d1 ;
wire reset_B;
wire Iin_d_d27_d1 ;
output Iout2_d_d17_d0 ;
output Iout1_d_d27_d0 ;
output Iout1_d_d10_d0 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d12_d1 ;
wire Iin_d_d23_d1 ;
output Iin_a ;
wire Iout_en_buf_out0 ;
output Iout2_d_d17_d1 ;
output Iout2_d_d18_d1 ;
wire Iin_d_d29_d1 ;
output Iout1_d_d28_d0 ;
wire Iout1_a_B_buf_out0 ;
wire Icond_d_d0_d1 ;
output Iout2_d_d3_d0 ;
output Iout1_d_d23_d1 ;
output Iout2_d_d2_d0 ;
output Iout2_d_d10_d0 ;
output Iout2_d_d24_d0 ;
output Iout1_d_d9_d1 ;
output Iout1_d_d9_d0 ;
output Iout2_d_d29_d0 ;
output Iout2_d_d28_d0 ;
output Iout2_d_d7_d1 ;
output Iout1_d_d26_d1 ;
wire Icond_d_d0_d0 ;
output Iout1_d_d11_d1 ;
output Iout1_d_d13_d0 ;
output Iout1_d_d12_d0 ;
output Iout2_d_d11_d0 ;
output Iout1_d_d7_d1 ;
output Iout1_d_d25_d0 ;
output Iout1_d_d19_d0 ;
output Iout1_d_d0_d0 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d26_d1 ;
output Iout2_d_d22_d0 ;
output Iout1_d_d15_d1 ;
output Iout1_d_d14_d1 ;
wire Iin_d_d25_d0 ;
output Iout1_d_d13_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d7_d1 ;
output Iout1_d_d15_d0 ;
output Iout2_d_d20_d0 ;
output Iout2_d_d4_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d26_d0 ;
output Iout2_d_d28_d1 ;
output Iout2_d_d7_d0 ;
output Iout1_d_d25_d1 ;
wire Iin_d_d4_d1 ;
output Iout2_d_d15_d0 ;
output Iout2_d_d27_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d0 ;
output Iin_v ;
wire Iin_d_d13_d1 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d11_d0 ;
output Iout2_d_d11_d1 ;
wire Iin_d_d24_d0 ;
output Iout1_d_d21_d0 ;
output Iout2_d_d18_d0 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d23_d1 ;
output Iout1_d_d29_d0 ;
output Iout1_d_d16_d0 ;
output Iout2_d_d8_d0 ;
output Iout2_d_d9_d0 ;
output Iout1_d_d4_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d1_d0 ;
output Iout1_d_d18_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d15_d1 ;
output Iout2_d_d25_d0 ;
output Iout1_d_d16_d1 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d5_d1 ;
output Iout2_d_d14_d0 ;
wire I_c_t_buf0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d2_d0 ;
output Iout2_d_d6_d0 ;
wire Iin_d_d8_d0 ;
output Iout1_d_d21_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d15_d0 ;
output Iout1_d_d2_d1 ;
output Iout1_d_d8_d0 ;
wire _in_v ;
wire _reset_BX ;
output Iout2_d_d16_d0 ;
output Iout2_d_d29_d1 ;
wire Iin_d_d18_d0 ;
output Iout1_d_d29_d1 ;
wire _c_v ;
output Iout2_d_d22_d1 ;
wire Iin_d_d10_d0 ;
output Iout2_d_d23_d0 ;
output Iout2_d_d16_d1 ;
wire Iin_d_d9_d0 ;
output Iout1_d_d5_d0 ;
output Iout2_d_d26_d0 ;
wire Iin_d_d3_d1 ;
output Iout2_d_d26_d1 ;
output Iout2_d_d13_d0 ;
output Iout1_d_d17_d0 ;
wire _en ;
wire _out2_a_B ;
output Iout1_d_d19_d1 ;
output Iout1_d_d20_d0 ;
wire Iin_d_d28_d0 ;
output Icond_v ;
wire Iin_d_d5_d0 ;
wire Iin_d_d6_d0 ;
output Iout1_d_d14_d0 ;
wire Iout2_a ;
wire Iin_d_d0_d1 ;
output Iout2_d_d0_d0 ;
wire Iin_d_d21_d0 ;
output Iout1_d_d23_d0 ;
output Iout1_d_d2_d0 ;
output Iout2_d_d9_d1 ;
output Iout2_d_d10_d1 ;
output Iout2_d_d21_d1 ;
wire Iin_d_d24_d1 ;
output Iout1_d_d27_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d4_d0 ;
output Iout1_d_d26_d0 ;
wire Iin_d_d17_d0 ;
output Iout1_d_d3_d1 ;
wire Iin_d_d14_d0 ;
wire Iout2_v ;
output Iout2_d_d2_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d12_d0 ;
output Iout1_d_d24_d1 ;
output Iout1_d_d22_d0 ;
output Iout1_d_d18_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d12_d1 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d3_d1 ;
output Iout2_d_d14_d1 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d7_d0 ;
output Iout1_d_d3_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d10_d1 ;
output Iout2_d_d24_d1 ;
output Iout2_d_d27_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d13_d0 ;
output Iout1_d_d24_d0 ;
output Iout1_d_d6_d0 ;
output Iout2_d_d0_d1 ;
wire Iin_d_d1_d1 ;
output Iout1_d_d22_d1 ;
output Iout1_d_d6_d1 ;
wire Iout2_a_B_buf_out0 ;
output Iout2_d_d19_d1 ;
wire I_c_f_buf0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d19_d0 ;
wire _out_v ;
output Iout2_d_d20_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d27_d0 ;
output Iout1_d_d12_d1 ;
wire _out1_a_B ;
wire Iin_d_d16_d1 ;
output Iout1_d_d17_d1 ;
output Iout2_d_d15_d1 ;
output Iout2_d_d5_d0 ;
wire Iin_d_d16_d0 ;
output Iout1_d_d20_d1 ;
wire Iin_d_d11_d1 ;
output Iout2_d_d19_d0 ;
output Iout2_d_d6_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d28_d1 ;
output Iout1_d_d13_d1 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d7_d1 ;
output Iout2_d_d22_d1 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d11_d1 ;
wire Iin_d_d16_d1 ;
output Iout2_d_d10_d0 ;
output Iout1_d_d25_d1 ;
output Iout1_d_d17_d1 ;
wire Iin_d_d29_d1 ;
wire reset_B;
output Iout2_d_d17_d1 ;
output Iout1_d_d3_d0 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d21_d0 ;
output Iout1_d_d12_d0 ;
wire _reset_BX ;
output Iout2_d_d9_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d25_d0 ;
output Iout1_d_d24_d0 ;
wire Iin_d_d18_d1 ;
output Iout2_d_d22_d0 ;
wire Iin_d_d26_d0 ;
output Iout1_d_d11_d1 ;
output Iout1_d_d28_d0 ;
output Iout1_d_d9_d0 ;
wire Iin_d_d6_d0 ;
output Iout1_d_d0_d1 ;
output Iout1_d_d1_d0 ;
wire _out1_a_B ;
wire _out_v ;
output Iout2_d_d4_d0 ;
wire Iin_d_d7_d0 ;
output Iout2_d_d26_d0 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d12_d1 ;
output Iout2_d_d24_d1 ;
wire Iin_d_d8_d0 ;
output Iout1_d_d10_d1 ;
wire _en ;
wire Iin_d_d9_d1 ;
output Iout2_d_d23_d0 ;
output Iout1_d_d21_d0 ;
wire Iin_d_d7_d1 ;
output Iout2_d_d16_d1 ;
wire Iin_d_d2_d0 ;
output Iout1_d_d8_d0 ;
wire Icond_d_d0_d1 ;
output Iout2_d_d15_d1 ;
wire Iin_d_d11_d0 ;
output Iout1_d_d5_d1 ;
output Iout2_d_d13_d0 ;
output Iout2_d_d20_d0 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d29_d0 ;
output Iout2_d_d6_d0 ;
output Iout2_d_d9_d1 ;
wire Iin_d_d13_d1 ;
output Iout2_d_d25_d1 ;
output Iout2_d_d12_d0 ;
wire Iin_d_d4_d0 ;
output Iout1_d_d22_d0 ;
output Iout1_d_d19_d0 ;
output Iout1_d_d2_d0 ;
wire Iout2_v ;
wire I_reset_BXX0 ;
wire Iout1_v ;
output Iout2_d_d14_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d22_d0 ;
output Iout1_d_d17_d0 ;
output Iout2_d_d27_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d10_d0 ;
output Iout2_d_d19_d0 ;
output Iout1_d_d3_d1 ;
output Iout1_d_d11_d0 ;
wire Iin_d_d29_d0 ;
output Iout2_d_d16_d0 ;
output Iout1_d_d16_d1 ;
output Iout1_d_d14_d1 ;
output Iout1_d_d27_d0 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d15_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d21_d1 ;
output Iout2_d_d28_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d17_d1 ;
output Iout2_d_d8_d0 ;
output Iout2_d_d27_d1 ;
output Iout2_d_d12_d0 ;
output Iout1_d_d14_d0 ;
wire Iin_d_d5_d1 ;
output Iout2_d_d0_d0 ;
output Icond_v ;
wire Iin_d_d28_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d24_d0 ;
output Iout1_d_d22_d1 ;
output Iout2_d_d28_d1 ;
wire Iin_d_d13_d0 ;
output Iout1_d_d28_d1 ;
wire _in_v ;
output Iout2_d_d18_d0 ;
output Iout1_d_d23_d0 ;
output Iout2_d_d20_d1 ;
output Iout1_d_d24_d1 ;
output Iout1_d_d7_d1 ;
wire I_c_f_buf0 ;
wire Iin_d_d5_d0 ;
output Iout1_d_d15_d1 ;
output Iout1_d_d13_d0 ;
output Iout2_d_d3_d0 ;
output Iout1_d_d6_d1 ;
output Iout1_d_d0_d0 ;
wire Iout1_a ;
output Iout2_d_d0_d1 ;
output Iout1_d_d20_d1 ;
output Iout1_d_d1_d1 ;
wire Iin_d_d14_d1 ;
output Iout1_d_d6_d0 ;
output Iout1_d_d5_d0 ;
wire Iout2_a ;
wire Iin_d_d4_d1 ;
output Iout2_d_d13_d1 ;
output Iout2_d_d18_d1 ;
output Iout1_d_d2_d1 ;
output Iout1_d_d18_d0 ;
wire Icond_d_d0_d0 ;
wire Iin_d_d9_d0 ;
output Iout2_d_d11_d0 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d26_d1 ;
output Iout2_d_d17_d0 ;
output Iout1_d_d19_d1 ;
output Iin_a ;
output Iout2_d_d6_d1 ;
output Iout2_d_d10_d1 ;
output Iout1_d_d25_d0 ;
output Iout1_d_d29_d1 ;
output Iout1_d_d9_d1 ;
output Iout2_d_d26_d1 ;
output Iout2_d_d14_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d20_d0 ;
output Iout2_d_d29_d0 ;
output Iout2_d_d2_d1 ;
wire Iin_d_d12_d1 ;
output Iout2_d_d29_d1 ;
wire Iin_d_d15_d0 ;
output Iin_v ;
output Iout2_d_d19_d1 ;
output Iout1_d_d23_d1 ;
output Iout1_d_d26_d0 ;
wire _c_v ;
wire _out2_a_B ;
output Iout2_d_d23_d1 ;
wire Iin_d_d0_d0 ;
output Iout1_d_d20_d0 ;
output Iout1_d_d7_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d19_d1 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d27_d1 ;
output Iout2_d_d2_d0 ;
wire I_c_t_buf0 ;
wire Iin_d_d1_d1 ;
output Iout2_d_d4_d1 ;
output Iout2_d_d21_d0 ;
wire Iin_d_d1_d0 ;
output Iout2_d_d7_d0 ;
output Iout1_d_d15_d0 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d21_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d24_d1 ;
wire Iout2_a_B_buf_out0 ;
output Iout2_d_d5_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d22_d1 ;
output Iout1_d_d10_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d6_d1 ;
wire Iout1_a_B_buf_out0 ;
wire Iout_en_buf_out0 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d24_d0 ;
output Iout2_d_d25_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

392
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0demux_331_4/netlist/verilog.v

@ -199,215 +199,215 @@ module tmpl_0_0dataflow__neuro_0_0demux_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
// -- signals ---
output Iout1_d_d1_d0 ;
wire Iin_d_d26_d1 ;
output Iout2_d_d20_d0 ;
output Iout1_d_d26_d0 ;
wire Iin_d_d15_d0 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d9_d0 ;
wire Iin_d_d29_d1 ;
output Iout1_d_d29_d0 ;
output Iout1_d_d14_d0 ;
wire Iout2_v ;
output Iout1_d_d24_d1 ;
wire Iin_d_d11_d0 ;
output Iout2_d_d29_d0 ;
output Iout2_d_d2_d1 ;
output Iout2_d_d18_d1 ;
output Iout2_d_d17_d1 ;
output Iout2_d_d17_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d30_d1 ;
output Iout2_d_d9_d1 ;
output Iout2_d_d10_d1 ;
output Iout2_d_d13_d0 ;
output Iout2_d_d23_d0 ;
output Icond_v ;
output Iout2_d_d0_d1 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d28_d1 ;
output Iout2_d_d18_d0 ;
output Iout1_d_d22_d1 ;
output Iout1_d_d15_d1 ;
wire Iin_d_d2_d1 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d28_d0 ;
output Iout1_d_d16_d0 ;
output Iout1_d_d12_d0 ;
output Iout1_d_d2_d0 ;
output Iin_v ;
wire Iin_d_d18_d1 ;
output Iout2_d_d13_d1 ;
wire Iin_d_d13_d1 ;
output Iout2_d_d28_d1 ;
output Iout1_d_d5_d1 ;
output Iout2_d_d4_d1 ;
wire Iin_d_d19_d1 ;
output Iout2_d_d11_d0 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d16_d1 ;
output Iout2_d_d21_d1 ;
output Iout1_d_d15_d0 ;
wire Iin_d_d11_d1 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d19_d0 ;
output Iout2_d_d22_d0 ;
wire Iin_d_d29_d0 ;
output Iout1_d_d12_d1 ;
output Iout1_d_d13_d0 ;
output Iin_a ;
wire _out1_a_B ;
wire _in_v ;
wire Iin_d_d6_d0 ;
output Iout1_d_d3_d1 ;
output Iout2_d_d9_d1 ;
output Iout1_d_d19_d1 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d5_d0 ;
output Iout2_d_d5_d1 ;
wire Iin_d_d17_d0 ;
output Iout2_d_d18_d0 ;
output Iout1_d_d6_d1 ;
output Iout1_d_d1_d0 ;
wire Iout2_a ;
wire Icond_d_d0_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d7_d0 ;
output Iout1_d_d28_d1 ;
wire Iin_d_d21_d1 ;
output Iout2_d_d12_d0 ;
output Iout1_d_d25_d1 ;
output Iout1_d_d8_d0 ;
output Iout2_d_d9_d0 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d11_d0 ;
output Iout1_d_d4_d0 ;
wire reset_B;
wire Iin_d_d3_d1 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d28_d0 ;
output Iout2_d_d6_d1 ;
wire Iin_d_d3_d0 ;
output Iout2_d_d2_d0 ;
output Iout2_d_d3_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d25_d0 ;
output Iout1_d_d0_d1 ;
wire Iout1_a_B_buf_out0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d24_d1 ;
output Iout2_d_d10_d0 ;
output Iout1_d_d30_d1 ;
output Iout1_d_d23_d1 ;
output Iout1_d_d21_d0 ;
output Iout2_d_d20_d1 ;
output Iout2_d_d2_d0 ;
output Iout2_d_d4_d0 ;
output Iout1_d_d13_d0 ;
output Iout1_d_d10_d0 ;
output Iout1_d_d9_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d30_d0 ;
output Iout2_d_d28_d1 ;
output Iout2_d_d3_d0 ;
wire Iin_d_d19_d0 ;
output Iout2_d_d22_d1 ;
output Iout2_d_d23_d1 ;
wire Iin_d_d23_d1 ;
output Iout2_d_d0_d0 ;
wire Iin_d_d13_d1 ;
output Iout2_d_d17_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d7_d1 ;
output Iout1_d_d27_d0 ;
output Iout1_d_d23_d0 ;
output Iout1_d_d13_d1 ;
output Iout1_d_d12_d1 ;
wire Iout1_a ;
output Iout2_d_d8_d1 ;
wire I_c_f_buf0 ;
output Iout2_d_d4_d1 ;
output Iout2_d_d6_d0 ;
output Iout2_d_d19_d0 ;
wire Iin_d_d22_d0 ;
output Iout2_d_d25_d0 ;
output Iout1_d_d14_d1 ;
output Iout1_d_d30_d0 ;
output Iout1_d_d29_d0 ;
output Iout1_d_d18_d0 ;
output Iout1_d_d29_d1 ;
output Iout1_d_d0_d1 ;
wire Iin_d_d0_d0 ;
wire Icond_d_d0_d0 ;
output Iout2_d_d7_d1 ;
output Iout2_d_d12_d1 ;
output Iout1_d_d19_d0 ;
output Iin_v ;
output Iout2_d_d0_d1 ;
output Iout2_d_d11_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d12_d0 ;
output Iout2_d_d2_d1 ;
output Iout2_d_d19_d1 ;
output Iout2_d_d29_d1 ;
wire Iin_d_d16_d0 ;
output Iout2_d_d23_d1 ;
output Iout1_d_d2_d1 ;
wire _c_v ;
wire Iout1_v ;
output Iout2_d_d15_d1 ;
wire Iin_d_d15_d1 ;
output Iout2_d_d25_d1 ;
output Iout1_d_d13_d1 ;
wire Iout1_a ;
wire Iin_d_d4_d0 ;
wire _en ;
output Iout2_d_d11_d1 ;
output Iout2_d_d10_d0 ;
output Iout1_d_d21_d0 ;
output Iout2_d_d30_d1 ;
output Iout1_d_d23_d1 ;
output Iout1_d_d18_d0 ;
wire Icond_d_d0_d0 ;
output Iout2_d_d4_d0 ;
wire Iin_d_d24_d0 ;
output Iout1_d_d30_d1 ;
output Iout1_d_d6_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d0_d1 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d22_d1 ;
wire Iin_d_d8_d0 ;
output Iout1_d_d10_d0 ;
wire I_c_f_buf0 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d12_d0 ;
output Iout2_d_d16_d0 ;
output Iout1_d_d19_d0 ;
wire I_c_t_buf0 ;
wire _reset_BX ;
wire Iin_d_d23_d1 ;
wire Iin_d_d24_d1 ;
output Iout1_d_d25_d0 ;
output Iout2_d_d0_d0 ;
output Iout1_d_d3_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d20_d1 ;
output Iout1_d_d19_d1 ;
wire Iin_d_d27_d0 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d11_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d18_d0 ;
output Iout1_d_d0_d0 ;
wire Iin_d_d9_d1 ;
output Iout2_d_d6_d0 ;
output Iout2_d_d26_d0 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d29_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d7_d1 ;
output Iout2_d_d8_d0 ;
output Iout1_d_d27_d1 ;
output Iout2_d_d20_d1 ;
output Iout2_d_d7_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d19_d0 ;
output Iout2_d_d16_d1 ;
output Iout1_d_d20_d1 ;
wire Iout_en_buf_out0 ;
output Iout1_d_d17_d0 ;
wire Iin_d_d28_d0 ;
output Iout2_d_d14_d0 ;
output Iout2_d_d24_d0 ;
output Iout2_d_d25_d0 ;
output Iout1_d_d21_d1 ;
output Iout1_d_d9_d1 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d24_d0 ;
output Iout2_d_d5_d1 ;
output Iout2_d_d7_d1 ;
output Iout1_d_d8_d1 ;
output Iout1_d_d7_d1 ;
output Iout2_d_d30_d0 ;
wire Iin_d_d1_d0 ;
wire _out_v ;
output Iout2_d_d1_d1 ;
output Iout1_d_d20_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d12_d0 ;
output Iout2_d_d27_d0 ;
output Iout1_d_d14_d1 ;
wire _reset_BX ;
wire I_reset_BXX0 ;
wire Iin_d_d14_d1 ;
output Iout2_d_d26_d1 ;
output Iout1_d_d17_d1 ;
output Iout1_d_d6_d0 ;
wire Iin_d_d30_d0 ;
wire _out2_a_B ;
wire Iin_d_d0_d0 ;
wire Iin_d_d2_d0 ;
output Iout1_d_d23_d0 ;
output Iout1_d_d22_d0 ;
wire Iout2_a_B_buf_out0 ;
output Iout2_d_d14_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d4_d0 ;
output Iout2_d_d18_d1 ;
output Iout2_d_d9_d0 ;
wire Iin_d_d15_d0 ;
output Iout1_d_d2_d1 ;
output Iout1_d_d1_d1 ;
output Iout1_d_d3_d0 ;
output Iout1_d_d0_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d5_d1 ;
output Iout2_d_d15_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d7_d0 ;
output Iout2_d_d12_d1 ;
output Iout2_d_d27_d1 ;
output Iout1_d_d27_d0 ;
wire Iin_d_d4_d1 ;
output Iout1_d_d30_d0 ;
output Iout1_d_d5_d0 ;
wire Iin_d_d26_d0 ;
output Iout1_d_d4_d1 ;
wire Iin_d_d1_d1 ;
output Iout2_d_d11_d0 ;
output Iout2_d_d20_d0 ;
output Iout1_d_d21_d1 ;
output Iout1_d_d20_d1 ;
output Iout1_d_d14_d0 ;
output Iout2_d_d16_d1 ;
output Iout1_d_d8_d0 ;
output Iout2_d_d22_d0 ;
output Iout1_d_d15_d0 ;
output Iout2_d_d13_d1 ;
wire Iin_d_d3_d0 ;
output Iout1_d_d22_d0 ;
output Iout2_d_d30_d0 ;
wire Iin_d_d6_d1 ;
output Iout2_d_d10_d1 ;
wire Iin_d_d24_d0 ;
output Iout1_d_d25_d0 ;
output Iout1_d_d20_d0 ;
output Iout1_d_d12_d0 ;
output Iout1_d_d11_d0 ;
output Iout2_d_d26_d0 ;
output Icond_v ;
wire Iout_en_buf_out0 ;
wire Iin_d_d27_d1 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d7_d0 ;
output Iout1_d_d2_d0 ;
wire Iout1_v ;
output Iout1_d_d11_d1 ;
output Iout1_d_d7_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d22_d0 ;
output Iout2_d_d24_d1 ;
wire I_c_t_buf0 ;
output Iout1_d_d27_d1 ;
wire _out1_a_B ;
output Iout2_d_d23_d0 ;
output Iout1_d_d26_d0 ;
output Iout2_d_d27_d0 ;
output Iout2_d_d13_d0 ;
output Iout2_d_d14_d0 ;
output Iout2_d_d6_d1 ;
wire reset_B;
wire Iin_d_d2_d1 ;
wire Iin_d_d16_d1 ;
output Iout2_d_d8_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d29_d0 ;
wire _c_v ;
wire Iin_d_d6_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d26_d1 ;
output Iout2_d_d29_d0 ;
output Iout1_d_d24_d1 ;
output Iout2_d_d30_d1 ;
output Iout1_d_d28_d0 ;
wire Iout2_v ;
output Iout2_d_d17_d0 ;
output Iout2_d_d3_d1 ;
output Iout2_d_d1_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d11_d0 ;
output Iout1_d_d7_d0 ;
output Iout1_d_d6_d0 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d12_d1 ;
output Iout2_d_d27_d1 ;
output Iout1_d_d15_d1 ;
wire _out_v ;
wire Iin_d_d8_d1 ;
wire Iin_d_d25_d1 ;
output Iout2_d_d16_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d26_d0 ;
output Iout1_d_d16_d1 ;
wire Iin_d_d22_d1 ;
output Iout2_d_d26_d1 ;
wire Iout1_a_B_buf_out0 ;
output Iout2_d_d28_d0 ;
wire _en ;
wire Iout2_a_B_buf_out0 ;
output Iout2_d_d24_d1 ;
output Iout1_d_d22_d1 ;
wire Icond_d_d0_d1 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d21_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d9_d0 ;
output Iout2_d_d24_d0 ;
output Iin_a ;
wire Iin_d_d14_d0 ;
output Iout1_d_d9_d1 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d14_d1 ;
output Iout2_d_d15_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d4_d1 ;
output Iout1_d_d17_d1 ;
output Iout1_d_d5_d1 ;
output Iout1_d_d3_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
output Iout2_d_d25_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d29_d1 ;
output Iout1_d_d17_d0 ;
wire _out2_a_B ;
output Iout1_d_d28_d1 ;
output Iout1_d_d18_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

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test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4/netlist/verilog.v

@ -135,144 +135,144 @@ module tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4(Iin_d_d0_d0 , Iin_d_d
input cond;
// -- signals ---
output Iout_d_d28_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d9_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d16_d1 ;
wire Iin_d_d27_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d22_d1 ;
wire Ior2_b ;
output Iout_d_d29_d0 ;
output Iout_d_d29_d1 ;
wire Ior2_y ;
wire Iout_a ;
wire Iin_d_d5_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d20_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d_d22_d0 ;
output Iout_d_d15_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d11_d0 ;
wire Ivt_out ;
output Iout_d_d11_d1 ;
wire Iin_d_d24_d1 ;
wire _drop ;
output Iout_d_d19_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d23_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d12_d1 ;
output Iin_v ;
wire Iin_d_d2_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d30_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d7_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d_d16_d1 ;
output Iout_d_d21_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d22_d0 ;
wire Iand_f31_b ;
output Iout_d_d7_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d8_d1 ;
output Iout_d_d11_d0 ;
output Iout_d_d28_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d14_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d10_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d8_d0 ;
output Iout_d_d24_d0 ;
wire _in_vX ;
wire Iin_d_d20_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d31_d1 ;
wire Iin_d_d18_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d31_d1 ;
output Iout_d_d20_d0 ;
output Iout_d_d6_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d24_d1 ;
wire cond;
output Iout_d_d2_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d26_d0 ;
output Iout_d_d0_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d31_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d22_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d24_d0 ;
output Iout_d_d12_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d15_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d12_d0 ;
output Iin_v ;
output Iout_d_d21_d0 ;
output Iout_d_d23_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d10_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d29_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d11_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d8_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d11_d1 ;
wire Ivt_out ;
wire Iin_d_d25_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d22_d1 ;
wire Iout_a ;
wire Iin_d_d17_d0 ;
output Iout_d_d31_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d7_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d26_d1 ;
wire _in_vX ;
output Iout_d_d4_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d18_d1 ;
output Iout_d_d30_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d7_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d_d23_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d31_d0 ;
output Iout_d_d22_d1 ;
wire Iand_f31_b ;
wire Iin_d_d5_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d27_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d20_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d31_d1 ;
wire Iin_d_d14_d0 ;
output Iout_d_d17_d0 ;
wire Ior2_b ;
wire Iin_d_d15_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d17_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d31_d0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d24_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d14_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d30_d0 ;
output Iin_a ;
wire Iin_d_d11_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d16_d0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d19_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d13_d1 ;
wire Iin_d_d21_d1 ;
output Iin_a ;
output Iout_d_d9_d0 ;
wire Ior2_y ;
output Iout_d_d27_d0 ;
wire Iin_d_d19_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d_d17_d1 ;
wire cond;
wire Iin_d_d2_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d24_d0 ;
wire _drop ;
wire Iin_d_d6_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d16_d0 ;
wire Iin_d_d31_d0 ;
output Iout_d_d9_d1 ;
// --- instances
BUF_X4 Iin_v_buf (.y(_in_vX), .a(Ivt_out ), .vdd(vdd), .vss(vss));

22
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4/netlist/verilog.v

@ -16,24 +16,24 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4(Iin0 , Iin1 , Iin2 ,
input Isupply_vss ;
// -- signals ---
wire I_inX4 ;
wire Iin5 ;
wire Isupply_vss ;
wire I_inX3 ;
output Iout_d1_d0 ;
output Iout_d2_d1 ;
wire I_inX2 ;
wire I_inX1 ;
wire Iin1 ;
wire I_inX0 ;
wire Iin2 ;
wire I_inX1 ;
output Iout_d2_d0 ;
wire Isupply_vss ;
wire I_inX3 ;
wire I_inX5 ;
wire Iin4 ;
wire Iin2 ;
wire I_inX2 ;
wire Iin5 ;
wire Iin3 ;
output Iout_d0_d0 ;
output Iout_d1_d0 ;
wire I_inX4 ;
wire Iin0 ;
wire I_inX5 ;
output Iout_d2_d1 ;
output Iout_d1_d1 ;
output Iout_d2_d0 ;
output Iout_d0_d1 ;
// --- instances

68
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4/netlist/verilog.v

@ -27,45 +27,45 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4(Iin0 , Iin1 , Iin2
input Isupply_vss ;
// -- signals ---
wire I_inX13 ;
output Iout_d0_d0 ;
output Iout_d0_d1 ;
wire I_inX8 ;
wire I_inX9 ;
output Iout_d1_d0 ;
wire I_inX0 ;
wire I_inX11 ;
wire Iin1 ;
wire Iin9 ;
wire Iin6 ;
wire I_inX1 ;
wire Iin3 ;
wire Iin2 ;
wire Iin10 ;
output Iout_d3_d0 ;
wire I_inX4 ;
wire I_inX5 ;
wire Iin4 ;
wire I_inX12 ;
wire I_inX2 ;
wire I_inX3 ;
wire Iin7 ;
wire I_inX10 ;
wire I_inX7 ;
wire Iin0 ;
output Iout_d1_d1 ;
output Iout_d3_d1 ;
output Iout_d2_d1 ;
wire Iin12 ;
wire Isupply_vss ;
wire I_inX0 ;
wire I_inX9 ;
wire I_inX3 ;
wire Iin6 ;
wire I_inX8 ;
wire I_inX6 ;
output Iout_d2_d0 ;
wire Iin0 ;
wire I_inX5 ;
wire I_inX1 ;
output Iout_d0_d0 ;
wire Iin1 ;
wire Iin13 ;
wire I_inX14 ;
wire Iin11 ;
wire Iin14 ;
output Iout_d2_d0 ;
wire I_inX6 ;
wire Iin8 ;
wire I_inX11 ;
output Iout_d3_d0 ;
wire Iin2 ;
wire Iin5 ;
wire I_inX4 ;
wire Iin10 ;
wire Iin9 ;
wire Iin4 ;
wire I_inX2 ;
output Iout_d0_d1 ;
output Iout_d3_d1 ;
wire Iin11 ;
wire I_inX12 ;
wire I_inX10 ;
wire I_inX13 ;
wire Iin14 ;
wire Iin8 ;
wire Iin12 ;
wire Iin3 ;
output Iout_d1_d0 ;
wire I_inX7 ;
output Iout_d2_d1 ;
output Iout_d1_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (I_inX7 ), .Iin4 (I_inX9 ), .Iin5 (I_inX11 ), .Iin6 (I_inX13 ), .Iin7 (Isupply_vss ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));

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test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4/netlist/verilog.v

@ -121,124 +121,124 @@ module tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4(Isynapses0_d_d0 , I
input Ineuron_a ;
// -- signals ---
output Isynapses15_a ;
output Isynapses12_a ;
output Isynapses6_a ;
wire Isynapses32_d_d0 ;
output Isynapses31_a ;
wire Isynapses29_d_d0 ;
output Isynapses27_a ;
wire Isynapses49_d_d0 ;
wire Isynapses43_d_d0 ;
wire Isynapses25_d_d0 ;
wire Isynapses55_d_d0 ;
wire Isynapses47_d_d0 ;
output Isynapses38_a ;
output Isynapses57_a ;
wire Isynapses56_d_d0 ;
wire Isynapses52_d_d0 ;
wire Isynapses33_d_d0 ;
wire Isynapses19_d_d0 ;
wire Isynapses3_d_d0 ;
output Isynapses45_a ;
output Isynapses43_a ;
wire Isynapses38_d_d0 ;
wire Isynapses1_d_d0 ;
wire Isynapses11_d_d0 ;
wire Isynapses0_d_d0 ;
wire Isynapses15_d_d0 ;
wire Isynapses9_d_d0 ;
wire Isynapses6_d_d0 ;
output Isynapses23_a ;
output Isynapses21_a ;
wire Isynapses14_d_d0 ;
output Isynapses54_a ;
wire Isynapses48_d_d0 ;
output Isynapses41_a ;
output Isynapses32_a ;
wire Isynapses26_d_d0 ;
output Isynapses10_a ;
output Isynapses1_a ;
output Isynapses48_a ;
output Isynapses26_a ;
wire Isynapses16_d_d0 ;
wire Isynapses10_d_d0 ;
output Isynapses53_a ;
output Isynapses56_a ;
wire Isynapses54_d_d0 ;
output Isynapses51_a ;
output Isynapses35_a ;
output Isynapses34_a ;
wire Isynapses24_d_d0 ;
output Isynapses22_a ;
output Isynapses20_a ;
wire Isynapses17_d_d0 ;
wire Isynapses27_d_d0 ;
output Isynapses19_a ;
output Isynapses13_a ;
output Isynapses9_a ;
output Isynapses8_a ;
wire Isynapses30_d_d0 ;
wire Isynapses39_d_d0 ;
output Isynapses39_a ;
output Isynapses36_a ;
output Isynapses5_a ;
output Isynapses24_a ;
wire Isynapses22_d_d0 ;
wire Isynapses12_d_d0 ;
wire Isynapses53_d_d0 ;
wire Isynapses45_d_d0 ;
wire Isynapses41_d_d0 ;
output Isynapses18_a ;
wire Isynapses31_d_d0 ;
wire Isynapses21_d_d0 ;
wire Isynapses5_d_d0 ;
output Isynapses4_a ;
wire Isynapses50_d_d0 ;
output Isynapses29_a ;
wire Isynapses13_d_d0 ;
output Isynapses37_a ;
output Isynapses46_a ;
output Isynapses14_a ;
output Isynapses3_a ;
output Isynapses33_a ;
output Isynapses16_a ;
output Isynapses2_a ;
output Isynapses50_a ;
output Isynapses49_a ;
wire Isynapses44_d_d0 ;
wire Isynapses42_d_d0 ;
wire Isynapses26_d_d0 ;
wire Isynapses23_d_d0 ;
wire Isynapses4_d_d0 ;
wire Isynapses2_d_d0 ;
wire Isynapses57_d_d0 ;
wire Isynapses20_d_d0 ;
output Isynapses17_a ;
output Isynapses55_a ;
wire Isynapses35_d_d0 ;
wire Isynapses34_d_d0 ;
wire Isynapses28_d_d0 ;
output Isynapses25_a ;
output Isynapses44_a ;
output Isynapses42_a ;
output Isynapses30_a ;
wire Isynapses18_d_d0 ;
wire Isynapses7_d_d0 ;
output Isynapses52_a ;
wire Isynapses36_d_d0 ;
output Isynapses28_a ;
output Isynapses11_a ;
output Ineuron_d_d0 ;
wire Ineuron_a ;
wire Isynapses37_d_d0 ;
output Isynapses0_a ;
wire Isynapses51_d_d0 ;
output Isynapses47_a ;
wire Isynapses46_d_d0 ;
wire Isynapses12_d_d0 ;
wire Isynapses6_d_d0 ;
output Isynapses1_a ;
wire Isynapses47_d_d0 ;
wire Isynapses25_d_d0 ;
wire Isynapses40_d_d0 ;
wire Isynapses17_d_d0 ;
output Isynapses10_a ;
output Isynapses9_a ;
wire Isynapses42_d_d0 ;
wire Isynapses32_d_d0 ;
wire Isynapses18_d_d0 ;
output Isynapses42_a ;
output Isynapses37_a ;
output Isynapses33_a ;
wire Isynapses31_d_d0 ;
output Isynapses54_a ;
output Isynapses52_a ;
output Isynapses48_a ;
output Isynapses57_a ;
wire Isynapses51_d_d0 ;
wire Isynapses48_d_d0 ;
output Isynapses20_a ;
output Isynapses4_a ;
wire Isynapses1_d_d0 ;
wire Isynapses35_d_d0 ;
wire Isynapses33_d_d0 ;
output Isynapses26_a ;
wire Isynapses15_d_d0 ;
output Isynapses8_a ;
wire Isynapses56_d_d0 ;
wire Isynapses49_d_d0 ;
output Isynapses11_a ;
wire Isynapses2_d_d0 ;
wire Ineuron_a ;
output Isynapses56_a ;
output Isynapses40_a ;
wire Isynapses19_d_d0 ;
wire Isynapses0_d_d0 ;
wire Isynapses46_d_d0 ;
output Isynapses23_a ;
output Isynapses22_a ;
wire Isynapses10_d_d0 ;
output Isynapses44_a ;
output Isynapses5_a ;
wire Isynapses38_d_d0 ;
wire Isynapses20_d_d0 ;
output Isynapses15_a ;
wire Isynapses11_d_d0 ;
output Isynapses53_a ;
wire Isynapses41_d_d0 ;
output Isynapses28_a ;
wire Isynapses13_d_d0 ;
output Isynapses21_a ;
output Isynapses17_a ;
output Ineuron_d_d0 ;
wire Isynapses30_d_d0 ;
wire Isynapses3_d_d0 ;
output Isynapses0_a ;
output Isynapses51_a ;
wire Isynapses37_d_d0 ;
wire Isynapses55_d_d0 ;
output Isynapses46_a ;
output Isynapses38_a ;
output Isynapses3_a ;
wire Isynapses36_d_d0 ;
wire Isynapses21_d_d0 ;
output Isynapses50_a ;
wire Isynapses28_d_d0 ;
output Isynapses13_a ;
output Isynapses6_a ;
output Isynapses49_a ;
output Isynapses45_a ;
output Isynapses25_a ;
wire Isynapses53_d_d0 ;
wire Isynapses39_d_d0 ;
output Isynapses36_a ;
output Isynapses18_a ;
output Isynapses32_a ;
wire Isynapses4_d_d0 ;
output Isynapses30_a ;
wire Isynapses16_d_d0 ;
wire Isynapses54_d_d0 ;
output Isynapses29_a ;
wire Isynapses8_d_d0 ;
wire Isynapses43_d_d0 ;
output Isynapses27_a ;
wire Isynapses14_d_d0 ;
output Isynapses14_a ;
wire Isynapses44_d_d0 ;
wire Isynapses24_d_d0 ;
output Isynapses7_a ;
wire Isynapses5_d_d0 ;
wire Isynapses57_d_d0 ;
wire Isynapses45_d_d0 ;
output Isynapses43_a ;
output Isynapses41_a ;
output Isynapses31_a ;
wire Isynapses22_d_d0 ;
output Isynapses16_a ;
output Isynapses12_a ;
wire Isynapses52_d_d0 ;
output Isynapses39_a ;
output Isynapses19_a ;
wire Isynapses7_d_d0 ;
output Isynapses2_a ;
output Isynapses55_a ;
output Isynapses47_a ;
wire Isynapses50_d_d0 ;
output Isynapses35_a ;
wire Isynapses34_d_d0 ;
wire Isynapses29_d_d0 ;
wire Isynapses27_d_d0 ;
output Isynapses24_a ;
wire Isynapses9_d_d0 ;
// --- instances
AND2_X1 Iands0 (.y(Isynapses0_a ), .a(Ineuron_a ), .b(Isynapses0_d_d0 ), .vdd(vdd), .vss(vss));

21210
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dummy__neuron__core_358_790_715_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4/netlist/master.tag Normal file

@ -0,0 +1,2 @@
-- Master.tag File, Rev:1.0
verilog.v

266
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4/netlist/verilog.v Normal file

@ -0,0 +1,266 @@
module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4(Iinx0_d_d0 , Iinx0_a , Iinx1_d_d0 , Iinx1_a , Iinx2_d_d0 , Iinx2_a , Iinx3_d_d0 , Iinx3_a , Iinx4_d_d0 , Iinx4_a , Iinx5_d_d0 , Iinx5_a , Iinx6_d_d0 , Iinx6_a , Iinx7_d_d0 , Iinx7_a , Iinx8_d_d0 , Iinx8_a , Iinx9_d_d0 , Iinx9_a , Iinx10_d_d0 , Iinx10_a , Iinx11_d_d0 , Iinx11_a , Iinx12_d_d0 , Iinx12_a , Iinx13_d_d0 , Iinx13_a , Iinx14_d_d0 , Iinx14_a , Iiny0_d_d0 , Iiny0_a , Iiny1_d_d0 , Iiny1_a , Iiny2_d_d0 , Iiny2_a , Iiny3_d_d0 , Iiny3_a , Iiny4_d_d0 , Iiny4_a , Iiny5_d_d0 , Iiny5_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , Ito_pd_x0_d_d0 , Ito_pd_x0_a , Ito_pd_x1_d_d0 , Ito_pd_x1_a , Ito_pd_x2_d_d0 , Ito_pd_x2_a , Ito_pd_x3_d_d0 , Ito_pd_x3_a , Ito_pd_x4_d_d0 , Ito_pd_x4_a , Ito_pd_x5_d_d0 , Ito_pd_x5_a , Ito_pd_x6_d_d0 , Ito_pd_x6_a , Ito_pd_x7_d_d0 , Ito_pd_x7_a , Ito_pd_x8_d_d0 , Ito_pd_x8_a , Ito_pd_x9_d_d0 , Ito_pd_x9_a , Ito_pd_x10_d_d0 , Ito_pd_x10_a , Ito_pd_x11_d_d0 , Ito_pd_x11_a , Ito_pd_x12_d_d0 , Ito_pd_x12_a , Ito_pd_x13_d_d0 , Ito_pd_x13_a , Ito_pd_x14_d_d0 , Ito_pd_x14_a , Ito_pd_y0_d_d0 , Ito_pd_y0_a , Ito_pd_y1_d_d0 , Ito_pd_y1_a , Ito_pd_y2_d_d0 , Ito_pd_y2_a , Ito_pd_y3_d_d0 , Ito_pd_y3_a , Ito_pd_y4_d_d0 , Ito_pd_y4_a , Ito_pd_y5_d_d0 , Ito_pd_y5_a , Isupply_vss , reset_B, vdd, vss);
input vdd;
input vss;
input Iinx0_d_d0 ;
input Iinx1_d_d0 ;
input Iinx2_d_d0 ;
input Iinx3_d_d0 ;
input Iinx4_d_d0 ;
input Iinx5_d_d0 ;
input Iinx6_d_d0 ;
input Iinx7_d_d0 ;
input Iinx8_d_d0 ;
input Iinx9_d_d0 ;
input Iinx10_d_d0 ;
input Iinx11_d_d0 ;
input Iinx12_d_d0 ;
input Iinx13_d_d0 ;
input Iinx14_d_d0 ;
input Iiny0_d_d0 ;
input Iiny1_d_d0 ;
input Iiny2_d_d0 ;
input Iiny3_d_d0 ;
input Iiny4_d_d0 ;
input Iiny5_d_d0 ;
input Iout_a ;
input Iout_v ;
input Ito_pd_x0_a ;
input Ito_pd_x1_a ;
input Ito_pd_x2_a ;
input Ito_pd_x3_a ;
input Ito_pd_x4_a ;
input Ito_pd_x5_a ;
input Ito_pd_x6_a ;
input Ito_pd_x7_a ;
input Ito_pd_x8_a ;
input Ito_pd_x9_a ;
input Ito_pd_x10_a ;
input Ito_pd_x11_a ;
input Ito_pd_x12_a ;
input Ito_pd_x13_a ;
input Ito_pd_x14_a ;
input Ito_pd_y0_a ;
input Ito_pd_y1_a ;
input Ito_pd_y2_a ;
input Ito_pd_y3_a ;
input Ito_pd_y4_a ;
input Ito_pd_y5_a ;
input Isupply_vss ;
input reset_B;
// -- signals ---
wire Ito_pd_y3_a ;
output Ito_pd_y0_d_d0 ;
wire Iiny2_d_d0 ;
wire Ito_pd_y1_a ;
wire IXenc_out_d1_d0 ;
wire Iinv_buf_a ;
wire Iinx10_d_d0 ;
wire Iinx1_d_d0 ;
output Iiny2_a ;
output Iout_d_d6_d0 ;
output Ito_pd_y3_d_d0 ;
wire Ito_pd_x11_a ;
wire Isupply_vss ;
wire IXenc_out_d2_d1 ;
output Iinx9_a ;
wire Iinx0_d_d0 ;
output Ito_pd_y5_d_d0 ;
wire Iinx4_d_d0 ;
output Ito_pd_y2_d_d0 ;
output Ito_pd_x12_d_d0 ;
output Ito_pd_x11_d_d0 ;
output Ito_pd_x10_d_d0 ;
wire IXenc_out_d3_d1 ;
wire Iinx5_d_d0 ;
wire Ibuf_in_v ;
wire IYenc_out_d2_d0 ;
output Iinx14_a ;
output Iinx12_a ;
wire Iinx2_d_d0 ;
output Iinx5_a ;
output Iiny5_a ;
output Iiny1_a ;
output Iiny0_a ;
output Ito_pd_x3_d_d0 ;
output Iout_d_d3_d1 ;
wire Ito_pd_x7_a ;
output Iinx13_a ;
wire Iout_a ;
output Iout_d_d6_d1 ;
wire Ito_pd_x14_a ;
output Ito_pd_x0_d_d0 ;
wire Iinx9_d_d0 ;
output Iinx0_a ;
output Iout_d_d0_d1 ;
output Ito_pd_y1_d_d0 ;
wire Ito_pd_x12_a ;
wire Ito_pd_x10_a ;
output Iinx8_a ;
wire Ito_pd_y5_a ;
wire Ipd_y5_reset_B ;
wire Iinx11_d_d0 ;
output Ito_pd_x7_d_d0 ;
wire IXenc_out_d0_d0 ;
output Ito_pd_x13_d_d0 ;
wire Ito_pd_x3_a ;
wire _r_y ;
output Iout_d_d3_d0 ;
wire IXenc_out_d2_d0 ;
wire _a_y ;
wire Iinx7_d_d0 ;
output Iinx4_a ;
output Iinx1_a ;
wire Iiny0_d_d0 ;
wire Ito_pd_x9_a ;
wire Ia_x_Cel_c1 ;
output Iout_d_d2_d1 ;
wire IYenc_out_d1_d1 ;
output Iinx7_a ;
output Iinx2_a ;
output Iiny4_a ;
wire IYenc_out_d2_d1 ;
wire Ito_pd_y4_a ;
wire _r_x ;
output Iinx3_a ;
output Iiny3_a ;
output Iout_d_d4_d1 ;
wire IXenc_out_d3_d0 ;
wire Iinx6_d_d0 ;
wire Iiny3_d_d0 ;
wire IYenc_out_d0_d0 ;
wire Ito_pd_y0_a ;
wire _a_x ;
wire Ito_pd_y2_a ;
wire Ito_pd_x0_a ;
wire reset_B;
wire Ito_pd_x5_a ;
wire IXenc_out_d1_d1 ;
wire Iinx14_d_d0 ;
output Iinx11_a ;
output Iinx10_a ;
wire Iinx8_d_d0 ;
output Iout_d_d4_d0 ;
wire Iiny4_d_d0 ;
output Iout_d_d5_d0 ;
wire Ito_pd_x13_a ;
wire Ito_pd_x8_a ;
output Ito_pd_x6_d_d0 ;
output Ito_pd_x2_d_d0 ;
wire Ito_pd_x1_a ;
wire Iinx3_d_d0 ;
wire Iout_v ;
output Iout_d_d5_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d1_d0 ;
output Ito_pd_x9_d_d0 ;
wire Iinx13_d_d0 ;
output Iinx6_a ;
wire Iiny5_d_d0 ;
output Iout_d_d1_d1 ;
output Ito_pd_x14_d_d0 ;
output Ito_pd_x8_d_d0 ;
output Ito_pd_x1_d_d0 ;
wire IXenc_out_d0_d1 ;
wire Iiny1_d_d0 ;
output Iout_d_d0_d0 ;
wire IYenc_out_d1_d0 ;
wire IYenc_out_d0_d1 ;
output Ito_pd_x4_d_d0 ;
wire Ito_pd_x2_a ;
wire Iinx12_d_d0 ;
wire Ito_pd_x4_a ;
wire Ipd_x14_reset_B ;
output Ito_pd_y4_d_d0 ;
wire Ito_pd_x6_a ;
output Ito_pd_x5_d_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbtree_315_4 IXarb (.Iin0_d_d0 (Iinx0_d_d0 ), .Iin0_a (Iinx0_a ), .Iin1_d_d0 (Iinx1_d_d0 ), .Iin1_a (Iinx1_a ), .Iin2_d_d0 (Iinx2_d_d0 ), .Iin2_a (Iinx2_a ), .Iin3_d_d0 (Iinx3_d_d0 ), .Iin3_a (Iinx3_a ), .Iin4_d_d0 (Iinx4_d_d0 ), .Iin4_a (Iinx4_a ), .Iin5_d_d0 (Iinx5_d_d0 ), .Iin5_a (Iinx5_a ), .Iin6_d_d0 (Iinx6_d_d0 ), .Iin6_a (Iinx6_a ), .Iin7_d_d0 (Iinx7_d_d0 ), .Iin7_a (Iinx7_a ), .Iin8_d_d0 (Iinx8_d_d0 ), .Iin8_a (Iinx8_a ), .Iin9_d_d0 (Iinx9_d_d0 ), .Iin9_a (Iinx9_a ), .Iin10_d_d0 (Iinx10_d_d0 ), .Iin10_a (Iinx10_a ), .Iin11_d_d0 (Iinx11_d_d0 ), .Iin11_a (Iinx11_a ), .Iin12_d_d0 (Iinx12_d_d0 ), .Iin12_a (Iinx12_a ), .Iin13_d_d0 (Iinx13_d_d0 ), .Iin13_a (Iinx13_a ), .Iin14_d_d0 (Iinx14_d_d0 ), .Iin14_a (Iinx14_a ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));
INV_X2 Iinv_buf (.y(Ia_x_Cel_c1 ), .a(Iinv_buf_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_pd_x (.in(reset_B), .Iout0 (Ipd_x14_reset_B ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_y_Cel (.y(_a_y), .c1(Ia_x_Cel_c1 ), .c2(_r_y), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4 IXenc (.Iin0 (Iinx0_a ), .Iin1 (Iinx1_a ), .Iin2 (Iinx2_a ), .Iin3 (Iinx3_a ), .Iin4 (Iinx4_a ), .Iin5 (Iinx5_a ), .Iin6 (Iinx6_a ), .Iin7 (Iinx7_a ), .Iin8 (Iinx8_a ), .Iin9 (Iinx9_a ), .Iin10 (Iinx10_a ), .Iin11 (Iinx11_a ), .Iin12 (Iinx12_a ), .Iin13 (Iinx13_a ), .Iin14 (Iinx14_a ), .Iout_d0_d0 (IXenc_out_d0_d0 ), .Iout_d0_d1 (IXenc_out_d0_d1 ), .Iout_d1_d0 (IXenc_out_d1_d0 ), .Iout_d1_d1 (IXenc_out_d1_d1 ), .Iout_d2_d0 (IXenc_out_d2_d0 ), .Iout_d2_d1 (IXenc_out_d2_d1 ), .Iout_d3_d0 (IXenc_out_d3_d0 ), .Iout_d3_d1 (IXenc_out_d3_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x0 (.in(Ito_pd_x0_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x1 (.in(Ito_pd_x1_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x2 (.in(Ito_pd_x2_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x3 (.in(Ito_pd_x3_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x4 (.in(Ito_pd_x4_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x5 (.in(Ito_pd_x5_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x6 (.in(Ito_pd_x6_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x7 (.in(Ito_pd_x7_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x8 (.in(Ito_pd_x8_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x9 (.in(Ito_pd_x9_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x10 (.in(Ito_pd_x10_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x11 (.in(Ito_pd_x11_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x12 (.in(Ito_pd_x12_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x13 (.in(Ito_pd_x13_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x14 (.in(Ito_pd_x14_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y0 (.in(Ito_pd_y0_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y1 (.in(Ito_pd_y1_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y2 (.in(Ito_pd_y2_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y3 (.in(Ito_pd_y3_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y4 (.in(Ito_pd_y4_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y5 (.in(Ito_pd_y5_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ibuf (.Iin_d_d0_d0 (IXenc_out_d0_d0 ), .Iin_d_d0_d1 (IXenc_out_d0_d1 ), .Iin_d_d1_d0 (IXenc_out_d1_d0 ), .Iin_d_d1_d1 (IXenc_out_d1_d1 ), .Iin_d_d2_d0 (IXenc_out_d2_d0 ), .Iin_d_d2_d1 (IXenc_out_d2_d1 ), .Iin_d_d3_d0 (IXenc_out_d3_d0 ), .Iin_d_d3_d1 (IXenc_out_d3_d1 ), .Iin_d_d4_d0 (IYenc_out_d0_d0 ), .Iin_d_d4_d1 (IYenc_out_d0_d1 ), .Iin_d_d5_d0 (IYenc_out_d1_d0 ), .Iin_d_d5_d1 (IYenc_out_d1_d1 ), .Iin_d_d6_d0 (IYenc_out_d2_d0 ), .Iin_d_d6_d1 (IYenc_out_d2_d1 ), .Iin_a (Iinv_buf_a ), .Iin_v (Ibuf_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbtree_36_4 IYarb (.Iin0_d_d0 (Iiny0_d_d0 ), .Iin0_a (Iiny0_a ), .Iin1_d_d0 (Iiny1_d_d0 ), .Iin1_a (Iiny1_a ), .Iin2_d_d0 (Iiny2_d_d0 ), .Iin2_a (Iiny2_a ), .Iin3_d_d0 (Iiny3_d_d0 ), .Iin3_a (Iiny3_a ), .Iin4_d_d0 (Iiny4_d_d0 ), .Iin4_a (Iiny4_a ), .Iin5_d_d0 (Iiny5_d_d0 ), .Iin5_a (Iiny5_a ), .Iout_d_d0 (_r_y), .Iout_a (_a_y), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4 IYenc (.Iin0 (Iiny0_a ), .Iin1 (Iiny1_a ), .Iin2 (Iiny2_a ), .Iin3 (Iiny3_a ), .Iin4 (Iiny4_a ), .Iin5 (Iiny5_a ), .Iout_d0_d0 (IYenc_out_d0_d0 ), .Iout_d0_d1 (IYenc_out_d0_d1 ), .Iout_d1_d0 (IYenc_out_d1_d0 ), .Iout_d1_d1 (IYenc_out_d1_d1 ), .Iout_d2_d0 (IYenc_out_d2_d0 ), .Iout_d2_d1 (IYenc_out_d2_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_x_Cel (.y(_a_x), .c1(Ia_x_Cel_c1 ), .c2(_r_x), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Irsb_pd_y (.in(reset_B), .Iout0 (Ipd_y5_reset_B ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_313_75_4/netlist/master.tag Normal file

@ -0,0 +1,2 @@
-- Master.tag File, Rev:1.0
verilog.v

243
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_313_75_4/netlist/verilog.v Normal file

@ -0,0 +1,243 @@
module tmpl_0_0dataflow__neuro_0_0fifo_313_75_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
output Iout_d_d9_d1 ;
wire Iin_d_d2_d1 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Ififo_element4_in_d_d1_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element4_in_d_d8_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d5_d0 ;
wire Ififo_element4_in_d_d6_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element4_in_d_d1_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Iin_d_d4_d1 ;
output Iin_a ;
wire Ififo_element4_in_d_d5_d1 ;
wire Iin_d_d6_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Ififo_element3_in_d_d1_d1 ;
wire Ififo_element3_in_d_d9_d0 ;
wire Iin_d_d12_d1 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
output Iout_d_d7_d1 ;
wire Ififo_element1_in_a ;
wire Ififo_element2_in_d_d2_d1 ;
output Iout_d_d5_d1 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element4_in_d_d0_d1 ;
wire Ififo_element4_in_d_d11_d1 ;
wire Iin_d_d11_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
output Iout_d_d3_d0 ;
output Iin_v ;
wire Ififo_element4_in_d_d7_d1 ;
output Iout_d_d0_d0 ;
wire Ififo_element3_in_d_d10_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d1_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element3_in_d_d2_d1 ;
wire Ififo_element3_in_d_d8_d0 ;
wire Iout_a ;
wire Ififo_element1_in_d_d8_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Iin_d_d11_d1 ;
wire Ififo_element4_in_d_d2_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element3_in_a ;
wire Iin_d_d0_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
wire I_reset_BXX4 ;
wire Iin_d_d7_d0 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Iin_d_d12_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
output Iout_d_d11_d0 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element3_in_d_d6_d1 ;
output Iout_d_d4_d1 ;
wire Iin_d_d9_d0 ;
wire Ififo_element2_in_a ;
wire Iout_v ;
wire Ififo_element3_in_d_d8_d1 ;
wire Ififo_element3_in_d_d4_d1 ;
wire Ififo_element3_in_d_d5_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
output Iout_d_d10_d0 ;
wire Ififo_element4_in_d_d12_d0 ;
wire Iin_d_d8_d0 ;
wire Ififo_element3_in_d_d3_d1 ;
wire Iin_d_d5_d1 ;
wire Ififo_element3_in_d_d11_d0 ;
wire Ififo_element4_in_d_d5_d0 ;
wire Ififo_element4_in_d_d10_d1 ;
wire Iin_d_d8_d1 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element3_in_d_d12_d1 ;
wire Ififo_element4_in_d_d9_d0 ;
wire Ififo_element4_in_d_d8_d1 ;
wire Iin_d_d4_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element3_in_v ;
wire Ififo_element4_in_d_d6_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d1_d0 ;
wire Ififo_element4_in_d_d12_d1 ;
wire Ififo_element2_in_d_d7_d1 ;
output Iout_d_d12_d1 ;
wire Ififo_element4_in_v ;
wire Ififo_element3_in_d_d2_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d10_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element4_in_d_d2_d0 ;
wire Ififo_element3_in_d_d11_d1 ;
wire Ififo_element4_in_a ;
wire Iin_d_d6_d0 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element2_in_v ;
wire Ififo_element3_in_d_d5_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element3_in_d_d4_d0 ;
wire Ififo_element3_in_d_d0_d0 ;
wire Ififo_element3_in_d_d10_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Ififo_element3_in_d_d7_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d2_d1 ;
wire _reset_BX ;
wire Iin_d_d9_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_v ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
output Iout_d_d7_d0 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element3_in_d_d6_d0 ;
wire Ififo_element3_in_d_d7_d0 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element4_in_d_d3_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element4_in_d_d10_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element3_in_d_d12_d0 ;
wire Ififo_element4_in_d_d9_d1 ;
wire reset_B;
wire Iin_d_d2_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
output Iout_d_d12_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Iin_d_d10_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
output Iout_d_d3_d1 ;
wire Ififo_element4_in_d_d4_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d7_d1 ;
wire Ififo_element4_in_d_d0_d0 ;
wire Ififo_element4_in_d_d11_d0 ;
wire Ififo_element3_in_d_d1_d0 ;
wire Ififo_element3_in_d_d9_d1 ;
output Iout_d_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Ififo_element2_in_d_d4_d0 ;
output Iout_d_d1_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element3_in_d_d0_d1 ;
wire Ififo_element4_in_d_d7_d0 ;
wire Ififo_element3_in_d_d3_d0 ;
wire Ififo_element4_in_d_d3_d1 ;
wire Ififo_element4_in_d_d4_d1 ;
output Iout_d_d8_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX4 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element0 (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_d_d7_d0 (Iin_d_d7_d0 ), .Iin_d_d7_d1 (Iin_d_d7_d1 ), .Iin_d_d8_d0 (Iin_d_d8_d0 ), .Iin_d_d8_d1 (Iin_d_d8_d1 ), .Iin_d_d9_d0 (Iin_d_d9_d0 ), .Iin_d_d9_d1 (Iin_d_d9_d1 ), .Iin_d_d10_d0 (Iin_d_d10_d0 ), .Iin_d_d10_d1 (Iin_d_d10_d1 ), .Iin_d_d11_d0 (Iin_d_d11_d0 ), .Iin_d_d11_d1 (Iin_d_d11_d1 ), .Iin_d_d12_d0 (Iin_d_d12_d0 ), .Iin_d_d12_d1 (Iin_d_d12_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element1_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element1_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element1_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element1_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element1_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element1_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element1_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element1_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element1_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element1_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element1_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element1_in_d_d12_d1 ), .Iout_a (Ififo_element1_in_a ), .Iout_v (Ififo_element1_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element1 (.Iin_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element1_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element1_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element1_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element1_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element1_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element1_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element1_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element1_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element1_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element1_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element1_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element1_in_d_d12_d1 ), .Iin_a (Ififo_element1_in_a ), .Iin_v (Ififo_element1_in_v ), .Iout_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element2_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element2_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element2_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element2_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element2_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element2_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element2_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element2_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element2_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element2_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element2_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element2_in_d_d12_d1 ), .Iout_a (Ififo_element2_in_a ), .Iout_v (Ififo_element2_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element2 (.Iin_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element2_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element2_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element2_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element2_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element2_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element2_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element2_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element2_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element2_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element2_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element2_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element2_in_d_d12_d1 ), .Iin_a (Ififo_element2_in_a ), .Iin_v (Ififo_element2_in_v ), .Iout_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element3_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element3_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element3_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element3_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element3_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element3_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element3_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element3_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element3_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element3_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element3_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element3_in_d_d12_d1 ), .Iout_a (Ififo_element3_in_a ), .Iout_v (Ififo_element3_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element3 (.Iin_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element3_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element3_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element3_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element3_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element3_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element3_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element3_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element3_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element3_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element3_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element3_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element3_in_d_d12_d1 ), .Iin_a (Ififo_element3_in_a ), .Iin_v (Ififo_element3_in_v ), .Iout_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element4_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element4_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element4_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element4_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element4_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element4_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element4_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element4_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element4_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element4_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element4_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element4_in_d_d12_d1 ), .Iout_a (Ififo_element4_in_a ), .Iout_v (Ififo_element4_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element4 (.Iin_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element4_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element4_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element4_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element4_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element4_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element4_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element4_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element4_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element4_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element4_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element4_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element4_in_d_d12_d1 ), .Iin_a (Ififo_element4_in_a ), .Iin_v (Ififo_element4_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_d_d7_d0 (Iout_d_d7_d0 ), .Iout_d_d7_d1 (Iout_d_d7_d1 ), .Iout_d_d8_d0 (Iout_d_d8_d0 ), .Iout_d_d8_d1 (Iout_d_d8_d1 ), .Iout_d_d9_d0 (Iout_d_d9_d0 ), .Iout_d_d9_d1 (Iout_d_d9_d1 ), .Iout_d_d10_d0 (Iout_d_d10_d0 ), .Iout_d_d10_d1 (Iout_d_d10_d1 ), .Iout_d_d11_d0 (Iout_d_d11_d0 ), .Iout_d_d11_d1 (Iout_d_d11_d1 ), .Iout_d_d12_d0 (Iout_d_d12_d0 ), .Iout_d_d12_d1 (Iout_d_d12_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_329_75_4/netlist/master.tag Normal file

@ -0,0 +1,2 @@
-- Master.tag File, Rev:1.0
verilog.v

499
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_329_75_4/netlist/verilog.v Normal file

File diff suppressed because one or more lines are too long

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_330_75_4/netlist/master.tag Normal file

@ -0,0 +1,2 @@
-- Master.tag File, Rev:1.0
verilog.v

515
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-- Master.tag File, Rev:1.0
verilog.v

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-- Master.tag File, Rev:1.0
verilog.v

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test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_37_75_4/netlist/master.tag Normal file

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-- Master.tag File, Rev:1.0
verilog.v

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module tmpl_0_0dataflow__neuro_0_0fifo_37_75_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element4_in_d_d1_d1 ;
wire Ififo_element3_in_d_d3_d1 ;
wire Ififo_element1_in_v ;
output Iout_d_d2_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d5_d1 ;
wire _reset_BX ;
wire Iout_v ;
wire Ififo_element4_in_v ;
wire Ififo_element3_in_d_d2_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d2_d0 ;
wire Ififo_element4_in_d_d2_d1 ;
wire Ififo_element3_in_d_d4_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Iin_d_d5_d0 ;
wire Ififo_element4_in_d_d4_d1 ;
wire Ififo_element4_in_d_d3_d1 ;
wire Ififo_element3_in_d_d0_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
output Iout_d_d5_d1 ;
wire Ififo_element4_in_d_d2_d0 ;
wire Ififo_element3_in_d_d6_d1 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Iout_a ;
output Iout_d_d3_d1 ;
wire Iin_d_d3_d1 ;
wire Ififo_element4_in_d_d3_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
output Iin_a ;
wire Iin_d_d1_d0 ;
output Iout_d_d6_d1 ;
wire Ififo_element4_in_d_d4_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire I_reset_BXX4 ;
output Iout_d_d3_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element3_in_d_d5_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element3_in_a ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element3_in_d_d4_d1 ;
wire Ififo_element3_in_d_d1_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire reset_B;
output Iout_d_d0_d0 ;
wire Ififo_element3_in_d_d3_d0 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element3_in_d_d5_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element3_in_d_d2_d1 ;
wire Ififo_element1_in_a ;
wire Ififo_element1_in_d_d3_d0 ;
wire Iin_d_d4_d0 ;
wire Ififo_element4_in_d_d6_d1 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d0_d1 ;
wire Ififo_element3_in_v ;
wire Ififo_element3_in_d_d0_d1 ;
wire Ififo_element2_in_a ;
wire Iin_d_d0_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element4_in_d_d5_d1 ;
wire Ififo_element3_in_d_d6_d0 ;
wire Ififo_element3_in_d_d1_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d4_d1 ;
wire Ififo_element4_in_a ;
wire Ififo_element4_in_d_d0_d0 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element4_in_d_d6_d0 ;
wire Ififo_element4_in_d_d1_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
output Iin_v ;
output Iout_d_d5_d0 ;
wire Ififo_element4_in_d_d5_d0 ;
wire Ififo_element4_in_d_d0_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX4 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element0 (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iout_a (Ififo_element1_in_a ), .Iout_v (Ififo_element1_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element1 (.Iin_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iin_a (Ififo_element1_in_a ), .Iin_v (Ififo_element1_in_v ), .Iout_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iout_a (Ififo_element2_in_a ), .Iout_v (Ififo_element2_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element2 (.Iin_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iin_a (Ififo_element2_in_a ), .Iin_v (Ififo_element2_in_v ), .Iout_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iout_a (Ififo_element3_in_a ), .Iout_v (Ififo_element3_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element3 (.Iin_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iin_a (Ififo_element3_in_a ), .Iin_v (Ififo_element3_in_v ), .Iout_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iout_a (Ififo_element4_in_a ), .Iout_v (Ififo_element4_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element4 (.Iin_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iin_a (Ififo_element4_in_a ), .Iin_v (Ififo_element4_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
endmodule

394
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fork_332_4/netlist/verilog.v

@ -202,215 +202,215 @@ module tmpl_0_0dataflow__neuro_0_0fork_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d
input reset_B;
// -- signals ---
output Iout2_d_d6_d1 ;
output Iout2_d_d11_d0 ;
output Iout2_d_d11_d1 ;
output Iout2_d_d27_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d25_d1 ;
wire Iout1_en_buf_out0 ;
output Iout1_d_d9_d0 ;
output Iout2_d_d5_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
output Iout1_d_d27_d1 ;
output Iout1_d_d16_d1 ;
wire Iout1_v ;
wire Iin_d_d31_d1 ;
wire Iout2_en_buf_out0 ;
output Iout1_d_d12_d0 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d25_d1 ;
wire Iout1_a ;
wire Iin_d_d9_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d26_d0 ;
output Iout2_d_d22_d0 ;
output Iout2_d_d2_d0 ;
wire Iin_d_d12_d0 ;
output Iout2_d_d28_d1 ;
wire Iin_d_d1_d0 ;
output Iout1_d_d8_d0 ;
output Iout2_d_d4_d0 ;
wire _en ;
output Iout2_d_d23_d1 ;
output Iout2_d_d0_d1 ;
output Iout1_d_d28_d1 ;
output Iout1_d_d3_d0 ;
output Iout1_d_d19_d0 ;
output Iout1_d_d14_d1 ;
wire Iin_d_d27_d1 ;
output Iout1_d_d29_d0 ;
output Iout1_d_d3_d1 ;
output Iout2_d_d14_d1 ;
output Iout1_d_d14_d0 ;
output Iout1_d_d17_d0 ;
output Iin_v ;
wire Iin_d_d26_d1 ;
wire Iin_d_d30_d1 ;
output Iout1_d_d10_d1 ;
output Iout2_d_d31_d1 ;
wire Iin_d_d16_d0 ;
output Iout1_d_d23_d0 ;
wire reset_B;
output Iout2_d_d29_d0 ;
output Iout2_d_d13_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d6_d0 ;
output Iout1_d_d7_d1 ;
wire _out2_a_B ;
output Iout1_d_d4_d0 ;
output Iout2_d_d29_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d21_d0 ;
output Iout1_d_d2_d0 ;
output Iout2_d_d17_d0 ;
wire Iin_d_d0_d0 ;
output Iout1_d_d0_d0 ;
output Iout2_d_d12_d0 ;
wire _in_v ;
wire Iin_d_d15_d0 ;
output Iout2_d_d30_d1 ;
wire Iout2_v ;
wire Iin_d_d13_d1 ;
output Iout1_d_d28_d0 ;
output Iout2_d_d19_d0 ;
output Iout1_d_d22_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d7_d0 ;
output Iout1_d_d24_d0 ;
output Iout2_d_d23_d0 ;
output Iout2_d_d24_d1 ;
wire Iin_d_d11_d0 ;
output Iout2_d_d3_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d29_d1 ;
output Iout2_d_d25_d0 ;
output Iout2_d_d1_d0 ;
output Iout2_d_d5_d1 ;
wire Iout1_a_B_buf_out0 ;
output Iout1_d_d16_d0 ;
output Iout1_d_d11_d1 ;
output Iout2_d_d18_d0 ;
output Iout1_d_d20_d1 ;
wire Iin_d_d30_d0 ;
output Iout2_d_d13_d0 ;
output Iout1_d_d26_d1 ;
output Iout2_d_d8_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d27_d0 ;
output Iout1_d_d27_d0 ;
output Iout1_d_d2_d1 ;
output Iout2_d_d28_d0 ;
wire Iin_d_d14_d0 ;
output Iout1_d_d31_d0 ;
output Iout1_d_d9_d1 ;
output Iout2_d_d31_d0 ;
output Iout2_d_d26_d0 ;
output Iout2_d_d14_d0 ;
wire Iin_d_d4_d0 ;
output Iout2_d_d16_d0 ;
output Iout2_d_d4_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d19_d0 ;
output Iout2_d_d18_d1 ;
output Iout2_d_d15_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d22_d0 ;
output Iout1_d_d13_d1 ;
output Iout2_d_d24_d0 ;
wire Iin_d_d10_d1 ;
output Iout1_d_d20_d0 ;
output Iout1_d_d6_d0 ;
output Iout1_d_d18_d0 ;
wire _reset_BX ;
wire Iin_d_d17_d1 ;
output Iout1_d_d22_d0 ;
output Iout2_d_d8_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d29_d0 ;
output Iout2_d_d0_d0 ;
output Iout2_d_d26_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d7_d0 ;
output Iout1_d_d3_d1 ;
output Iout2_d_d29_d0 ;
wire _out1_a_B ;
output Iout2_d_d31_d0 ;
output Iout2_d_d24_d0 ;
output Iout2_d_d7_d0 ;
output Iout2_d_d6_d1 ;
wire Iout2_a_B_buf_out0 ;
wire Iout2_en_buf_out0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d30_d0 ;
output Iout1_d_d21_d0 ;
output Iout2_d_d10_d1 ;
output Iout2_d_d9_d1 ;
output Iout2_d_d3_d1 ;
output Iout2_d_d2_d1 ;
output Iout1_d_d19_d1 ;
wire Iin_d_d29_d1 ;
output Iout1_d_d1_d0 ;
output Iout1_d_d10_d0 ;
output Iout2_d_d21_d1 ;
output Iout2_d_d4_d1 ;
output Iout1_d_d5_d0 ;
output Iout1_d_d11_d0 ;
output Iout1_d_d28_d0 ;
output Iout1_d_d20_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d18_d0 ;
output Iout2_d_d0_d0 ;
output Iout2_d_d25_d1 ;
wire Iin_d_d23_d0 ;
output Iout2_d_d10_d0 ;
output Iout2_d_d2_d0 ;
output Iout1_d_d29_d1 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d8_d0 ;
output Iout1_d_d14_d0 ;
output Iout1_d_d15_d0 ;
output Iout1_d_d9_d1 ;
output Iout2_d_d23_d0 ;
output Iout2_d_d17_d0 ;
output Iout2_d_d18_d1 ;
wire Iin_d_d28_d1 ;
output Iout1_d_d2_d1 ;
output Iout1_d_d7_d1 ;
output Iout2_d_d27_d0 ;
output Iout2_d_d3_d0 ;
output Iout1_d_d24_d0 ;
output Iout2_d_d31_d1 ;
output Iout2_d_d15_d1 ;
output Iout1_d_d27_d1 ;
wire Iout1_a ;
output Iout2_d_d19_d0 ;
output Iout1_d_d22_d0 ;
output Iout1_d_d23_d0 ;
output Iout1_d_d10_d1 ;
wire Iin_d_d24_d0 ;
output Iout2_d_d22_d0 ;
output Iout2_d_d7_d1 ;
wire Iin_d_d13_d1 ;
output Iout2_d_d18_d0 ;
output Iout2_d_d30_d1 ;
output Iout2_d_d23_d1 ;
wire Iin_d_d12_d0 ;
output Iout1_d_d0_d0 ;
wire Iin_d_d14_d1 ;
output Iout1_d_d26_d0 ;
output Iout1_d_d29_d0 ;
wire Iin_d_d25_d1 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d15_d0 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d1_d1 ;
wire _in_v ;
output Iout2_d_d20_d0 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d30_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d11_d1 ;
output Iout2_d_d14_d0 ;
output Iout2_d_d24_d1 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d24_d1 ;
output Iout1_d_d23_d1 ;
wire Iin_d_d5_d0 ;
output Iout1_d_d9_d0 ;
output Iout1_d_d12_d0 ;
output Iout1_d_d6_d1 ;
wire Iout2_v ;
output Iout2_d_d11_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d31_d0 ;
wire _reset_BX ;
wire Iin_d_d4_d0 ;
wire Iin_d_d21_d1 ;
output Iout1_d_d14_d1 ;
wire Iout1_v ;
wire Iin_d_d13_d0 ;
output Iout1_d_d13_d0 ;
output Iout2_d_d9_d0 ;
output Iout1_d_d17_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d27_d0 ;
output Iout1_d_d20_d0 ;
output Iout1_d_d30_d0 ;
output Iout1_d_d0_d1 ;
output Iout2_d_d6_d0 ;
wire Iin_d_d23_d1 ;
output Iout1_d_d30_d0 ;
output Iin_a ;
output Iout1_d_d5_d1 ;
output Iout2_d_d20_d0 ;
output Iout2_d_d30_d0 ;
wire Iin_d_d2_d1 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d22_d1 ;
output Iout2_d_d21_d1 ;
wire Iout2_a_B_buf_out0 ;
output Iout1_d_d31_d1 ;
output Iout1_d_d18_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d28_d0 ;
output Iout2_d_d16_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d25_d0 ;
output Iout2_d_d21_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d21_d1 ;
output Iout1_d_d25_d0 ;
output Iout1_d_d26_d0 ;
output Iout2_d_d7_d0 ;
output Iout2_d_d12_d1 ;
output Iout1_d_d19_d1 ;
output Iout1_d_d29_d1 ;
wire Iin_d_d16_d1 ;
output Iout2_d_d15_d0 ;
output Iout1_d_d10_d0 ;
output Iout2_d_d13_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d19_d0 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d20_d1 ;
output Iout2_d_d7_d1 ;
output Iout1_d_d23_d1 ;
wire Iin_d_d7_d1 ;
output Iout2_d_d10_d0 ;
output Iout2_d_d19_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d28_d1 ;
output Iout1_d_d12_d1 ;
wire Iin_d_d14_d1 ;
output Iout1_d_d11_d0 ;
output Iout1_d_d15_d0 ;
output Iout2_d_d17_d1 ;
output Iout1_d_d25_d1 ;
output Iout1_d_d24_d1 ;
wire Iout2_a ;
output Iout1_d_d1_d0 ;
output Iout2_d_d4_d0 ;
output Iout1_d_d21_d1 ;
output Iout1_d_d5_d0 ;
output Iout1_d_d7_d0 ;
output Iin_a ;
wire Iin_d_d12_d1 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d29_d1 ;
output Iout2_d_d26_d1 ;
output Iout2_d_d2_d1 ;
output Iout1_d_d22_d1 ;
wire Iin_d_d4_d1 ;
wire Iout2_a ;
output Iout1_d_d16_d1 ;
output Iout1_d_d6_d0 ;
output Iout1_d_d25_d0 ;
output Iout2_d_d30_d0 ;
wire Iin_d_d1_d0 ;
output Iout1_d_d17_d0 ;
output Iout1_d_d15_d1 ;
output Iout1_d_d21_d0 ;
output Iout1_d_d6_d1 ;
output Iout2_d_d0_d1 ;
output Iout1_d_d25_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d22_d1 ;
output Iout2_d_d27_d1 ;
output Iout2_d_d12_d1 ;
wire _en ;
output Iout1_d_d3_d0 ;
output Iout2_d_d17_d1 ;
output Iout2_d_d14_d1 ;
output Iin_v ;
output Iout2_d_d26_d0 ;
output Iout2_d_d9_d0 ;
wire Iin_d_d6_d1 ;
output Iout1_d_d11_d1 ;
output Iout2_d_d9_d1 ;
output Iout1_d_d16_d0 ;
output Iout2_d_d20_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d31_d1 ;
output Iout2_d_d12_d0 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d22_d0 ;
wire _out2_a_B ;
output Iout1_d_d4_d0 ;
output Iout2_d_d8_d0 ;
output Iout2_d_d16_d1 ;
output Iout1_d_d17_d1 ;
wire Iin_d_d28_d0 ;
output Iout1_d_d13_d1 ;
wire Iout1_en_buf_out0 ;
output Iout2_d_d25_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d10_d0 ;
output Iout1_d_d27_d0 ;
output Iout1_d_d5_d1 ;
output Iout2_d_d16_d0 ;
output Iout2_d_d13_d0 ;
wire Iin_d_d24_d1 ;
output Iout1_d_d2_d0 ;
output Iout1_d_d13_d0 ;
output Iout1_d_d18_d0 ;
output Iout1_d_d12_d1 ;
output Iout2_d_d19_d1 ;
wire Iin_d_d8_d1 ;
output Iout2_d_d28_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d31_d0 ;
output Iout2_d_d27_d0 ;
output Iout1_d_d30_d1 ;
wire _out1_a_B ;
wire Iin_d_d21_d0 ;
output Iout2_d_d22_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d30_d1 ;
wire Iout1_a_B_buf_out0 ;
wire Iin_d_d9_d0 ;
output Iout2_d_d21_d0 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d5_d1 ;
output Iout1_d_d31_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d8_d0 ;
output Iout2_d_d28_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d10_d1 ;
wire reset_B;
wire Iin_d_d0_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d11_d0 ;
output Iout1_d_d31_d0 ;
output Iout2_d_d11_d0 ;
output Iout1_d_d28_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d23_d1 ;
output Iout1_d_d19_d0 ;
// --- instances
A_4C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout1_v ), .c4(Iout2_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));

400
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0merge_331_4/netlist/verilog.v

@ -196,214 +196,214 @@ module tmpl_0_0dataflow__neuro_0_0merge_331_4(Iin1_d_d0_d0 , Iin1_d_d0_d1 , Iin1
input reset_B;
// -- signals ---
wire Iin2_d_d10_d1 ;
wire I_in2_arb_X0 ;
wire Iin1_d_d21_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d26_d0 ;
output Iout_d_d9_d1 ;
output Iout_d_d17_d0 ;
wire Iin1_d_d30_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d19_d1 ;
wire Iin1_d_d7_d0 ;
wire Iin2_d_d9_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d13_d1 ;
wire Iin2_d_d8_d1 ;
wire Iin1_d_d12_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire Iin1_d_d9_d1 ;
output Iin1_a ;
output Iout_d_d3_d0 ;
wire Iin2_d_d5_d1 ;
output Iout_d_d3_d1 ;
wire Iin2_d_d0_d1 ;
output Iout_d_d15_d0 ;
wire Iin1_d_d23_d1 ;
output Iout_d_d0_d0 ;
wire I_out_a_BX0 ;
wire Iin2_d_d23_d0 ;
output Iin2_a ;
output Iout_d_d30_d1 ;
wire Iin2_d_d18_d0 ;
wire Iout_a ;
output Iout_d_d13_d0 ;
wire _out_a_B ;
wire Iin1_d_d11_d0 ;
wire Iin1_d_d10_d1 ;
output Iout_d_d24_d0 ;
wire Iin1_d_d26_d0 ;
wire _in1_a_B ;
wire Iin1_d_d12_d1 ;
wire Iin1_d_d17_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d14_d0 ;
wire _in2_arb ;
wire Iin1_d_d19_d1 ;
wire Iin2_d_d30_d1 ;
wire Iin2_d_d27_d1 ;
wire Iin2_d_d6_d1 ;
output Iout_d_d5_d1 ;
wire Iin1_d_d17_d0 ;
wire Iin2_d_d17_d0 ;
wire Iin1_d_d20_d0 ;
wire Iin2_d_d20_d0 ;
wire reset_B;
wire Iin2_d_d19_d0 ;
output Iout_d_d21_d0 ;
wire _in1_arb ;
wire Iin1_d_d9_d0 ;
wire Iin2_d_d11_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin2_d_d22_d1 ;
wire Iin2_d_d12_d1 ;
wire Iin2_d_d11_d1 ;
wire Iin2_d_d28_d0 ;
wire Iin1_d_d3_d1 ;
wire Iin1_d_d30_d1 ;
wire Iin2_d_d13_d1 ;
wire Iin1_d_d4_d1 ;
wire Iin1_d_d0_d0 ;
output Iout_d_d30_d0 ;
wire Iin1_d_d8_d1 ;
wire Iin1_d_d21_d1 ;
output Iout_d_d12_d1 ;
wire Iin2_d_d29_d1 ;
wire Iin2_d_d2_d1 ;
wire Iin2_d_d19_d0 ;
wire Iin1_d_d5_d1 ;
wire I_in1_arb_X0 ;
wire Iin1_d_d9_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d7_d1 ;
wire Iin2_d_d8_d0 ;
output Iout_d_d20_d0 ;
wire Iin1_d_d20_d0 ;
output Iout_d_d25_d0 ;
wire Iout_a ;
output Iout_d_d29_d1 ;
output Iout_d_d9_d0 ;
wire Iin2_d_d7_d1 ;
wire Iin2_d_d11_d0 ;
wire Iin1_d_d1_d1 ;
output Iout_d_d20_d1 ;
wire Iin2_d_d1_d1 ;
wire Iin1_d_d13_d0 ;
output Iout_d_d21_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin1_d_d4_d1 ;
wire Iin1_d_d7_d1 ;
wire _out_a_B ;
wire Iin1_d_d27_d1 ;
output Iout_d_d28_d0 ;
wire I_out_temp_d_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d14_d0 ;
wire Iin2_d_d26_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d10_d0 ;
wire _en ;
wire Iin1_d_d16_d0 ;
wire I_en_X0 ;
wire Iin1_d_d6_d0 ;
output Iout_d_d4_d1 ;
wire _in1_a_B ;
output Iout_d_d22_d1 ;
wire Iin2_d_d18_d0 ;
output Iout_d_d24_d1 ;
output Iin1_v ;
output Iout_d_d29_d0 ;
wire Iin1_d_d14_d1 ;
output Iout_d_d13_d1 ;
wire Iin1_d_d21_d0 ;
wire Iin2_d_d25_d0 ;
wire _in2_arb ;
wire Iin1_d_d20_d1 ;
wire Iin2_d_d5_d0 ;
wire Iin1_d_d8_d0 ;
wire Iin1_d_d18_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d9_d1 ;
wire Iin1_d_d29_d0 ;
wire Iin1_d_d12_d1 ;
wire Iin2_d_d24_d1 ;
wire Iin2_d_d23_d1 ;
wire Iin2_d_d17_d0 ;
wire Iin1_d_d19_d0 ;
wire Iin1_d_d6_d1 ;
wire Iin2_d_d27_d0 ;
wire _in1_arb ;
wire Iin2_d_d16_d1 ;
wire Iin1_d_d22_d1 ;
wire Iin2_d_d3_d0 ;
wire Iin1_d_d11_d0 ;
wire Iin1_d_d15_d0 ;
wire _in1_arb_temp ;
wire Iin2_d_d20_d1 ;
output Iout_d_d3_d1 ;
wire Iin1_d_d17_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d17_d0 ;
wire Iin2_d_d28_d0 ;
output Iout_d_d18_d1 ;
wire Iin2_d_d12_d1 ;
wire Iin2_d_d20_d0 ;
output Iout_d_d26_d0 ;
wire Iin2_d_d29_d0 ;
wire Iin2_d_d11_d1 ;
output Iout_d_d11_d1 ;
wire Iin2_d_d5_d1 ;
wire reset_B;
output Iout_d_d19_d1 ;
wire Iin2_d_d13_d1 ;
wire Iin1_d_d26_d1 ;
output Iout_d_d22_d0 ;
wire Iin1_d_d22_d0 ;
wire Iin1_d_d23_d0 ;
wire Iin2_d_d21_d0 ;
wire Iin2_d_d22_d0 ;
wire Iin2_d_d23_d0 ;
output Iout_d_d10_d1 ;
wire Iin2_d_d12_d0 ;
output Iout_d_d12_d1 ;
wire Iin2_d_d0_d1 ;
wire Iin1_d_d25_d1 ;
wire Iin1_d_d21_d1 ;
wire Iin2_d_d15_d1 ;
wire Iin1_d_d26_d0 ;
wire Iin2_d_d25_d1 ;
wire Iin1_d_d23_d1 ;
output Iout_d_d12_d0 ;
wire Iin2_d_d16_d0 ;
wire Iin1_d_d25_d0 ;
output Iout_d_d14_d1 ;
wire Iin2_d_d28_d1 ;
wire Iin2_d_d14_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d16_d0 ;
wire Iin2_d_d27_d1 ;
wire Iin1_d_d9_d1 ;
output Iout_d_d2_d0 ;
wire Iin2_d_d6_d0 ;
wire Iin1_d_d0_d1 ;
wire Iin1_d_d3_d1 ;
wire Iin2_d_d4_d1 ;
output Iout_d_d1_d1 ;
wire Iin1_d_d3_d0 ;
output Iout_d_d19_d0 ;
wire Iout_v ;
wire Iin2_d_d8_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d23_d1 ;
wire Iin2_d_d1_d0 ;
wire Iin2_d_d13_d0 ;
output Iout_d_d23_d0 ;
wire Iin2_d_d24_d0 ;
wire Iin1_d_d17_d1 ;
output Iout_d_d30_d1 ;
wire Iin2_d_d19_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d15_d1 ;
wire Iin2_d_d3_d1 ;
wire Iin1_d_d12_d0 ;
wire Iin1_d_d14_d0 ;
wire Iin1_d_d18_d0 ;
wire Iin2_d_d21_d1 ;
output Iout_d_d28_d1 ;
wire Iin1_d_d24_d1 ;
wire Iin1_d_d4_d0 ;
wire Iin1_d_d5_d0 ;
wire Iin2_d_d7_d0 ;
wire Iin2_d_d26_d0 ;
wire _in2_a_B ;
wire Iin1_d_d19_d1 ;
output Iout_d_d21_d1 ;
wire Iin2_d_d17_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d7_d0 ;
wire Iin1_d_d28_d0 ;
output Iin2_v ;
wire Iin1_d_d30_d1 ;
wire Iin1_d_d10_d0 ;
wire Iin1_d_d2_d1 ;
wire Iin2_d_d18_d1 ;
wire I_in2_arb_X0 ;
wire Iin1_d_d10_d1 ;
wire Iin1_d_d11_d1 ;
wire Iin2_d_d9_d1 ;
output Iin1_a ;
wire Iin1_d_d27_d0 ;
wire Iin2_d_d0_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d7_d0 ;
wire Iin1_d_d13_d0 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d8_d0 ;
wire Iin2_d_d15_d0 ;
wire Iin2_d_d30_d0 ;
wire Iin1_d_d5_d1 ;
wire Iin1_d_d6_d1 ;
output Iout_d_d10_d1 ;
wire Iin1_d_d16_d0 ;
wire Iin1_d_d7_d1 ;
wire Iin1_d_d25_d1 ;
output Iout_d_d4_d0 ;
wire Iin1_d_d6_d0 ;
wire Iin1_d_d15_d0 ;
output Iout_d_d16_d1 ;
wire Iin2_d_d5_d0 ;
wire Iin1_d_d25_d0 ;
output Iout_d_d18_d1 ;
wire Iin2_d_d3_d1 ;
output Iout_d_d20_d0 ;
wire Iin1_d_d11_d1 ;
output Iout_d_d24_d1 ;
wire Iin1_d_d4_d0 ;
output Iout_d_d12_d0 ;
wire Iin1_d_d14_d0 ;
wire Iin1_d_d2_d0 ;
output Iout_d_d22_d0 ;
wire Iin1_d_d26_d1 ;
wire Iin1_d_d1_d1 ;
wire Iout_v ;
wire Iin2_d_d15_d1 ;
wire Iin1_d_d13_d1 ;
wire Iin2_d_d24_d1 ;
output Iout_d_d11_d1 ;
output Iin1_v ;
wire Iin2_d_d10_d0 ;
wire Iin1_d_d18_d0 ;
wire Iin2_d_d25_d0 ;
wire I_reset_BXX0 ;
wire Iin1_d_d27_d0 ;
output Iout_d_d29_d0 ;
wire _in2_a_B ;
output Iout_d_d14_d1 ;
output Iout_d_d8_d1 ;
wire Iin2_d_d14_d0 ;
output Iout_d_d25_d0 ;
wire Iin2_d_d20_d1 ;
output Iout_d_d2_d0 ;
wire Iin2_d_d3_d0 ;
wire Iin2_d_d26_d0 ;
wire Iin2_d_d27_d0 ;
output Iout_d_d21_d1 ;
wire Iin1_d_d24_d1 ;
wire Iin1_d_d19_d0 ;
wire Iin2_d_d18_d1 ;
wire _in1_arb_temp ;
wire I_out_temp_d_d0 ;
wire Iin2_d_d29_d1 ;
wire Iin2_d_d7_d0 ;
wire Iin2_d_d21_d0 ;
output Iout_d_d28_d0 ;
wire _reset_BX ;
wire Iin2_d_d1_d1 ;
wire Iin1_d_d5_d0 ;
wire Iin1_d_d27_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d25_d1 ;
wire Iin2_d_d16_d1 ;
output Iout_d_d4_d1 ;
wire Iin1_d_d22_d0 ;
wire Iin1_d_d14_d1 ;
output Iout_d_d26_d1 ;
wire Iin2_d_d4_d0 ;
wire Iin2_d_d6_d0 ;
wire Iin2_d_d8_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d27_d1 ;
output Iout_d_d1_d0 ;
wire Iin2_d_d28_d1 ;
wire Iin2_d_d12_d0 ;
output Iout_d_d27_d0 ;
wire Iin1_d_d0_d1 ;
output Iout_d_d0_d0 ;
wire Iin2_d_d16_d0 ;
output Iout_d_d30_d0 ;
wire Iin2_d_d17_d1 ;
output Iout_d_d6_d1 ;
wire Iin2_d_d24_d0 ;
wire Iin2_d_d9_d1 ;
wire I_en_X0 ;
wire I_in1_arb_X0 ;
wire Iin1_d_d10_d0 ;
wire Iin1_d_d23_d0 ;
wire Iin2_d_d2_d1 ;
output Iout_d_d1_d1 ;
wire Iin1_d_d28_d1 ;
wire Iin1_d_d3_d0 ;
output Iout_d_d16_d0 ;
wire Iin2_d_d19_d1 ;
wire Iin2_d_d14_d1 ;
wire Iin2_d_d1_d0 ;
wire Iin2_d_d22_d0 ;
wire Iin2_d_d26_d1 ;
wire Iin1_d_d29_d1 ;
wire _in2_arb_temp ;
wire Iin2_d_d25_d1 ;
wire Iin1_d_d28_d0 ;
output Iout_d_d7_d1 ;
wire Iin2_d_d2_d0 ;
wire Iin1_d_d2_d1 ;
wire Iin2_d_d23_d1 ;
wire Iin2_d_d4_d1 ;
wire _en ;
wire Iin1_d_d15_d1 ;
wire Iin1_d_d16_d1 ;
output Iin2_v ;
wire Iin2_d_d21_d1 ;
wire Iin2_d_d13_d0 ;
wire Iin2_d_d29_d0 ;
wire Iin1_d_d20_d1 ;
wire Iin2_d_d7_d1 ;
wire Iin1_d_d0_d0 ;
output Iout_d_d23_d0 ;
wire Iin1_d_d29_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d6_d1 ;
wire Iin2_d_d9_d0 ;
wire Iin1_d_d13_d1 ;
output Iout_d_d25_d1 ;
wire Iin2_d_d10_d1 ;
wire Iin1_d_d28_d1 ;
output Iout_d_d6_d0 ;
wire Iin1_d_d7_d0 ;
output Iout_d_d11_d0 ;
wire Iin1_d_d2_d0 ;
wire Iin2_d_d14_d0 ;
wire Iin2_d_d15_d0 ;
wire Iin1_d_d30_d0 ;
wire Iin1_d_d18_d1 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d15_d0 ;
wire _in2_arb_temp ;
wire Iin2_d_d22_d1 ;
wire Iin2_d_d6_d1 ;
wire Iin1_d_d29_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d27_d0 ;
wire Iin2_d_d30_d0 ;
wire Iin1_d_d16_d1 ;
wire Iin2_d_d2_d0 ;
wire Iin2_d_d10_d0 ;
output Iin2_a ;
wire Iin2_d_d30_d1 ;
output Iout_d_d27_d1 ;
wire Iin2_d_d4_d0 ;
wire _reset_BX ;
// --- instances
A_2C2N2N_RB_X1 Imerge_func_f0 (.y(Iout_d_d0_d0 ), .c1(I_en_X0 ), .c2(I_out_a_BX0 ), .na1(I_in1_arb_X0 ), .na2(Iin1_d_d0_d0 ), .nb1(I_in2_arb_X0 ), .nb2(Iin2_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));

404
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0merge_332_4/netlist/verilog.v

@ -202,220 +202,220 @@ module tmpl_0_0dataflow__neuro_0_0merge_332_4(Iin1_d_d0_d0 , Iin1_d_d0_d1 , Iin1
input reset_B;
// -- signals ---
output Iout_d_d28_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d10_d0 ;
wire Iin2_d_d19_d0 ;
wire Iin2_d_d22_d1 ;
output Iout_d_d15_d0 ;
wire Iin1_d_d19_d0 ;
wire Iin1_d_d13_d1 ;
wire Iin1_d_d7_d0 ;
output Iout_d_d9_d0 ;
wire Iin2_d_d11_d0 ;
wire Iin1_d_d16_d0 ;
output Iout_d_d27_d0 ;
wire Iin1_d_d8_d1 ;
output Iout_d_d0_d1 ;
output Iin1_a ;
wire Iin2_d_d15_d0 ;
wire Iin1_d_d21_d0 ;
wire Iin2_d_d28_d0 ;
wire Iin1_d_d6_d1 ;
wire Iin1_d_d15_d1 ;
output Iout_d_d18_d1 ;
wire Iin2_d_d7_d1 ;
wire Iin1_d_d12_d1 ;
wire Iin2_d_d19_d1 ;
wire Iin2_d_d13_d1 ;
output Iout_d_d7_d1 ;
wire I_in2_arb_X0 ;
wire Iin2_d_d8_d0 ;
wire Iin2_d_d31_d0 ;
wire Iin2_d_d23_d1 ;
wire Iin2_d_d5_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d31_d0 ;
wire Iin2_d_d8_d1 ;
wire Iin2_d_d17_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d12_d1 ;
wire Iin1_d_d22_d0 ;
output Iout_d_d5_d0 ;
wire Iin1_d_d5_d0 ;
wire Iin2_d_d5_d0 ;
wire Iin1_d_d27_d0 ;
wire Iin2_d_d24_d1 ;
wire Iin2_d_d14_d1 ;
output Iout_d_d29_d0 ;
wire Iin2_d_d0_d1 ;
wire Iin1_d_d25_d1 ;
wire I_out_a_BX0 ;
wire Iin2_d_d25_d0 ;
wire Iin2_d_d29_d1 ;
wire Iin1_d_d30_d1 ;
output Iout_d_d4_d0 ;
wire _in2_arb_temp ;
wire Iin2_d_d27_d0 ;
wire Iin1_d_d0_d1 ;
wire _out_a_B ;
output Iin2_a ;
wire I_en_X0 ;
wire Iin1_d_d10_d0 ;
output Iout_d_d12_d0 ;
wire Iin1_d_d23_d0 ;
wire Iin2_d_d29_d0 ;
output Iout_d_d27_d1 ;
wire Iin2_d_d25_d1 ;
output Iout_d_d4_d1 ;
wire Iin2_d_d6_d0 ;
wire Iout_v ;
wire Iin2_d_d13_d0 ;
wire Iin2_d_d20_d0 ;
wire Iin2_d_d10_d0 ;
output Iout_d_d22_d0 ;
wire Iin1_d_d31_d0 ;
output Iout_d_d9_d1 ;
wire Iin2_d_d1_d1 ;
wire Iin1_d_d4_d0 ;
output Iout_d_d7_d0 ;
wire _in2_a_B ;
wire _en ;
wire I_out_temp_d_d0 ;
output Iout_d_d18_d1 ;
wire I_in1_arb_X0 ;
wire Iin2_d_d16_d0 ;
wire Iin1_d_d17_d0 ;
wire Iin1_d_d0_d1 ;
output Iout_d_d15_d1 ;
wire Iin2_d_d2_d1 ;
wire _reset_BX ;
wire Iin2_d_d1_d0 ;
wire Iin2_d_d17_d1 ;
output Iout_d_d17_d1 ;
wire Iin2_d_d8_d1 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d5_d0 ;
wire Iin1_d_d21_d0 ;
wire Iin2_d_d12_d1 ;
output Iout_d_d3_d0 ;
wire reset_B;
wire Iin2_d_d30_d1 ;
output Iout_d_d4_d0 ;
wire Iin2_d_d14_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin2_d_d20_d1 ;
wire I_out_a_BX0 ;
wire Iin2_d_d5_d0 ;
output Iout_d_d20_d0 ;
wire Iin1_d_d28_d0 ;
wire Iin1_d_d16_d1 ;
wire Iin2_d_d26_d1 ;
output Iout_d_d24_d1 ;
wire Iin2_d_d22_d1 ;
wire Iin2_d_d8_d0 ;
wire _in2_arb_temp ;
wire Iin1_d_d31_d1 ;
output Iout_d_d19_d0 ;
wire Iin1_d_d27_d0 ;
wire Iin2_d_d16_d1 ;
wire Iin2_d_d0_d1 ;
output Iout_d_d31_d0 ;
output Iout_d_d26_d1 ;
wire Iin2_d_d10_d1 ;
wire Iin2_d_d3_d0 ;
wire _out_a_B ;
output Iout_d_d22_d1 ;
wire Iin2_d_d9_d1 ;
output Iout_d_d6_d0 ;
wire Iin1_d_d26_d0 ;
wire Iin2_d_d27_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d8_d1 ;
wire Iin1_d_d23_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d28_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d30_d0 ;
wire Iin1_d_d7_d1 ;
wire Iin1_d_d17_d1 ;
wire Iin1_d_d18_d1 ;
wire Iout_a ;
wire Iin1_d_d3_d0 ;
wire Iin1_d_d11_d1 ;
output Iout_d_d26_d0 ;
wire Iin1_d_d29_d0 ;
wire Iin1_d_d19_d1 ;
wire Iin1_d_d14_d0 ;
wire Iin2_d_d4_d1 ;
wire Iin1_d_d2_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d24_d0 ;
wire Iin1_d_d30_d0 ;
wire Iin1_d_d12_d1 ;
wire Iin2_d_d21_d0 ;
output Iout_d_d25_d0 ;
wire Iin2_d_d26_d0 ;
wire _in1_a_B ;
wire _in1_arb ;
wire Iin2_d_d15_d1 ;
wire Iin2_d_d16_d0 ;
wire Iin1_d_d5_d1 ;
output Iout_d_d23_d1 ;
output Iin1_v ;
wire I_in2_arb_X0 ;
wire Iin2_d_d7_d0 ;
wire Iin1_d_d8_d0 ;
wire Iin1_d_d9_d0 ;
wire Iin1_d_d10_d0 ;
output Iout_d_d17_d0 ;
wire Iin2_d_d28_d0 ;
wire _in2_arb ;
wire Iin1_d_d4_d1 ;
wire Iin2_d_d29_d1 ;
output Iout_d_d4_d1 ;
wire Iin2_d_d10_d0 ;
wire Iin1_d_d19_d0 ;
wire Iin1_d_d31_d0 ;
output Iout_d_d25_d1 ;
wire Iin2_d_d18_d0 ;
output Iout_d_d13_d0 ;
wire Iin2_d_d20_d0 ;
wire Iin2_d_d23_d1 ;
wire Iin2_d_d3_d1 ;
wire Iin2_d_d11_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d13_d1 ;
wire Iin1_d_d23_d1 ;
wire Iin2_d_d17_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d18_d0 ;
wire Iin1_d_d11_d1 ;
wire Iout_a ;
wire Iin1_d_d27_d1 ;
wire Iin1_d_d20_d0 ;
output Iout_d_d8_d1 ;
wire Iin1_d_d26_d1 ;
wire I_reset_BXX0 ;
wire Iin1_d_d11_d0 ;
wire Iin1_d_d12_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d2_d0 ;
wire Iin2_d_d3_d0 ;
output Iout_d_d16_d1 ;
wire Iin2_d_d2_d1 ;
wire Iin2_d_d6_d1 ;
wire Iin2_d_d22_d0 ;
wire Iin1_d_d3_d1 ;
wire Iin1_d_d17_d1 ;
wire Iin2_d_d1_d1 ;
wire Iin2_d_d23_d0 ;
wire _in1_arb ;
wire reset_B;
wire _reset_BX ;
output Iin2_v ;
wire Iin2_d_d3_d1 ;
wire Iin1_d_d2_d0 ;
output Iout_d_d20_d0 ;
wire _in2_arb ;
wire Iin1_d_d9_d1 ;
output Iout_d_d11_d0 ;
wire Iin1_d_d25_d0 ;
wire Iin1_d_d1_d1 ;
wire Iin1_d_d21_d1 ;
wire Iin1_d_d20_d1 ;
wire Iin1_d_d9_d0 ;
wire Iin1_d_d30_d0 ;
wire Iin1_d_d4_d1 ;
wire Iin2_d_d16_d1 ;
wire Iin2_d_d9_d0 ;
wire Iin2_d_d20_d1 ;
wire Iin1_d_d22_d1 ;
output Iout_d_d10_d1 ;
wire Iin1_d_d28_d0 ;
wire Iin2_d_d31_d1 ;
wire Iin2_d_d14_d0 ;
output Iout_d_d16_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d24_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin2_d_d18_d0 ;
wire Iin1_d_d4_d0 ;
wire Iin2_d_d4_d0 ;
output Iin1_v ;
output Iout_d_d0_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d25_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d21_d1 ;
wire Iin1_d_d31_d1 ;
wire Iin2_d_d30_d0 ;
output Iout_d_d31_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d17_d1 ;
wire Iin1_d_d0_d0 ;
wire Iin1_d_d13_d0 ;
wire Iin1_d_d2_d1 ;
wire Iin2_d_d28_d1 ;
wire Iin1_d_d7_d1 ;
wire Iin2_d_d26_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d11_d1 ;
wire Iin2_d_d10_d1 ;
wire Iin1_d_d14_d0 ;
wire Iin1_d_d26_d0 ;
wire Iin2_d_d19_d1 ;
output Iout_d_d14_d0 ;
output Iout_d_d28_d0 ;
wire Iin1_d_d5_d1 ;
output Iout_d_d2_d1 ;
wire Iin1_d_d29_d1 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d17_d0 ;
wire Iin1_d_d14_d1 ;
output Iout_d_d23_d1 ;
wire Iin1_d_d8_d0 ;
wire Iin1_d_d15_d0 ;
output Iout_d_d6_d1 ;
wire Iin1_d_d28_d1 ;
wire Iin2_d_d30_d1 ;
output Iout_d_d29_d1 ;
wire Iin2_d_d18_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d14_d1 ;
wire Iin2_d_d2_d0 ;
wire Iin1_d_d3_d0 ;
wire Iin2_d_d7_d0 ;
wire Iin1_d_d10_d1 ;
wire Iin2_d_d9_d1 ;
wire Iin2_d_d21_d0 ;
output Iout_d_d3_d1 ;
wire Iin1_d_d24_d1 ;
wire Iin1_d_d6_d0 ;
output Iout_d_d23_d0 ;
wire I_out_temp_d_d0 ;
wire Iin2_d_d27_d1 ;
wire Iin2_d_d4_d1 ;
wire Iin2_d_d0_d0 ;
wire Iin2_d_d12_d0 ;
wire _en ;
wire Iin2_d_d21_d1 ;
wire Iin1_d_d19_d1 ;
output Iout_d_d26_d0 ;
wire Iin2_d_d12_d1 ;
wire Iin1_d_d18_d1 ;
output Iout_d_d7_d0 ;
wire Iin1_d_d18_d0 ;
wire _in2_a_B ;
wire Iin1_d_d16_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d14_d0 ;
wire Iin2_d_d29_d0 ;
wire Iout_v ;
wire Iin2_d_d25_d0 ;
output Iout_d_d20_d1 ;
wire Iin2_d_d18_d1 ;
output Iout_d_d7_d1 ;
wire Iin1_d_d0_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d29_d1 ;
wire Iin2_d_d25_d1 ;
output Iout_d_d10_d1 ;
wire Iin1_d_d20_d1 ;
wire Iin1_d_d25_d0 ;
output Iout_d_d21_d1 ;
wire Iin2_d_d6_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d1_d1 ;
wire Iin1_d_d10_d1 ;
wire Iin2_d_d19_d0 ;
wire _in1_arb_temp ;
wire Iin1_d_d14_d1 ;
output Iout_d_d27_d1 ;
wire Iin2_d_d11_d1 ;
wire Iin1_d_d30_d1 ;
wire Iin2_d_d24_d0 ;
wire Iin2_d_d15_d1 ;
wire Iin2_d_d1_d0 ;
wire Iin2_d_d26_d0 ;
wire Iin1_d_d12_d0 ;
output Iout_d_d27_d0 ;
wire Iin1_d_d28_d1 ;
wire Iin2_d_d0_d0 ;
output Iout_d_d2_d0 ;
wire Iin1_d_d7_d0 ;
wire Iin2_d_d22_d0 ;
wire Iin1_d_d6_d1 ;
wire Iin2_d_d21_d1 ;
wire Iin2_d_d6_d1 ;
wire Iin2_d_d4_d0 ;
wire Iin1_d_d1_d1 ;
wire Iin2_d_d14_d1 ;
wire Iin1_d_d29_d1 ;
output Iin2_v ;
wire Iin2_d_d9_d0 ;
wire Iin2_d_d13_d0 ;
wire Iin1_d_d13_d1 ;
wire Iin2_d_d23_d0 ;
wire Iin1_d_d15_d1 ;
output Iout_d_d31_d1 ;
wire I_reset_BXX0 ;
wire Iin1_d_d6_d0 ;
output Iin2_a ;
output Iout_d_d0_d0 ;
wire Iin1_d_d20_d0 ;
wire Iin1_d_d9_d1 ;
output Iout_d_d9_d0 ;
wire Iin2_d_d12_d0 ;
output Iout_d_d18_d0 ;
wire Iin1_d_d18_d0 ;
output Iout_d_d1_d0 ;
wire Iin2_d_d27_d0 ;
output Iout_d_d30_d1 ;
output Iout_d_d28_d1 ;
wire Iin2_d_d7_d1 ;
wire Iin1_d_d23_d0 ;
wire Iin2_d_d31_d0 ;
output Iout_d_d2_d1 ;
wire Iin1_d_d16_d0 ;
wire Iin1_d_d17_d0 ;
output Iout_d_d15_d0 ;
wire Iin2_d_d15_d0 ;
wire Iin2_d_d30_d0 ;
wire Iin1_d_d2_d1 ;
wire Iin1_d_d22_d1 ;
wire Iin1_d_d11_d0 ;
wire Iin1_d_d13_d0 ;
wire Iin2_d_d17_d0 ;
wire Iin1_d_d3_d1 ;
wire Iin2_d_d24_d1 ;
output Iout_d_d0_d1 ;
output Iin1_a ;
output Iout_d_d21_d0 ;
wire Iin1_d_d22_d0 ;
wire Iin2_d_d31_d1 ;
wire I_en_X0 ;
output Iout_d_d22_d0 ;
output Iout_d_d16_d1 ;
wire Iin1_d_d24_d1 ;
wire Iin1_d_d15_d0 ;
wire Iin1_d_d8_d1 ;
wire Iin1_d_d26_d1 ;
wire Iin1_d_d25_d1 ;
wire Iin1_d_d21_d1 ;
output Iout_d_d11_d0 ;
wire Iin2_d_d28_d1 ;
wire Iin2_d_d5_d1 ;
wire Iin2_d_d2_d0 ;
wire Iin1_d_d5_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d16_d0 ;
wire Iin1_d_d27_d1 ;
// --- instances
A_2C2N2N_RB_X1 Imerge_func_f0 (.y(Iout_d_d0_d0 ), .c1(I_en_X0 ), .c2(I_out_a_BX0 ), .na1(I_in1_arb_X0 ), .na2(Iin1_d_d0_d0 ), .nb1(I_in2_arb_X0 ), .nb2(Iin2_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));

18
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__hs__2d/netlist/verilog.v

@ -11,18 +11,18 @@ module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(Iin_d_d0 , Iin_a , Ioutx_d_d0 , Io
// -- signals ---
output Iin_a ;
wire _y_a_B ;
wire Iouty_a ;
wire Ioutx_a ;
wire Iin_d_d0 ;
output Iouty_d_d0 ;
wire _en ;
wire reset_B;
wire _reqB ;
wire _x_a_B ;
output Ioutx_d_d0 ;
wire _reset_BX ;
wire _reqB ;
output Iouty_d_d0 ;
wire Iin_d_d0 ;
wire reset_B;
wire Ioutx_a ;
wire _req ;
wire _en ;
wire Iouty_a ;
wire _reset_BX ;
wire _y_a_B ;
// --- instances
INV_X1 Ireq_inv (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));

516
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4/netlist/verilog.v

@ -268,278 +268,278 @@ module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4(Iin0_d_d0 , Iin0_a
input reset_B;
// -- signals ---
wire Ioutx6_a ;
output Iin31_a ;
wire Iouty4_a ;
output Iin19_a ;
wire Iin2_d_d0 ;
wire Iouty0_a ;
wire Iin12_d_d0 ;
wire Iouty2_a ;
output Iin52_a ;
output Iin62_a ;
output Iin65_a ;
wire Ioutx12_a ;
output Iouty2_d_d0 ;
wire Iin3_d_d0 ;
output Iin69_a ;
output Iin60_a ;
output Iin85_a ;
output Ioutx12_d_d0 ;
wire Iin63_d_d0 ;
output Iin79_a ;
output Ito_pd_y0_a ;
output Ioutx2_d_d0 ;
wire Iin69_d_d0 ;
wire Iin74_d_d0 ;
output Iin21_a ;
output Iin67_a ;
wire Irsb5_in ;
output Ito_pd_y4_a ;
wire Iin78_d_d0 ;
wire Iin47_d_d0 ;
output Ioutx1_d_d0 ;
wire Iin46_d_d0 ;
output Iin56_a ;
output Ito_pd_y5_d_d0 ;
wire Iin21_d_d0 ;
output Iin9_a ;
wire Iin55_d_d0 ;
wire Ioutx11_a ;
wire Ioutx5_a ;
wire Iin23_d_d0 ;
output Iin6_a ;
wire Iin11_d_d0 ;
output Ito_pd_x10_a ;
wire Iin7_d_d0 ;
wire Ineurons89_reset_B ;
wire Ioutx4_a ;
wire Iin26_d_d0 ;
output Iin51_a ;
wire Iin13_d_d0 ;
output Ito_pd_x11_a ;
output Ito_pd_x7_a ;
wire Iin6_d_d0 ;
output Iin44_a ;
output Iin73_a ;
wire Iin44_d_d0 ;
wire Iin59_d_d0 ;
output Iouty0_d_d0 ;
output Ioutx7_d_d0 ;
wire Iin52_d_d0 ;
output Iin83_a ;
output Iin13_a ;
wire Iin27_d_d0 ;
wire Ineurons29_reset_B ;
output Iin29_a ;
wire Iin24_d_d0 ;
output Iin58_a ;
output Iin49_a ;
wire Iin86_d_d0 ;
output Ito_pd_x2_a ;
output Ito_pd_x3_d_d0 ;
wire Iin79_d_d0 ;
output Iin22_a ;
output Iouty5_d_d0 ;
wire Iin15_d_d0 ;
wire Iin1_d_d0 ;
wire Iin34_d_d0 ;
output Iin26_a ;
output Iin25_a ;
output Iin8_a ;
output Iin5_a ;
output Iin45_a ;
output Iin63_a ;
output Iouty4_d_d0 ;
output Ito_pd_x13_d_d0 ;
output Iin68_a ;
output Ito_pd_x4_d_d0 ;
wire Iin60_d_d0 ;
output Iin75_a ;
output Iin23_a ;
wire Iin10_d_d0 ;
output Ioutx14_d_d0 ;
wire Iin57_d_d0 ;
output Iin0_a ;
wire Iin45_d_d0 ;
output Iin84_a ;
wire Ioutx13_a ;
wire Ioutx1_a ;
wire Iin9_d_d0 ;
wire Iouty1_a ;
output Ito_pd_y3_d_d0 ;
wire Iin80_d_d0 ;
output Ioutx10_d_d0 ;
wire Iin61_d_d0 ;
wire Iin0_d_d0 ;
wire Iin66_d_d0 ;
output Ito_pd_x5_d_d0 ;
wire Iin81_d_d0 ;
wire Iin53_d_d0 ;
output Ito_pd_y4_d_d0 ;
wire Iin89_d_d0 ;
output Iin89_a ;
wire Iin36_d_d0 ;
wire Iin16_d_d0 ;
wire Iin76_d_d0 ;
output Iin2_a ;
output Ito_pd_x10_d_d0 ;
wire Iin28_d_d0 ;
output Iin33_a ;
output Iin39_a ;
output Iin34_a ;
output Iin41_a ;
output Ito_pd_x6_d_d0 ;
output Iin50_a ;
wire Iin37_d_d0 ;
wire Iin51_d_d0 ;
output Iin78_a ;
wire Iin17_d_d0 ;
output Ito_pd_y0_d_d0 ;
output Iin30_a ;
wire Ineurons14_reset_B ;
output Ioutx0_d_d0 ;
output Iin35_a ;
output Iin57_a ;
wire Iin75_d_d0 ;
output Ito_pd_x1_a ;
output Iin37_a ;
wire Ineurons59_reset_B ;
output Iin10_a ;
wire Iin38_d_d0 ;
output Iin7_a ;
output Ito_pd_x4_a ;
output Iin36_a ;
wire Iin82_d_d0 ;
output Iouty3_d_d0 ;
output Ioutx6_d_d0 ;
wire Iin43_d_d0 ;
wire Iin65_d_d0 ;
output Iin24_a ;
output Iin38_a ;
output Iin86_a ;
wire reset_B;
output Iin18_a ;
output Ito_pd_x14_d_d0 ;
output Iin77_a ;
wire Iin29_d_d0 ;
wire Ineurons44_reset_B ;
output Iin48_a ;
output Ito_pd_x11_d_d0 ;
output Ito_pd_y1_a ;
output Ito_pd_x1_d_d0 ;
output Iin64_a ;
wire Iin77_d_d0 ;
output Iin17_a ;
wire Iin19_d_d0 ;
output Ito_pd_x14_a ;
output Iin3_a ;
output Ito_pd_x12_d_d0 ;
wire Ioutx0_a ;
wire Iin18_d_d0 ;
output Ito_pd_y5_a ;
wire Iin30_d_d0 ;
output Ito_pd_x0_a ;
output Iin81_a ;
output Ioutx3_d_d0 ;
wire Iin48_d_d0 ;
output Iin85_a ;
output Iin19_a ;
wire Iin17_d_d0 ;
wire Iin16_d_d0 ;
wire Iin31_d_d0 ;
output Ito_pd_y4_a ;
wire Iouty3_a ;
wire Iin39_d_d0 ;
wire Iin62_d_d0 ;
output Ito_pd_x3_a ;
output Iin58_a ;
output Iin42_a ;
output Iin45_a ;
wire Iin57_d_d0 ;
output Iin36_a ;
wire Iin83_d_d0 ;
wire Iin77_d_d0 ;
output Iin8_a ;
output Ito_pd_x14_d_d0 ;
output Iin53_a ;
output Iin54_a ;
output Iin55_a ;
output Iin70_a ;
output Ioutx5_d_d0 ;
output Ioutx4_d_d0 ;
wire Iin50_d_d0 ;
wire Iin71_d_d0 ;
wire Ioutx4_a ;
output Iin5_a ;
wire Iin63_d_d0 ;
wire Iin89_d_d0 ;
output Ito_pd_y3_a ;
wire Ioutx7_a ;
output Iin31_a ;
output Iin71_a ;
wire Iin14_d_d0 ;
output Ito_pd_x9_d_d0 ;
wire Iin8_d_d0 ;
output Ito_pd_y3_a ;
output Ito_pd_x7_d_d0 ;
wire Iin83_d_d0 ;
output Iin14_a ;
output Ito_pd_x6_a ;
wire Iin84_d_d0 ;
output Ito_pd_y2_d_d0 ;
wire Iin42_d_d0 ;
output Ito_pd_x9_a ;
wire Iin5_d_d0 ;
wire Iin35_d_d0 ;
output Ito_pd_x8_a ;
output Ioutx9_d_d0 ;
output Iin46_a ;
wire Iin54_d_d0 ;
wire Ioutx3_a ;
output Iin76_a ;
output Iin32_a ;
wire Iin20_d_d0 ;
wire Iin49_d_d0 ;
output Ito_pd_x5_a ;
output Ito_pd_x8_d_d0 ;
wire Ioutx8_a ;
output Ito_pd_x0_d_d0 ;
output Iin69_a ;
output Ito_pd_x3_a ;
output Iin41_a ;
output Ito_pd_x0_a ;
output Ito_pd_x12_d_d0 ;
wire Iin43_d_d0 ;
output Iin70_a ;
output Iin68_a ;
output Iin88_a ;
output Ito_pd_x6_d_d0 ;
output Iin50_a ;
output Iin29_a ;
output Ioutx7_d_d0 ;
wire Ioutx10_a ;
wire Iin87_d_d0 ;
wire Iin22_d_d0 ;
output Iin47_a ;
wire Iin32_d_d0 ;
output Iin12_a ;
wire Ioutx2_a ;
output Iin20_a ;
output Ito_pd_x12_a ;
wire Ineurons74_reset_B ;
wire Iin42_d_d0 ;
output Iin74_a ;
wire Ioutx0_a ;
wire Iin29_d_d0 ;
output Iin32_a ;
wire Iin37_d_d0 ;
wire Iin56_d_d0 ;
wire reset_B;
wire Ioutx9_a ;
output Ito_pd_x2_d_d0 ;
wire Ioutx14_a ;
wire Iin10_d_d0 ;
output Iin1_a ;
output Iin39_a ;
wire Iin86_d_d0 ;
output Ito_pd_x11_a ;
output Ito_pd_y0_d_d0 ;
wire Iin54_d_d0 ;
wire Iin75_d_d0 ;
output Iin25_a ;
output Ito_pd_x13_a ;
wire Iin9_d_d0 ;
wire Iin65_d_d0 ;
wire Iin79_d_d0 ;
output Iin21_a ;
output Iin44_a ;
output Ioutx10_d_d0 ;
output Iin34_a ;
output Iouty2_d_d0 ;
wire Iouty4_a ;
output Ito_pd_x7_d_d0 ;
wire Iin36_d_d0 ;
wire Ineurons59_reset_B ;
output Ito_pd_x1_a ;
output Iin46_a ;
output Ito_pd_x7_a ;
output Iin64_a ;
output Iin83_a ;
output Ito_pd_x1_d_d0 ;
output Ito_pd_x8_d_d0 ;
output Ioutx1_d_d0 ;
output Iin49_a ;
output Ito_pd_y4_d_d0 ;
output Iin17_a ;
wire Iin73_d_d0 ;
wire Iin6_d_d0 ;
output Ito_pd_x4_d_d0 ;
wire Iin55_d_d0 ;
wire Iin80_d_d0 ;
output Iin9_a ;
wire Iin8_d_d0 ;
wire Iin71_d_d0 ;
wire Iin61_d_d0 ;
output Iin2_a ;
wire Ineurons89_reset_B ;
wire Iin15_d_d0 ;
output Iin30_a ;
wire Iin0_d_d0 ;
wire Iouty0_a ;
output Iin27_a ;
wire Iin20_d_d0 ;
output Ito_pd_y2_a ;
wire Iin34_d_d0 ;
output Iin86_a ;
output Ito_pd_x13_d_d0 ;
wire Iin30_d_d0 ;
wire Iouty5_a ;
wire Iin41_d_d0 ;
wire Iouty1_a ;
output Iin4_a ;
wire Irsb5_in ;
wire Ineurons44_reset_B ;
wire Iin13_d_d0 ;
output Iin89_a ;
wire Iin2_d_d0 ;
output Iin76_a ;
wire Iin49_d_d0 ;
output Iin10_a ;
output Ito_pd_x11_d_d0 ;
wire Iin11_d_d0 ;
output Iin37_a ;
output Iin61_a ;
wire Iin38_d_d0 ;
output Ito_pd_y5_d_d0 ;
wire Ioutx11_a ;
wire Ioutx2_a ;
output Iin24_a ;
output Iin15_a ;
output Ioutx6_d_d0 ;
output Iin80_a ;
wire Iin21_d_d0 ;
output Ito_pd_x12_a ;
output Iin7_a ;
output Ioutx8_d_d0 ;
wire Iin22_d_d0 ;
wire Iin19_d_d0 ;
output Iin52_a ;
output Ioutx2_d_d0 ;
wire Iin51_d_d0 ;
output Iin72_a ;
output Ioutx0_d_d0 ;
output Iin16_a ;
output Ioutx13_d_d0 ;
wire Iin58_d_d0 ;
output Iin66_a ;
output Iouty1_d_d0 ;
wire Iin33_d_d0 ;
output Iin80_a ;
output Ito_pd_y2_a ;
wire Iin68_d_d0 ;
wire Iin72_d_d0 ;
wire Ioutx9_a ;
output Iin15_a ;
output Iin1_a ;
output Ioutx11_d_d0 ;
wire Iin56_d_d0 ;
wire Iin40_d_d0 ;
output Iin88_a ;
output Iin40_a ;
output Iin42_a ;
output Iin43_a ;
output Ito_pd_x0_d_d0 ;
wire Iin41_d_d0 ;
wire Ioutx14_a ;
output Iin74_a ;
output Iin87_a ;
output Iin28_a ;
output Iin16_a ;
output Iin4_a ;
wire Iin73_d_d0 ;
wire Ioutx7_a ;
output Iin11_a ;
wire Iouty3_a ;
output Ito_pd_x2_d_d0 ;
output Ito_pd_y1_d_d0 ;
wire Iouty5_a ;
wire Iin64_d_d0 ;
output Iin71_a ;
wire Iin88_d_d0 ;
wire Iin25_d_d0 ;
output Iin72_a ;
output Iin82_a ;
wire Iin31_d_d0 ;
output Ito_pd_x14_a ;
wire Iin12_d_d0 ;
wire Iin52_d_d0 ;
output Iin62_a ;
output Ito_pd_y2_d_d0 ;
output Iin14_a ;
output Iin11_a ;
output Ito_pd_x2_a ;
output Ito_pd_x5_d_d0 ;
output Ito_pd_x9_a ;
output Iin6_a ;
wire Iin68_d_d0 ;
output Iin12_a ;
wire Iin3_d_d0 ;
output Iin26_a ;
output Ito_pd_x8_a ;
output Ito_pd_x6_a ;
wire Ioutx12_a ;
output Iin23_a ;
wire Iin5_d_d0 ;
wire Iin1_d_d0 ;
output Ito_pd_y0_a ;
output Iin43_a ;
output Ioutx4_d_d0 ;
output Ito_pd_y3_d_d0 ;
wire Iin4_d_d0 ;
output Iin48_a ;
wire Ineurons74_reset_B ;
wire Iin72_d_d0 ;
output Iin82_a ;
output Iin84_a ;
wire Ioutx1_a ;
output Iin59_a ;
wire Ioutx8_a ;
wire Iin85_d_d0 ;
output Iin27_a ;
output Ioutx8_d_d0 ;
wire Iin67_d_d0 ;
output Ito_pd_x13_a ;
output Iin75_a ;
wire Iin78_d_d0 ;
output Iin22_a ;
output Ito_pd_x10_a ;
output Iin67_a ;
wire Iin82_d_d0 ;
wire Ineurons29_reset_B ;
wire Iin7_d_d0 ;
output Iin18_a ;
output Ioutx12_d_d0 ;
output Iin20_a ;
output Ito_pd_y1_d_d0 ;
wire Iin35_d_d0 ;
wire Iin62_d_d0 ;
output Iouty3_d_d0 ;
output Iin40_a ;
wire Iin47_d_d0 ;
wire Iin70_d_d0 ;
wire Iin23_d_d0 ;
output Iin81_a ;
output Ito_pd_x10_d_d0 ;
output Ioutx3_d_d0 ;
output Iin63_a ;
wire Iin87_d_d0 ;
wire Iin32_d_d0 ;
output Iin55_a ;
output Iin79_a ;
wire Ioutx13_a ;
wire Iin76_d_d0 ;
output Iin87_a ;
wire Iin44_d_d0 ;
wire Ioutx6_a ;
wire Iin53_d_d0 ;
output Ito_pd_x4_a ;
output Iin54_a ;
wire Iin18_d_d0 ;
wire Iin45_d_d0 ;
wire Iouty2_a ;
output Iin35_a ;
wire Iin64_d_d0 ;
output Iin73_a ;
output Iouty5_d_d0 ;
wire Iin28_d_d0 ;
output Iin13_a ;
output Iin56_a ;
output Iin78_a ;
wire Iin85_d_d0 ;
output Ioutx5_d_d0 ;
output Ioutx11_d_d0 ;
wire Iin60_d_d0 ;
output Iouty1_d_d0 ;
output Ito_pd_x5_a ;
wire Iin67_d_d0 ;
output Iin0_a ;
output Iouty4_d_d0 ;
output Ito_pd_y1_a ;
wire Iin84_d_d0 ;
output Ito_pd_y5_a ;
output Ito_pd_x3_d_d0 ;
output Iin60_a ;
wire Ioutx5_a ;
wire Ineurons14_reset_B ;
wire Iin33_d_d0 ;
wire Ioutx3_a ;
wire Iin26_d_d0 ;
wire Iin81_d_d0 ;
wire Iin40_d_d0 ;
wire Iin50_d_d0 ;
output Iin38_a ;
output Iin51_a ;
wire Iin46_d_d0 ;
wire Iin24_d_d0 ;
output Iin57_a ;
output Iin65_a ;
output Iin28_a ;
output Ioutx9_d_d0 ;
output Ioutx14_d_d0 ;
output Iin47_a ;
wire Iin59_d_d0 ;
wire Iin66_d_d0 ;
wire Iin27_d_d0 ;
output Iin3_a ;
wire Iin74_d_d0 ;
output Iin33_a ;
output Iouty0_d_d0 ;
wire Iin48_d_d0 ;
wire Iin25_d_d0 ;
output Iin66_a ;
// --- instances
BUF_X4 Iout_req_buf_x0 (.y(Ioutx0_d_d0 ), .a(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));

4
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down/netlist/verilog.v

@ -6,10 +6,10 @@ module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, out, v
output out;
// -- signals ---
wire Iinv_y ;
wire out ;
wire in;
wire reset_B;
wire in;
wire Iinv_y ;
// --- instances
A_1N_U_X4 Ipull_down (.n1(in), .y(out), .vdd(vdd), .vss(vss));

42
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_315_4/netlist/verilog.v

@ -19,32 +19,32 @@ module tmpl_0_0dataflow__neuro_0_0ortree_315_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Itmp19 ;
wire Iin0 ;
wire Iin6 ;
wire Itmp17 ;
wire Iin2 ;
wire Iin7 ;
wire Itmp21 ;
wire Itmp23 ;
wire Iin4 ;
wire Iin10 ;
wire Iin7 ;
wire Iin4 ;
wire Iin11 ;
wire Itmp16 ;
wire Itmp15 ;
wire Itmp23 ;
wire Itmp24 ;
wire Iin14 ;
wire Itmp19 ;
wire Iin5 ;
wire Iin9 ;
wire Itmp18 ;
wire Iin8 ;
wire Iin6 ;
wire out ;
wire Iin12 ;
wire Itmp20 ;
wire Itmp17 ;
wire Iin1 ;
wire Iin2 ;
wire Iin0 ;
wire Itmp21 ;
wire Iin3 ;
wire Itmp22 ;
wire Iin12 ;
wire Iin5 ;
wire Itmp24 ;
wire Itmp20 ;
wire Iin14 ;
wire Iin11 ;
wire Iin8 ;
wire out ;
wire Itmp18 ;
wire Itmp15 ;
wire Iin13 ;
wire Iin9 ;
wire Itmp16 ;
// --- instances
OR3_X1 Ior3s0 (.y(Itmp21 ), .a(Iin12 ), .b(Iin13 ), .c(Iin14 ), .vdd(vdd), .vss(vss));

8
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_34_4/netlist/verilog.v

@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0ortree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, v
output out;
// -- signals ---
wire Iin0 ;
wire Itmp4 ;
wire Itmp5 ;
wire out ;
wire Itmp4 ;
wire Iin0 ;
wire Iin3 ;
wire Iin1 ;
wire out ;
wire Iin2 ;
wire Iin1 ;
// --- instances
OR2_X1 Ior2s0 (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

204
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_358_4/netlist/verilog.v

@ -62,118 +62,118 @@ module tmpl_0_0dataflow__neuro_0_0ortree_358_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin36 ;
wire Itmp74 ;
wire Itmp100 ;
wire Itmp103 ;
wire Itmp98 ;
wire Iin54 ;
wire Iin48 ;
wire Iin50 ;
wire Iin19 ;
wire Iin11 ;
wire out ;
wire Iin13 ;
wire Iin3 ;
wire Itmp109 ;
wire Itmp92 ;
wire Iin51 ;
wire Iin33 ;
wire Itmp107 ;
wire Itmp85 ;
wire Iin6 ;
wire Itmp59 ;
wire Itmp86 ;
wire Iin31 ;
wire Iin14 ;
wire Iin8 ;
wire Iin47 ;
wire Itmp67 ;
wire Itmp106 ;
wire Itmp102 ;
wire Iin30 ;
wire Itmp91 ;
wire Iin26 ;
wire Itmp66 ;
wire Itmp88 ;
wire Iin39 ;
wire Iin20 ;
wire Iin12 ;
wire Itmp62 ;
wire Itmp93 ;
wire Iin57 ;
wire Iin53 ;
wire Itmp72 ;
wire Iin15 ;
wire Itmp65 ;
wire Itmp89 ;
wire Iin38 ;
wire Iin34 ;
wire Iin25 ;
wire Iin7 ;
wire Iin56 ;
wire Itmp83 ;
wire Iin46 ;
wire Iin5 ;
wire Iin2 ;
wire Itmp107 ;
wire Iin51 ;
wire Iin40 ;
wire Iin35 ;
wire Iin14 ;
wire Itmp88 ;
wire Iin18 ;
wire Iin41 ;
wire Itmp76 ;
wire Iin34 ;
wire Itmp61 ;
wire Itmp73 ;
wire Iin31 ;
wire Iin8 ;
wire Iin49 ;
wire Iin37 ;
wire Itmp86 ;
wire Itmp97 ;
wire Iin46 ;
wire Iin11 ;
wire Itmp89 ;
wire Iin20 ;
wire Itmp110 ;
wire Itmp92 ;
wire Itmp77 ;
wire Iin10 ;
wire Itmp74 ;
wire Iin25 ;
wire Itmp82 ;
wire Itmp62 ;
wire Itmp100 ;
wire Iin56 ;
wire Iin53 ;
wire Iin44 ;
wire Iin45 ;
wire Iin24 ;
wire Iin19 ;
wire Iin17 ;
wire Itmp105 ;
wire Itmp101 ;
wire Itmp95 ;
wire Itmp87 ;
wire Iin52 ;
wire Iin30 ;
wire Iin28 ;
wire Iin23 ;
wire Iin13 ;
wire Iin4 ;
wire Iin55 ;
wire Iin35 ;
wire Iin29 ;
wire Iin22 ;
wire Iin18 ;
wire Iin0 ;
wire Itmp110 ;
wire Itmp99 ;
wire Iin41 ;
wire Iin23 ;
wire Itmp64 ;
wire Itmp94 ;
wire Iin44 ;
wire Itmp78 ;
wire Iin17 ;
wire Iin4 ;
wire Itmp108 ;
wire Iin2 ;
wire Iin32 ;
wire Iin28 ;
wire Itmp69 ;
wire Itmp106 ;
wire Iin55 ;
wire Iin47 ;
wire Iin49 ;
wire Itmp77 ;
wire Iin5 ;
wire Itmp58 ;
wire Itmp105 ;
wire Itmp84 ;
wire Itmp82 ;
wire Iin45 ;
wire Itmp68 ;
wire Itmp101 ;
wire Itmp96 ;
wire Iin42 ;
wire Itmp70 ;
wire Iin1 ;
wire Itmp79 ;
wire Iin27 ;
wire Iin21 ;
wire Itmp63 ;
wire Iin24 ;
wire Itmp104 ;
wire Iin52 ;
wire Itmp81 ;
wire Itmp76 ;
wire Iin16 ;
wire Iin10 ;
wire Iin43 ;
wire Iin37 ;
wire Itmp71 ;
wire Itmp67 ;
wire Itmp95 ;
wire Itmp90 ;
wire Itmp60 ;
wire Itmp97 ;
wire Iin15 ;
wire out ;
wire Itmp65 ;
wire Iin7 ;
wire Iin1 ;
wire Itmp93 ;
wire Itmp83 ;
wire Iin36 ;
wire Iin26 ;
wire Itmp81 ;
wire Itmp78 ;
wire Itmp85 ;
wire Itmp104 ;
wire Itmp80 ;
wire Itmp75 ;
wire Itmp72 ;
wire Itmp103 ;
wire Itmp99 ;
wire Itmp90 ;
wire Itmp64 ;
wire Iin9 ;
wire Itmp87 ;
wire Iin6 ;
wire Itmp60 ;
wire Itmp108 ;
wire Itmp109 ;
wire Iin43 ;
wire Iin27 ;
wire Itmp71 ;
wire Iin21 ;
wire Iin0 ;
wire Itmp58 ;
wire Iin12 ;
wire Iin50 ;
wire Iin48 ;
wire Iin38 ;
wire Itmp66 ;
wire Itmp63 ;
wire Itmp98 ;
wire Itmp96 ;
wire Itmp94 ;
wire Iin42 ;
wire Itmp79 ;
wire Itmp68 ;
wire Itmp59 ;
wire Iin57 ;
wire Itmp75 ;
wire Iin32 ;
wire Itmp73 ;
wire Itmp70 ;
wire Itmp69 ;
wire Itmp91 ;
wire Iin33 ;
wire Iin3 ;
wire Itmp84 ;
// --- instances
OR3_X1 Ior3s0 (.y(Itmp100 ), .a(Itmp84 ), .b(Itmp85 ), .c(Itmp86 ), .vdd(vdd), .vss(vss));

238
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_364_4/netlist/verilog.v

@ -68,133 +68,133 @@ module tmpl_0_0dataflow__neuro_0_0ortree_364_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Itmp82 ;
wire Iin19 ;
wire Iin60 ;
wire Iin55 ;
wire Iin53 ;
wire Iin7 ;
wire Itmp119 ;
wire Itmp114 ;
wire Iin62 ;
wire Itmp80 ;
wire Itmp72 ;
wire Itmp67 ;
wire Itmp100 ;
wire Iin47 ;
wire Itmp116 ;
wire Iin42 ;
wire Itmp83 ;
wire Itmp77 ;
wire Itmp111 ;
wire Itmp106 ;
wire Itmp88 ;
wire Itmp86 ;
wire Iin43 ;
wire Iin20 ;
wire Iin4 ;
wire Itmp117 ;
wire Iin50 ;
wire Iin39 ;
wire Itmp109 ;
wire Iin54 ;
wire Itmp74 ;
wire Itmp125 ;
wire Itmp101 ;
wire Itmp94 ;
wire Iin48 ;
wire Iin44 ;
wire Iin13 ;
wire Iin2 ;
wire Itmp121 ;
wire Itmp92 ;
wire Iin52 ;
wire Iin41 ;
wire Itmp115 ;
wire Itmp111 ;
wire Iin57 ;
wire Itmp84 ;
wire Iin12 ;
wire Itmp69 ;
wire Iin5 ;
wire Itmp96 ;
wire Iin49 ;
wire Iin46 ;
wire Iin28 ;
wire Iin15 ;
wire Itmp123 ;
wire Itmp122 ;
wire Iin40 ;
wire Iin36 ;
wire Iin26 ;
wire Itmp76 ;
wire Itmp102 ;
wire Iin14 ;
wire Iin59 ;
wire Iin31 ;
wire Iin16 ;
wire Iin45 ;
wire Iin35 ;
wire Itmp95 ;
wire Itmp93 ;
wire Iin30 ;
wire Itmp78 ;
wire out ;
wire Itmp85 ;
wire Iin0 ;
wire Itmp64 ;
wire Itmp107 ;
wire Iin56 ;
wire Iin24 ;
wire Itmp112 ;
wire Itmp91 ;
wire Itmp87 ;
wire Iin37 ;
wire Itmp98 ;
wire Iin58 ;
wire Iin51 ;
wire Itmp81 ;
wire Iin18 ;
wire Itmp73 ;
wire Iin8 ;
wire Iin32 ;
wire Iin11 ;
wire Itmp68 ;
wire Itmp66 ;
wire Itmp105 ;
wire Itmp90 ;
wire Iin10 ;
wire Itmp65 ;
wire Itmp120 ;
wire Itmp113 ;
wire Itmp108 ;
wire Iin63 ;
wire Iin61 ;
wire Itmp79 ;
wire Itmp110 ;
wire Iin33 ;
wire Iin22 ;
wire Iin21 ;
wire Itmp109 ;
wire Iin59 ;
wire Itmp85 ;
wire Iin20 ;
wire Itmp71 ;
wire Itmp89 ;
wire Iin9 ;
wire Iin5 ;
wire Itmp64 ;
wire Itmp115 ;
wire Iin45 ;
wire Itmp86 ;
wire Iin38 ;
wire Iin34 ;
wire Itmp70 ;
wire Iin17 ;
wire Iin3 ;
wire Iin1 ;
wire Itmp118 ;
wire Itmp97 ;
wire Iin27 ;
wire Iin6 ;
wire Itmp104 ;
wire Itmp103 ;
wire Iin29 ;
wire Iin25 ;
wire Itmp124 ;
wire Itmp70 ;
wire Itmp79 ;
wire Iin44 ;
wire Iin21 ;
wire Iin14 ;
wire Itmp119 ;
wire Itmp108 ;
wire Itmp99 ;
wire Iin23 ;
wire Itmp66 ;
wire Iin0 ;
wire Itmp84 ;
wire Iin16 ;
wire Itmp95 ;
wire Iin61 ;
wire Iin49 ;
wire Itmp81 ;
wire Iin28 ;
wire Itmp75 ;
wire Itmp98 ;
wire Iin60 ;
wire Iin4 ;
wire Itmp106 ;
wire Iin50 ;
wire Iin41 ;
wire Iin33 ;
wire Iin2 ;
wire Itmp118 ;
wire Iin37 ;
wire Iin30 ;
wire Iin13 ;
wire Iin6 ;
wire Itmp107 ;
wire Iin51 ;
wire Iin47 ;
wire Itmp82 ;
wire Iin24 ;
wire Itmp73 ;
wire Itmp87 ;
wire Iin34 ;
wire Itmp72 ;
wire Itmp69 ;
wire Iin48 ;
wire Itmp78 ;
wire Iin23 ;
wire Iin11 ;
wire Itmp103 ;
wire Itmp116 ;
wire Itmp101 ;
wire Iin58 ;
wire Iin42 ;
wire Itmp74 ;
wire Itmp124 ;
wire Itmp121 ;
wire Iin62 ;
wire Itmp94 ;
wire Iin53 ;
wire Itmp90 ;
wire Iin46 ;
wire Iin27 ;
wire Iin15 ;
wire out ;
wire Itmp123 ;
wire Itmp92 ;
wire Iin40 ;
wire Iin25 ;
wire Itmp97 ;
wire Iin35 ;
wire Itmp77 ;
wire Iin9 ;
wire Itmp114 ;
wire Itmp89 ;
wire Iin43 ;
wire Itmp80 ;
wire Itmp122 ;
wire Itmp105 ;
wire Iin63 ;
wire Itmp93 ;
wire Iin56 ;
wire Itmp110 ;
wire Itmp104 ;
wire Iin32 ;
wire Iin19 ;
wire Itmp112 ;
wire Iin52 ;
wire Itmp68 ;
wire Itmp100 ;
wire Itmp88 ;
wire Iin31 ;
wire Iin10 ;
wire Itmp102 ;
wire Iin7 ;
wire Itmp125 ;
wire Itmp120 ;
wire Itmp76 ;
wire Iin22 ;
wire Iin3 ;
wire Itmp113 ;
wire Itmp91 ;
wire Iin36 ;
wire Itmp65 ;
wire Iin26 ;
wire Iin18 ;
wire Iin12 ;
wire Itmp67 ;
wire Iin1 ;
wire Itmp96 ;
wire Iin55 ;
wire Iin54 ;
wire Iin39 ;
wire Itmp83 ;
wire Iin17 ;
// --- instances
OR2_X1 Ior2s0 (.y(Itmp64 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

14
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_38_4/netlist/verilog.v

@ -13,20 +13,20 @@ module tmpl_0_0dataflow__neuro_0_0ortree_38_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
// -- signals ---
wire Itmp11 ;
wire Iin4 ;
wire Iin2 ;
wire Iin6 ;
wire Itmp8 ;
wire Itmp13 ;
wire Iin7 ;
wire Itmp10 ;
wire Iin3 ;
wire Iin5 ;
wire Iin2 ;
wire Itmp9 ;
wire Iin4 ;
wire Iin1 ;
wire Itmp12 ;
wire out ;
wire Itmp9 ;
wire Itmp10 ;
wire Itmp13 ;
wire Iin0 ;
wire out ;
wire Itmp12 ;
// --- instances
OR2_X1 Ior2s0 (.y(Itmp8 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

248
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4/netlist/verilog.v

@ -108,144 +108,144 @@ module tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Ii
input reset_B;
// -- signals ---
wire Iin_d_d14_d1 ;
wire Iout_vtree_in_d8_d0 ;
wire Iout_vtree_in_d10_d0 ;
wire Iout_vtree_in_d13_d0 ;
output Iout_d28 ;
output Iout_d14 ;
wire Iout_vtree_in_d30_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d23 ;
output Iout_d25 ;
wire Iin_d_d9_d0 ;
output Iin_v ;
output Iout_d21 ;
wire Idly_in ;
wire Iin_d_d5_d1 ;
wire Iin_d_d12_d0 ;
wire Iout_vtree_in_d26_d0 ;
wire Iout_vtree_in_d27_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d13_d0 ;
output Iout_d30 ;
output Iout_d2 ;
wire Iout_vtree_in_d18_d0 ;
output Iout_d15 ;
output Iout_d0 ;
wire Iout_vtree_in_d29_d0 ;
output Iout_d13 ;
output Iout_d3 ;
wire Iout_vtree_in_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Iout_vtree_in_d21_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d29_d0 ;
wire Iout_vtree_in_d30_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d27 ;
output Iout_d20 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d28_d1 ;
wire Iout_vtree_in_d2_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d1 ;
wire Iout_vtree_in_d20_d0 ;
wire Idly_cfg0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d24 ;
wire reset_B;
wire Iin_d_d30_d0 ;
output Iout_d26 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d31_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d19_d0 ;
wire Iout_vtree_in_d14_d0 ;
wire Iout_vtree_in_d28_d0 ;
wire Iin_d_d10_d0 ;
wire Idly_cfg3 ;
wire Iin_d_d0_d0 ;
wire Iout_vtree_in_d16_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d6_d0 ;
output Iout_d12 ;
output Iout_d6 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d12_d1 ;
wire Iout_vtree_in_d5_d0 ;
output Iout_d9 ;
wire Iout_vtree_in_d22_d0 ;
output Iout_d18 ;
wire Idly_cfg2 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d13_d0 ;
output Iout_d19 ;
wire Idly_cfg1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d26_d0 ;
output Iout_d5 ;
wire Iout_vtree_in_d19_d0 ;
wire Iout_vtree_in_d24_d0 ;
output Iout_d31 ;
wire Iout_vtree_in_d31_d0 ;
output Iout_r ;
output Iout_d4 ;
wire Iout_vtree_in_d17_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d26_d1 ;
wire Iout_vtree_in_d0_d0 ;
wire Iout_a ;
wire Iin_d_d15_d0 ;
wire Iin_d_d30_d1 ;
wire Iout_vtree_in_d12_d0 ;
wire Iout_vtree_in_d1_d0 ;
output Iout_d7 ;
output Iout_d17 ;
wire Iin_d_d4_d1 ;
output Iout_d16 ;
wire Iout_vtree_in_d25_d0 ;
output Iout_d10 ;
wire Iout_vtree_in_d15_d0 ;
wire Iin_d_d25_d1 ;
wire Iout_vtree_in_d4_d0 ;
output Iout_d11 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d29 ;
wire Iin_d_d16_d0 ;
wire Iout_vtree_in_d7_d0 ;
wire Iout_vtree_in_d9_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d29_d1 ;
output Iout_d27 ;
wire Iout_vtree_in_d31_d0 ;
wire Iout_vtree_in_d11_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d6 ;
output Iout_d28 ;
output Iout_d31 ;
wire Idly_in ;
wire Iin_d_d0_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d9_d1 ;
output Iout_d9 ;
wire Iin_d_d7_d1 ;
output Iout_d0 ;
wire Iout_vtree_in_d17_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d21_d0 ;
wire Iout_vtree_in_d26_d0 ;
wire Iout_vtree_in_d28_d0 ;
wire Iin_d_d20_d1 ;
output Iin_a ;
output Iout_d22 ;
wire Iin_d_d29_d1 ;
wire Iout_vtree_in_d11_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d16_d0 ;
output Iout_d30 ;
wire Iin_d_d31_d0 ;
wire Iout_vtree_in_d10_d0 ;
wire Iin_d_d17_d1 ;
wire Iout_vtree_in_d1_d0 ;
output Iout_d11 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d1 ;
output Iout_d8 ;
wire Iout_vtree_in_d23_d0 ;
output Iout_d29 ;
wire Iin_d_d20_d0 ;
output Iout_d10 ;
wire Iout_a ;
wire Iin_d_d4_d1 ;
wire Iout_vtree_in_d0_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d15_d0 ;
wire Iout_vtree_in_d3_d0 ;
wire Iin_d_d20_d0 ;
wire Iout_vtree_in_d25_d0 ;
wire Iin_d_d15_d1 ;
wire Iout_vtree_in_d29_d0 ;
output Iout_d12 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d31_d1 ;
wire Iout_vtree_in_d5_d0 ;
output Iout_d17 ;
wire Iout_vtree_in_d22_d0 ;
wire Iout_vtree_in_d23_d0 ;
wire Idly_cfg3 ;
wire Iout_vtree_in_d2_d0 ;
output Iout_r ;
wire Iin_d_d0_d0 ;
wire Iout_vtree_in_d14_d0 ;
wire Iout_vtree_in_d15_d0 ;
wire Iin_d_d22_d1 ;
wire Iout_vtree_in_d4_d0 ;
output Iout_d19 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d30_d0 ;
output Iout_d20 ;
output Iout_d24 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d28_d0 ;
output Iout_d3 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d24_d0 ;
wire Iout_vtree_in_d18_d0 ;
output Iout_d14 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d25_d0 ;
wire Iout_vtree_in_d21_d0 ;
output Iout_d13 ;
output Iout_d26 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d11_d1 ;
wire reset_B;
wire Iout_vtree_in_d12_d0 ;
wire Iout_vtree_in_d13_d0 ;
output Iin_v ;
output Iout_d15 ;
wire Iout_vtree_in_d16_d0 ;
wire Idly_cfg2 ;
wire Iin_d_d19_d0 ;
output Iout_d16 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d31_d0 ;
output Iout_d22 ;
output Iout_d5 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d26_d0 ;
wire Iout_vtree_in_d9_d0 ;
output Iout_d25 ;
wire Iin_d_d25_d1 ;
output Iout_d18 ;
output Iout_d23 ;
wire Idly_cfg0 ;
output Iout_d4 ;
wire Iout_vtree_in_d20_d0 ;
wire Iout_vtree_in_d24_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d7 ;
wire Iout_vtree_in_d8_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d24_d1 ;
wire Idly_cfg1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d14_d1 ;
wire Iout_vtree_in_d19_d0 ;
output Iout_d21 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly (.out(Iout_r ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));

202
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4/netlist/verilog.v

@ -98,112 +98,112 @@ module tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4(Iin_d_d0_d0 ,
input reset_B;
// -- signals ---
wire Iin_d_d17_d0 ;
output Iout_d9_d0 ;
output Iout_d0_d1 ;
wire Iin_d_d1_d1 ;
wire _flushBX ;
wire Iin_d_d9_d1 ;
output Iout_d12_d0 ;
output Iout_d10_d0 ;
output Iout_d2_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d19_d1 ;
output Iout_d15_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d13_d1 ;
wire Ireset_sb_in ;
output Iout_d1_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d11_d0 ;
wire _en ;
output Iout_d7_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d2_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d18_d0 ;
output Iout_d14_d1 ;
output Iout_d5_d1 ;
wire _out_v ;
wire Iin_d_d0_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d12_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d6_d1 ;
output Iout_d21_d1 ;
output Iout_d21_d0 ;
output Iout_d20_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d11_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d10_d1 ;
wire _flush ;
output Iout_d13_d1 ;
output Iout_d3_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d14_d0 ;
output Iout_d7_d0 ;
wire Iin_d_d2_d0 ;
output Iout_d22_d1 ;
output Iout_d15_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d8_d1 ;
output Iout_d0_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d11_d1 ;
output Iout_d18_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d3_d1 ;
wire I_resetX0 ;
output Iin_a ;
wire IA_flush_sr_B ;
output Iout_d8_d1 ;
wire Iin_d_d3_d0 ;
wire reset_B;
output Iout_d22_d0 ;
output Iout_d17_d0 ;
output Iout_d16_d1 ;
wire _out_vB ;
wire Iin_d_d4_d0 ;
wire Iin_d_d17_d1 ;
wire _enBX ;
output Iout_d11_d0 ;
output Iout_d10_d1 ;
output Iout_d4_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d17_d1 ;
output Iout_d6_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d15_d0 ;
output Iout_d16_d0 ;
output Iout_d6_d1 ;
wire Ien_inv_y ;
output Iout_d20_d1 ;
output Iout_d13_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d4_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d15_d1 ;
output Iout_d3_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d14_d0 ;
wire Iin_d_d0_d1 ;
wire reset_B;
output Iout_d19_d0 ;
output Iout_d9_d1 ;
output Iout_d18_d0 ;
output Iout_d6_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d12_d0 ;
output Iout_d7_d1 ;
wire Iin_d_d6_d1 ;
wire Iflush_inv_y ;
output Iout_d19_d1 ;
output Iout_d8_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d5_d0 ;
output Iout_d20_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d10_d0 ;
wire Ireset_sb_in ;
output Iout_d15_d1 ;
output Iout_d1_d1 ;
wire _out_v ;
wire Iin_d_d22_d0 ;
output Iout_d21_d0 ;
output Iout_d10_d0 ;
output Iout_d9_d1 ;
output Iout_d8_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d5_d1 ;
output Iout_d22_d0 ;
output Iout_d21_d1 ;
output Iout_d11_d0 ;
output Iout_d4_d0 ;
output Iout_d3_d1 ;
output Iout_d2_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d1_d1 ;
wire _flush ;
wire Iin_d_d12_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d0_d1 ;
wire _en ;
output Iout_d1_d0 ;
wire _enBX ;
output Iout_d19_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d13_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d2_d1 ;
wire Ien_inv_y ;
wire Iin_d_d17_d1 ;
wire _out_vB ;
wire Iin_d_d1_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d3_d1 ;
output Iin_a ;
output Iout_d16_d0 ;
output Iout_d5_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d8_d0 ;
wire _flushBX ;
output Iout_d15_d0 ;
output Iout_d6_d1 ;
output Iout_d5_d0 ;
output Iout_d4_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d13_d1 ;
wire I_resetX0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d22_d1 ;
output Iout_d8_d0 ;
output Iout_d7_d0 ;
output Iout_d0_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d16_d1 ;
wire IA_flush_sr_B ;
output Iout_d10_d1 ;
output Iout_d3_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d8_d1 ;
output Iout_d20_d1 ;
wire Iin_d_d20_d1 ;
output Iout_d17_d1 ;
output Iout_d16_d1 ;
output Iout_d9_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d12_d1 ;
output Iout_d2_d1 ;
output Iout_d17_d0 ;
output Iout_d13_d1 ;
output Iout_d11_d1 ;
wire Iin_d_d9_d1 ;
output Iout_d18_d1 ;
output Iout_d14_d1 ;
// --- instances
INV_X2 Iout_val_inv (.y(_out_vB), .a(_out_v), .vdd(vdd), .vss(vss));

12606
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0register__wr__array_36_723_764_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_313_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_313_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X4 Ibuf4 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_315_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X6 Ibuf6 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_323_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_323_4(in, Iout0 , vdd, vss);
// -- signals ---
wire in;
output Iout0 ;
wire in;
// --- instances
BUF_X8 Ibuf8 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_324_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_324_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X8 Ibuf8 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_326_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_326_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X8 Ibuf8 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_330_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_330_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_346_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_346_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_347_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_347_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_348_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_348_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_34_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_34_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X1 Ibuf1 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist/master.tag Normal file

@ -0,0 +1,2 @@
-- Master.tag File, Rev:1.0
verilog.v

13
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_35_4/netlist/verilog.v Normal file

@ -0,0 +1,13 @@
module tmpl_0_0dataflow__neuro_0_0sigbuf_35_4(in, Iout0 , vdd, vss);
input vdd;
input vss;
input in;
// -- signals ---
output Iout0 ;
wire in;
// --- instances
BUF_X2 Ibuf2 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_365_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_365_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_370_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_370_4(in, Iout0 , vdd, vss);
// -- signals ---
wire in;
output Iout0 ;
wire in;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

50
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_715_4/netlist/verilog.v

@ -33,36 +33,36 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_715_4(Iin0 , Iin1 , Iin2
// -- signals ---
wire Iin14 ;
output Iout6 ;
output Iout14 ;
wire Iin13 ;
output Iout3 ;
wire Iin3 ;
wire Iin4 ;
wire Iin13 ;
wire Iin8 ;
output Iout4 ;
output Iout10 ;
output Iout5 ;
wire Iin2 ;
output Iout13 ;
wire Iin6 ;
wire Iin5 ;
output Iout8 ;
output Iout2 ;
output Iout12 ;
wire Iin1 ;
wire Iin11 ;
wire Iin10 ;
output Iout9 ;
output Iout0 ;
wire Iin0 ;
wire Iin7 ;
output Iout1 ;
output Iout12 ;
output Iout11 ;
wire Iin9 ;
wire Iin12 ;
output Iout3 ;
output Iout9 ;
output Iout5 ;
output Iout7 ;
output Iout6 ;
wire Iin6 ;
wire Iin2 ;
wire Iin14 ;
output Iout8 ;
wire Iin10 ;
wire Iin5 ;
output Iout4 ;
output Iout1 ;
output Iout13 ;
wire Iin7 ;
wire Iin9 ;
output Iout10 ;
output Iout14 ;
wire Iin3 ;
wire Iin0 ;
output Iout0 ;
wire Iin12 ;
wire Iin11 ;
output Iout2 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Isb0 (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));

50
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_74_4/netlist/verilog.v

@ -33,36 +33,36 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_74_4(Iin0 , Iin1 , Iin2
// -- signals ---
output Iout1 ;
wire Iin14 ;
output Iout12 ;
output Iout9 ;
output Iout0 ;
output Iout4 ;
output Iout11 ;
wire Iin6 ;
wire Iin13 ;
output Iout5 ;
wire Iin10 ;
output Iout7 ;
wire Iin12 ;
wire Iin1 ;
output Iout14 ;
wire Iin11 ;
output Iout13 ;
output Iout3 ;
output Iout8 ;
wire Iin12 ;
output Iout4 ;
output Iout12 ;
wire Iin4 ;
wire Iin13 ;
output Iout11 ;
output Iout10 ;
wire Iin0 ;
wire Iin11 ;
wire Iin7 ;
wire Iin9 ;
output Iout7 ;
wire Iin3 ;
output Iout9 ;
wire Iin1 ;
output Iout0 ;
output Iout6 ;
wire Iin2 ;
output Iout5 ;
wire Iin5 ;
wire Iin6 ;
output Iout2 ;
output Iout14 ;
wire Iin8 ;
wire Iin0 ;
output Iout10 ;
wire Iin9 ;
wire Iin14 ;
wire Iin7 ;
wire Iin4 ;
output Iout2 ;
wire Iin3 ;
wire Iin5 ;
output Iout8 ;
output Iout6 ;
output Iout1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_34_4 Isb0 (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));

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