fixed decoder_2d_hybrid unit test

test/unit_tests/decoder_2d_hybrid/test.act

@@ -39,7 +39,7 @@ open std::data;
 
 open tmpl::dataflow_neuro;
 
-defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
+defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en, ack_disable){
     bool _reset_B; 
     prs {
         Reset => _reset_B-
@@ -48,38 +48,55 @@ defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], h
     supply.vdd = Vdd;
     supply.vss = GND;
 
-    decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .dly_cfg = dly_cfg, .hs_en = hs_en,
+    decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .dly_cfg = dly_cfg, .hs_en = hs_en, .ack_disable = ack_disable,
         .reset_B = _reset_B, .supply = supply);
 
-    // model the synapse as having automatic pulldown of ack.
+    // Dummy synapses to perform the handshaking.
-    INV_X1 synapses[8];
+    // They consist of a grid of ANDs and pulldowns, and have the "synapses" exposed,\
-    AND2_X1 req_and2s[8];
+    // which would be the pulse extenders (which we thus short here)
 
-    pint index;
 
-    PULLDOWN_X4 synapses2[8];
+    decoder_2d_synapse_hs<2,4> syn_hs(.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
-    (i:4:
+        .out_ackB_decoder = decoder.in_ackB_decoder,
-        (j:2:
+        .to_pu = decoder.to_pu,
-            index = i + 4*j;
+        .synapses = out,
+        .supply = supply);
 
-            req_and2s[index].a = decoder.out_req_x[index];
-            req_and2s[index].b = decoder.out_req_y[index];
 
-            // synapses[index].a = decoder.out[index].r;
-            synapses[index].a = req_and2s[index].y;
-            synapses2[index].a = synapses[index].y; 
-            synapses2[index].y = decoder.out[index].a;
 
-            synapses[index].vss = supply.vss;
+    // (i:8: syn_hs.synapses[i].a = syn_hs.synapses[i].r;)
-            synapses[index].vdd = supply.vdd;
-            synapses2[index].vss = supply.vss;
-            synapses2[index].vdd = supply.vdd;            
-            req_and2s[index].vss = supply.vss;
-            req_and2s[index].vdd = supply.vdd;
 
-        )
+    // // model the synapse as having automatic pulldown of ack.
+    // INV_X1 synapses[8];
+    // AND2_X1 req_and2s[8];
+
+    // pint index;
+
+    // PULLDOWN_X4 synapses2[8];
+    // (i:4:
+    //     (j:2:
+    //         index = i + 4*j;
+
+    //         req_and2s[index].a = decoder.out_req_x[index];
+    //         req_and2s[index].b = decoder.out_req_y[index];
+
+    //         // synapses[index].a = decoder.out[index].r;
+    //         synapses[index].a = req_and2s[index].y;
+    //         synapses2[index].a = synapses[index].y; 
+    //         synapses2[index].y = decoder.out[index].a;
+
+    //         synapses[index].vss = supply.vss;
+    //         synapses[index].vdd = supply.vdd;
+    //         synapses2[index].vss = supply.vss;
+    //         synapses2[index].vdd = supply.vdd;            
+    //         req_and2s[index].vss = supply.vss;
+    //         req_and2s[index].vdd = supply.vdd;
+
+    //     )
         
-    )
+    // )
+
+
 }
 
 

test/unit_tests/decoder_2d_hybrid/test.prsim

@@ -8,7 +8,7 @@ set e.out[4].a 0
 set e.out[5].a 0
 set e.out[6].a 0
 set e.out[7].a 0
-
+cycle
 set e.dly_cfg[0] 0
 set e.dly_cfg[1] 0
 set e.dly_cfg[2] 0
@@ -16,6 +16,8 @@ set e.dly_cfg[3] 0
 
 set e.hs_en 1
 
+set e.ack_disable 0
+
 set-qdi-channel-neutral "e.in" 3
 set Reset 1
 
@@ -58,16 +60,15 @@ assert e.out[6].r 0
 assert e.out[7].r 0
 assert e.in.a 0
 assert e.in.v 0
-assert e.out[0].a 0
+set e.out[0].a 0
-assert e.out[1].a 0
+set e.out[1].a 0
-assert e.out[2].a 0
+set e.out[2].a 0
-assert e.out[3].a 0
+set e.out[3].a 0
-assert e.out[4].a 0
+set e.out[4].a 0
-assert e.out[5].a 0
+set e.out[5].a 0
-assert e.out[6].a 0
+set e.out[6].a 0
-assert e.out[7].a 0
+set e.out[7].a 0
-
+cycle
-
 
 
 
@@ -102,15 +103,15 @@ assert e.out[6].r 0
 assert e.out[7].r 0
 assert e.in.a 0
 assert e.in.v 0
-assert e.out[0].a 0
+set e.out[0].a 0
-assert e.out[1].a 0
+set e.out[1].a 0
-assert e.out[2].a 0
+set e.out[2].a 0
-assert e.out[3].a 0
+set e.out[3].a 0
-assert e.out[4].a 0
+set e.out[4].a 0
-assert e.out[5].a 0
+set e.out[5].a 0
-assert e.out[6].a 0
+set e.out[6].a 0
-assert e.out[7].a 0
+set e.out[7].a 0
-
+cycle
 
 
 system "echo '[] Sending in a 1 packet'"
@@ -140,15 +141,15 @@ assert e.out[5].r 0
 assert e.out[6].r 0
 assert e.out[7].r 0
 
-assert e.out[0].a 0
+set e.out[0].a 0
-assert e.out[1].a 0
+set e.out[1].a 0
-assert e.out[2].a 0
+set e.out[2].a 0
-assert e.out[3].a 0
+set e.out[3].a 0
-assert e.out[4].a 0
+set e.out[4].a 0
-assert e.out[5].a 0
+set e.out[5].a 0
-assert e.out[6].a 0
+set e.out[6].a 0
-assert e.out[7].a 0
+set e.out[7].a 0
-
+cycle
 assert e.in.a 1
 assert e.in.v 1
 
@@ -197,15 +198,15 @@ assert e.out[6].r 0
 assert e.out[7].r 0
 assert e.in.a 0
 assert e.in.v 0
-assert e.out[0].a 0
+set e.out[0].a 0
-assert e.out[1].a 0
+set e.out[1].a 0
-assert e.out[2].a 0
+set e.out[2].a 0
-assert e.out[3].a 0
+set e.out[3].a 0
-assert e.out[4].a 0
+set e.out[4].a 0
-assert e.out[5].a 0
+set e.out[5].a 0
-assert e.out[6].a 0
+set e.out[6].a 0
-assert e.out[7].a 0
+set e.out[7].a 0
-
+cycle
 
 
 
@@ -241,15 +242,15 @@ assert e.out[6].r 0
 assert e.out[7].r 0
 assert e.in.a 0
 assert e.in.v 0
-assert e.out[0].a 0
+set e.out[0].a 0
-assert e.out[1].a 0
+set e.out[1].a 0
-assert e.out[2].a 0
+set e.out[2].a 0
-assert e.out[3].a 0
+set e.out[3].a 0
-assert e.out[4].a 0
+set e.out[4].a 0
-assert e.out[5].a 0
+set e.out[5].a 0
-assert e.out[6].a 0
+set e.out[6].a 0
-assert e.out[7].a 0
+set e.out[7].a 0
-
+cycle
 
 
 system "echo '[] Sending in a 1 packet'"
@@ -279,15 +280,15 @@ assert e.out[5].r 0
 assert e.out[6].r 0
 assert e.out[7].r 0
 
-assert e.out[0].a 0
+set e.out[0].a 0
-assert e.out[1].a 0
+set e.out[1].a 0
-assert e.out[2].a 0
+set e.out[2].a 0
-assert e.out[3].a 0
+set e.out[3].a 0
-assert e.out[4].a 0
+set e.out[4].a 0
-assert e.out[5].a 0
+set e.out[5].a 0
-assert e.out[6].a 0
+set e.out[6].a 0
-assert e.out[7].a 0
+set e.out[7].a 0
-
+cycle
 assert e.in.a 1
 assert e.in.v 1