texel 30 unit tests working

test/unit_tests/texel_in30/test.prsim

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+watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+set-bd-channel-neutral "c.in" 30
+set c.out.a 0
+set c.loopback_en 1
+set Reset 1
+
+cycle
+
+mode run
+status X
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+# Reading address 0
+set-bd-data-valid "c.in" 30 536870912
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
+
+# Should first get loopback
+assert-bd-channel-valid "c.out" 30 536870912
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 30
+set c.out.a 0
+cycle
+
+# Expect register read packet to arrive
+# Receiving output 4194303 from register 0
+assert-bd-channel-valid "c.out" 30 268435392
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 30
+set c.out.a 0
+cycle
+
+# Disable loopback cus it's annoying
+set c.loopback_en 0
+cycle
+
+# Writing 1 to address 0 (enables hs, disables synapse delays)
+set-bd-data-valid "c.in" 30 805306432
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
+
+# Sending spike to synapse [2,3]
+set-bd-data-valid "c.in" 30 8
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+# Receiving output spike [2,3]
+assert-bd-channel-valid "c.out" 30 8
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 30
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+# # Writing 68 to address 1
+# set c.in.d[0] 1
+# set c.in.d[1] 0
+# set c.in.d[2] 0
+# set c.in.d[3] 0
+# set c.in.d[4] 0
+# set c.in.d[5] 0
+# set c.in.d[6] 1
+# set c.in.d[7] 0
+# set c.in.d[8] 0
+# set c.in.d[9] 0
+# set c.in.d[10] 1
+# set c.in.d[11] 0
+# set c.in.d[12] 1
+# set c.in.d[13] 1
+# cycle
+# set c.in.r 1
+# cycle
+# assert c.in.a 1
+
+# # Remove input
+# set-bd-channel-neutral "c.in" 14
+# cycle
+# assert c.in.a 0
+
+
+# # Reading address 1
+# set c.in.d[0] 1
+# set c.in.d[1] 0
+# set c.in.d[2] 0
+# set c.in.d[3] 0
+# set c.in.d[4] 0
+# set c.in.d[5] 0
+# set c.in.d[6] 0
+# set c.in.d[7] 0
+# set c.in.d[8] 0
+# set c.in.d[9] 0
+# set c.in.d[10] 0
+# set c.in.d[11] 0
+# set c.in.d[12] 0
+# set c.in.d[13] 1
+# cycle
+# set c.in.r 1
+# cycle
+# assert c.in.a 1
+
+#  # Remove input
+# set-bd-channel-neutral "c.in" 14
+# cycle
+# assert c.in.a 0
+
+
+# # Receiving output 68 from register 1
+# assert-bd-channel-valid "c.out" 14 1089
+# set c.out.a 1
+# cycle
+# assert-bd-channel-neutral "c.out" 14
+# set c.out.a 0
+# cycle
+
+# # Sending spike to synapse [0,1]
+# set c.in.d[0] 0
+# set c.in.d[1] 1
+# set c.in.d[2] 0
+# set c.in.d[3] 0
+# set c.in.d[4] 0
+# set c.in.d[5] 0
+# set c.in.d[6] 0
+# set c.in.d[7] 0
+# set c.in.d[8] 0
+# set c.in.d[9] 0
+# set c.in.d[10] 0
+# set c.in.d[11] 0
+# set c.in.d[12] 0
+# set c.in.d[13] 0
+# cycle
+# set c.in.r 1
+# cycle
+# assert c.in.a 1