bics/actlib_dataflow_neuro
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fixing tests, started cleaning

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This commit is contained in:
M. Mastella
2023-11-17 11:13:19 +01:00
parent ff077c5169
commit 25e0b4b1a2
156 changed files with 55 additions and 8287468 deletions
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6
test/unit_tests/bd-fifo-register-fifo-bd/test.act
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@@ -36,7 +36,7 @@ open std::data;
open tmpl::dataflow_neuro;
defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]){
defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]; bool? dly_cfg2[2]){
bool _reset_B;
prs {
Reset => _reset_B-
@@ -45,13 +45,13 @@ defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? d
supply.vdd = Vdd;
supply.vss = GND;
bd2qdi<9,4> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
bd2qdi<9,4,2> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .dly_cfg2 = dly_cfg2, .reset_B = _reset_B, .supply = supply);
fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
register_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
.reset_B = _reset_B, .supply = supply);
fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);