fifo_test_adv works
This commit is contained in:
Michele
58
test/unit_tests/arbiter_handshake_simple/run/prsim.out
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58
test/unit_tests/arbiter_handshake_simple/run/prsim.out
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@ -0,0 +1,58 @@
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t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.a.arbiter._y2 t.out.a t.in1.a t.a._y1_arb t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell1._y t.a.ack_cell2._y
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[0] code starts
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0 t.in1.r : 0
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0 t.out.a : 0
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0 t.in2.r : 0
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1 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
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7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
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7094 t.a._y2_arb : 0 [by t.a.arbiter._y2:=1]
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10468 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
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10582 t.a.or_cell._y : 1 [by t.a._y1_arb:=0]
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11605 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
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11847 t.a.ack_cell2._y : 1 [by t.a._y2_arb:=0]
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11886 t.in2.a : 0 [by t.a.ack_cell2._y:=1]
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13331 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
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75948 t.out.r : 0 [by t.a.or_cell._y:=1]
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[1] reset done
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----------------------------------------------------------------------------------------------------
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75948 t.in1.r : 1
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75963 t.a.arbiter._y1 : 0 [by t.in1.r:=1]
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76454 t.a._y1_arb : 1 [by t.a.arbiter._y1:=0]
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76467 t.a.or_cell._y : 0 [by t.a._y1_arb:=1]
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76507 t.out.r : 1 [by t.a.or_cell._y:=0]
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76507 t.out.a : 1
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76922 t.a.ack_cell1._y : 0 [by t.out.a:=1]
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76942 t.in1.a : 1 [by t.a.ack_cell1._y:=0]
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[2] test in1 done
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----------------------------------------------------------------------------------------------------
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76942 t.in1.r : 0
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83003 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
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83050 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
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83066 t.a.or_cell._y : 1 [by t.a._y1_arb:=0]
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127164 t.out.r : 0 [by t.a.or_cell._y:=1]
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127164 t.out.a : 0
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140888 t.a.ack_cell1._y : 1 [by t.out.a:=0]
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140892 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
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[3] reset done
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----------------------------------------------------------------------------------------------------
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140892 t.in2.r : 1
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150021 t.a.arbiter._y2 : 0 [by t.in2.r:=1]
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150036 t.a._y2_arb : 1 [by t.a.arbiter._y2:=0]
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193284 t.a.or_cell._y : 0 [by t.a._y2_arb:=1]
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230215 t.out.r : 1 [by t.a.or_cell._y:=0]
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230215 t.out.a : 1
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230270 t.a.ack_cell2._y : 0 [by t.out.a:=1]
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281923 t.in2.a : 1 [by t.a.ack_cell2._y:=0]
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[4] test in2 done
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----------------------------------------------------------------------------------------------------
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281923 t.in2.r : 0
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311703 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
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325552 t.a._y2_arb : 0 [by t.a.arbiter._y2:=1]
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350364 t.a.or_cell._y : 1 [by t.a._y2_arb:=0]
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364707 t.out.r : 0 [by t.a.or_cell._y:=1]
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364707 t.out.a : 0
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365129 t.a.ack_cell2._y : 1 [by t.out.a:=0]
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413843 t.in2.a : 0 [by t.a.ack_cell2._y:=1]
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[5] reset done
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----------------------------------------------------------------------------------------------------
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70
test/unit_tests/arbiter_handshake_simple/run/test.prs
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70
test/unit_tests/arbiter_handshake_simple/run/test.prs
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@ -0,0 +1,70 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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= "t.a.in1.d.d[0]" "t.a.in1.r"
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= "t.a.in1.a" "t.a.arbiter.d"
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= "t.a.in1.a" "t.a.ack_cell1.y"
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= "t.a.in1.d.d[0]" "t.a.arbiter.a"
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= "t.a.in1.d.d[0]" "t.a.in1.r"
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~"t.a.ack_cell1.c1"&~"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"+
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"t.a.ack_cell1.c1"&"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"-
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"t.a.ack_cell1._y"->"t.a.ack_cell1.y"-
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~("t.a.ack_cell1._y")->"t.a.ack_cell1.y"+
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= "t.a.in2.d.d[0]" "t.a.in2.r"
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= "t.a.in2.a" "t.a.arbiter.c"
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= "t.a.in2.a" "t.a.ack_cell2.y"
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= "t.a.in2.d.d[0]" "t.a.arbiter.b"
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= "t.a.in2.d.d[0]" "t.a.in2.r"
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= "t.a.supply.vdd" "t.a.arbiter.vdd"
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= "t.a.supply.vdd" "t.a.or_cell.vdd"
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= "t.a.supply.vdd" "t.a.ack_cell2.vdd"
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= "t.a.supply.vdd" "t.a.ack_cell1.vdd"
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= "t.a.supply.vss" "t.a.arbiter.vss"
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= "t.a.supply.vss" "t.a.or_cell.vss"
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= "t.a.supply.vss" "t.a.ack_cell2.vss"
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= "t.a.supply.vss" "t.a.ack_cell1.vss"
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"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"-
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~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+
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"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"-
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~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+
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"t.a.arbiter._y1"|"t.a.arbiter.c"->"t.a.arbiter.y1"-
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~("t.a.arbiter._y1"|"t.a.arbiter.c")->"t.a.arbiter.y1"+
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"t.a.arbiter._y2"|"t.a.arbiter.d"->"t.a.arbiter.y2"-
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~("t.a.arbiter._y2"|"t.a.arbiter.d")->"t.a.arbiter.y2"+
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mk_excllo("t.a.arbiter._y1","t.a.arbiter._y2")
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= "t.a._y1_arb" "t.a.arbiter.y1"
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= "t.a._y1_arb" "t.a.or_cell.a"
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= "t.a._y1_arb" "t.a.ack_cell1.c2"
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~"t.a.ack_cell2.c1"&~"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"+
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"t.a.ack_cell2.c1"&"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"-
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"t.a.ack_cell2._y"->"t.a.ack_cell2.y"-
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~("t.a.ack_cell2._y")->"t.a.ack_cell2.y"+
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"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"-
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~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+
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"t.a.or_cell._y"->"t.a.or_cell.y"-
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~("t.a.or_cell._y")->"t.a.or_cell.y"+
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= "t.a.out.d.d[0]" "t.a.out.r"
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= "t.a.out.a" "t.a.ack_cell2.c1"
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= "t.a.out.a" "t.a.ack_cell1.c1"
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= "t.a.out.d.d[0]" "t.a.or_cell.y"
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= "t.a.out.d.d[0]" "t.a.out.r"
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= "t.a._y2_arb" "t.a.arbiter.y2"
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= "t.a._y2_arb" "t.a.or_cell.b"
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= "t.a._y2_arb" "t.a.ack_cell2.c2"
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= "Vdd" "t.a.supply.vdd"
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= "GND" "t.a.supply.vss"
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= "t.in1.d.d[0]" "t.in1.r"
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= "t.in1.r" "t.a.in1.r"
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= "t.in1.a" "t.a.in1.a"
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= "t.in1.d.d[0]" "t.a.in1.d.d[0]"
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= "t.in1.d.d[0]" "t.in1.r"
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= "t.out.d.d[0]" "t.out.r"
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= "t.out.r" "t.a.out.r"
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= "t.out.a" "t.a.out.a"
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= "t.out.d.d[0]" "t.a.out.d.d[0]"
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= "t.out.d.d[0]" "t.out.r"
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= "t.in2.d.d[0]" "t.in2.r"
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= "t.in2.r" "t.a.in2.r"
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= "t.in2.a" "t.a.in2.a"
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= "t.in2.d.d[0]" "t.a.in2.d.d[0]"
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= "t.in2.d.d[0]" "t.in2.r"
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41
test/unit_tests/arbiter_handshake_simple/test.act
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41
test/unit_tests/arbiter_handshake_simple/test.act
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
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{
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arbiter_handshake a(.in1 = in1, .in2 = in2, .out = out);
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a.supply.vdd = Vdd;
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a.supply.vss = GND;
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}
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arbiter_test t;
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42
test/unit_tests/arbiter_handshake_simple/test.prsim
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42
test/unit_tests/arbiter_handshake_simple/test.prsim
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@ -0,0 +1,42 @@
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watchall
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system "echo '[0] code starts'"
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set t.in1.r 0
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set t.in2.r 0
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set t.out.a 0
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cycle
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status X
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mode run
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system "echo '[1] reset done'"
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system "echo '----------------------------------------------------------------------------------------------------'"
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set t.in1.r 1
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cycle
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assert t.out.r 1
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set t.out.a 1
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cycle
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assert t.in1.a 1
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system "echo '[2] test in1 done'"
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system "echo '----------------------------------------------------------------------------------------------------'"
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set t.in1.r 0
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cycle
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assert t.out.r 0
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set t.out.a 0
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cycle
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assert t.in1.a 0
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system "echo '[3] reset done'"
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system "echo '----------------------------------------------------------------------------------------------------'"
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set t.in2.r 1
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cycle
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assert t.out.r 1
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set t.out.a 1
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cycle
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assert t.in2.a 1
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system "echo '[4] test in2 done'"
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system "echo '----------------------------------------------------------------------------------------------------'"
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set t.in2.r 0
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cycle
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assert t.out.r 0
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set t.out.a 0
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cycle
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assert t.in2.a 0
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system "echo '[5] reset done'"
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system "echo '----------------------------------------------------------------------------------------------------'"
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