Merge branch 'innovus_ready' into dev

dataflow_neuro/chips.act

@@ -56,19 +56,31 @@ REG_NCA, REG_NCW, REG_M>
 
 defproc texel_core (avMx1of2<N_IN> in, out;
     Mx1of2<REG_NCW> reg_data[REG_M];
-    a1of1 synapses[N_SYN_X * N_SYN_Y];
+
-    a1of1 neurons[N_NRN_X * N_NRN_Y];
+    // Dummy synapses and neurons in the handshake blocks
-    
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
     bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
     bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
     bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
     bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
 
-    // bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
-    // bool? loopback_en;
     power supply;
-    bool? reset_B){
+    bool? reset_B, reset_reg_B){
 
     bool _reset_BX;
     BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
@@ -82,7 +94,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     // Register
     fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
     register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
-        .supply = supply, .reset_B = _reset_BX);
+        .supply = supply, .reset_B = reset_reg_B);
     fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
 
 
@@ -94,6 +106,9 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
         .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
         .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
         .supply = supply, .reset_B = _reset_BX);
     INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
     (i:N_SYN_DLY_CFG:
@@ -104,28 +119,28 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     )
 
     // Synapse handshake circuits, to be removed for innovus
-    decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
-        .synapses = synapses,
+    //     .synapses = synapses,
-        .in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
-        .to_pu = decoder.to_pu,
+    //     .to_pu = syn_pu,
-        // .in_ackB_pullups = decoder.out_ackB_pullups,
+    //     .out_ackB_decoder = dec_ackB,
-        // .out_req_x_pullups = decoder.in_req_x_pullups,
+    //     .supply = supply);
-        .out_ackB_decoder = decoder.in_ackB_decoder,
-        .supply = supply);
 
     // Neurons + encoder
     pint NC_NRN;
     NC_NRN = NC_NRN_X + NC_NRN_Y;
     encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
-        .reset_B = _reset_BX, .supply = supply);
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
     fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
         .reset_B = _reset_BX, .supply = supply);
 
     // Neuron handshake circuits, to be removed for innovus
-    nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
-        .outx = encoder.inx, .outy = encoder.iny,
+    //     .outx = enc_inx, .outy = enc_iny,
-        .to_pd_x = encoder.to_pd_x, .to_pd_y = encoder.to_pd_y,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
-        .supply = supply, .reset_B = _reset_BX);
+    //     .supply = supply, .reset_B = _reset_BX);
 
 
 
@@ -271,8 +286,8 @@ REG_NCA, REG_NCW, REG_M>
 
 defproc texel_singlecore (bd<N_IN> in, out;
 	Mx1of2<REG_NCW> reg_data[REG_M];
-	a1of1 synapses[N_SYN_X * N_SYN_Y];
+	// a1of1 synapses[N_SYN_X * N_SYN_Y];
-	a1of1 neurons[N_NRN_X * N_NRN_Y];
+	// a1of1 neurons[N_NRN_X * N_NRN_Y];
     
     bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
     bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
@@ -309,8 +324,8 @@ defproc texel_singlecore (bd<N_IN> in, out;
     texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
         core(.in = fifo_fork2core.out,
             .reg_data = reg_data,
-            .synapses = synapses,
+            // .synapses = synapses,
-            .neurons = neurons,
+            // .neurons = neurons,
             .nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
             .syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
             .syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
@@ -355,9 +370,17 @@ REG_NCA, REG_NCW, REG_M>
 defproc texel_dualcore (bd<N_IN> in, out;
 
     Mx1of2<REG_NCW> c1_reg_data[REG_M];
-    a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+
-    a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
+    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
     
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
     bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
     bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
     bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
@@ -365,9 +388,17 @@ defproc texel_dualcore (bd<N_IN> in, out;
     bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
     Mx1of2<REG_NCW> c2_reg_data[REG_M];
-    a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+
-    a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
     
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
     bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
     bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
     bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
@@ -377,7 +408,7 @@ defproc texel_dualcore (bd<N_IN> in, out;
     bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
     bool? loopback_en;
     power supply;
-    bool? reset_B){
+    bool? reset_B, reset_reg_B){
 
     // Reset buffers
     bool _reset_BX;
@@ -407,15 +438,23 @@ defproc texel_dualcore (bd<N_IN> in, out;
         core1(.in = fifo_dmx2core1.out,
 
             .reg_data = c1_reg_data,
-            .synapses = c1_synapses,
+            // .synapses = c1_synapses,
-            .neurons = c1_neurons,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
             .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
             .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
             .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
             .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
             .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
 
-            .reset_B = _reset_BX,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
             .supply = supply
             );
 
@@ -424,15 +463,23 @@ defproc texel_dualcore (bd<N_IN> in, out;
         core2(.in = fifo_dmx2core2.out,
 
             .reg_data = c2_reg_data,
-            .synapses = c2_synapses,
+            // .synapses = c2_synapses,
-            .neurons = c2_neurons,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
             .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
             .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
             .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
             .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
             .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
 
-            .reset_B = _reset_BX,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
             .supply = supply
             );
 

test/unit_tests/texel_dualcore/test.act

@@ -80,12 +80,16 @@ pint REG_NCW = 23;
 defproc chip_texel_dualcore (bd<N_IN> in, out;
 
     Mx1of2<REG_NCW> c1_reg_data[REG_M];
+
     a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
     a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-    // bool c1_syn_r[N_SYN_X * N_SYN_Y];
+
-    // bool c1_syn_a[N_SYN_X * N_SYN_Y];
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
-    // bool c1_nrn_r[N_NRN_X * N_NRN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
-    // bool c1_nrn_a[N_NRN_X * N_NRN_Y];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
     
     bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
     bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
@@ -94,12 +98,16 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
     bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
     Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
     a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
     a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-    // bool c2_syn_r[N_SYN_X * N_SYN_Y];
+
-    // bool c2_syn_a[N_SYN_X * N_SYN_Y];
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
-    // bool c2_nrn_r[N_NRN_X * N_NRN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
-    // bool c2_nrn_a[N_NRN_X * N_NRN_Y];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
     
     bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
     bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
@@ -118,25 +126,6 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
     supply.vdd = Vdd;
     supply.vss = GND;
 
-
-    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-    // (i:N_SYN_X * N_SYN_Y:
-    //     c1_synapses[i].r = c1_syn_r[i];
-    //     c2_synapses[i].r = c2_syn_r[i];
-    //     c1_synapses[i].a = c1_syn_a[i];
-    //     c2_synapses[i].a = c2_syn_a[i];
-    // )
-    // (i:N_NRN_X * N_NRN_Y:
-    //     c1_neurons[i].r = c1_nrn_r[i];
-    //     c2_neurons[i].r = c2_nrn_r[i];
-    //     c1_neurons[i].a = c1_nrn_a[i];
-    //     c2_neurons[i].a = c2_nrn_a[i];
-    // )
-
-
     texel_dualcore<N_IN,
     N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
     NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
@@ -148,10 +137,35 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
     N_LINE_PD_DLY,
     N_BD_DLY_CFG, N_BD_DLY_CFG2,
     REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
-        .c1_reg_data = c1_reg_data, .c1_synapses = c1_synapses, .c1_neurons = c1_neurons, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_synapses = c2_synapses, .c2_neurons = c2_neurons, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
+        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
-        .loopback_en = loopback_en, .supply = supply, .reset_B = _reset_B);
+        .loopback_en = loopback_en,
+        .reset_B = _reset_B, .reset_reg_B = _reset_B,
+        .supply = supply);
 
 
+    decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c1_syn_grid(
+        .synapses = c1_synapses,
+        .in_req_x = c1_dec_req_x, .in_req_y = c1_dec_req_y,
+        .to_pu = c1_syn_pu,
+        .out_ackB_decoder = c1_dec_ackB,
+        .supply = supply);
+
+    nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c1_nrn_grid(.in = c1_neurons,
+        .outx = c1_enc_inx, .outy = c1_enc_iny,
+        .to_pd_x = c1_nrn_pd_x, .to_pd_y = c1_nrn_pd_y,
+        .supply = supply, .reset_B = _reset_B);
+
+    decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c2_syn_grid(
+        .synapses = c2_synapses,
+        .in_req_x = c2_dec_req_x, .in_req_y = c2_dec_req_y,
+        .to_pu = c2_syn_pu,
+        .out_ackB_decoder = c2_dec_ackB,
+        .supply = supply);
+
+    nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c2_nrn_grid(.in = c2_neurons,
+        .outx = c2_enc_inx, .outy = c2_enc_iny,
+        .to_pd_x = c2_nrn_pd_x, .to_pd_y = c2_nrn_pd_y,
+        .supply = supply, .reset_B = _reset_B);
 }
 
 

test/unit_tests/texel_dualcore/test.prsim

@@ -10644,9 +10644,10 @@ cycle
 mode run
 status X
 system "echo '[] Set reset 0'"
-status X
+# status X
 set Reset 0
 cycle
+status X
 
 assert-bd-channel-neutral "c.out" 32
 

test/unit_tests/texel_dualcore_innovus/run/prsim.in

@@ -0,0 +1,29 @@
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+# watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+
+set-bd-channel-neutral "c.in" 32
+set c.out.a 0
+set c.loopback_en 1
+# set c.loopback_en 0
+# set R
+
+cycle

test/unit_tests/texel_dualcore_innovus/run/prsim.out

@@ -0,0 +1 @@
+c.c.core2.encoder.dly_x[13].dly[0].bufchain[8].y c.c.core2.syn_x_AMZI_tbuf[4].y c.c.core1.encoder.dly_x[3].dly[0].bufchain[3].y c.c.core2.encoder.dly_y[1].dly[0].bufchain[7]._y c.c.core1.encoder.Xenc._inX[11] c.c._qdi2bd.dly.dly[4].y c.c.core1.encoder.Xarb.arbs[13]._y1_arb c.c.core1.encoder.Xenc._inX[6] c.c1_enc_inx[13].a c.c.core1.encoder.dly_x[5].dly[0].bufchain[8].y c.c._bd2qdi.dly.dly[6].bufchain[12].y c.c.core2.encoder.dly_x[10].dly[0].y c.c.core1.encoder.dly_y[0].dly[0].bufchain[3].y c.c.core1.encoder.dly_x[7].dly[1].bufchain[1]._y c.c2_syn_mon_AMZI[29] c.c.core2.encoder.dly_x[12].dly[1].bufchain[2].y c.c.core1.encoder.Xenc._inX[5] c.c.core2.encoder.dly_y[3].dly[1].bufchain[0].y c.c.core2.encoder.Xenc._inX[10] c.c.core1.encoder.dly_x[7].dly[0].bufchain[7].y c.c.core1.encoder.dly_x[0].dly[0].bufchain[5].y c.c.core2.encoder.dly_x[8].dly[0].bufchain[8]._y c.c.core2.encoder.dly_x[10].dly[0].bufchain[9].y c.c.core1.encoder.dly_y[5].dly[2].bufchain[15]._y c.c._bd2qdi._reqXX[0] c.c1_syn_mon_AMZI[27] c.c.core2.encoder.Xenc.ors_t[0].out c.c._bd2qdi.dly.dly[11].bufchain[13]._y c.c.core2.encoder.dly_y[2].dly[2].bufchain[12].y c.c.core1.encoder.Xarb.tmp[25].r c.c.core2.encoder.dly_x[7].dly[2].bufchain[0]._y c.c.core1.encoder.Xenc.ors_t[3].tmp[8] c.c2_nrn_mon_AMZI[30] c.c._bd2qdi.dly.dly[1].bufchain[1].y c.c.core1.encoder.dly_y[3].dly[1].bufchain[12].y c.c.core1.encoder.dly_x[0].dly[1].bufchain[12].y c.c.core1.encoder.dly_x[8].dly[2].bufchain[1]._y c.c2_nrn_pd_x[8].a c.c.core2.encoder.Xenc._inX[5] c.c2_nrn_pd_y[0].a c.c1_nrn_mon_AMZO[3] c.c._bd2qdi.dly.dly[0].bufchain[7]._y c.c2_nrn_mon_AMZO[4] c.c2_enc_inx[9].r c.c1_syn_mon_AMZI[10] c.c.core1.encoder.Yenc.ors_f[2].out c.c._bd2qdi.dly.dly[7].bufchain[0]._y c.c2_enc_inx[12].r c.c.core1.encoder.dly_x[14].dly[2].bufchain[11]._y c.c.core2.encoder.Yarb.tmp[7].r c.c.core2.encoder.dly_x[7].dly[2].bufchain[3]._y c.c._bd2qdi.dly.dly[11].bufchain[4]._y c.c._bd2qdi.dly.mu2[3]._s c.c2_dec_ackB[5] c.c.core2.encoder.Xarb.arbs[12].arbiter._y1 c.c.core2.encoder.dly_x[11].dly[2].bufchain[13].y c.in.d[27] c.c._bd2qdi.dly.dly[13].bufchain[1].y c.c.core1.encoder.dly_x[14].dly[0].bufchain[2].y c.c2_nrn_mon_AMZO[3] c.c1_enc_inx[3].a c.c.core2.decoder._ortree.tmp[15] c.c.core1.encoder.dly_x[7].dly[2].bufchain[13].y c.c.core1.encoder.Xenc._inX[9] c.c.core2.encoder.Xarb.tmp[20].r c.c2_syn_mon_AMZO[2] c.c.core1.nrn_x_AMZI_tbuf[0].y c.c1_nrn_mon_AMZO[6] c.c1_syn_pu[1].r c.c.core2.encoder.dly_y[3].dly[2].bufchain[7]._y c.c1_syn_mon_AMZO[1] c.c.core2.encoder.Yenc.ors_t[0].or2s[0]._y c.c.core1.encoder.dly_x[0].dly[2].bufchain[13].y c.c2_syn_mon_AMZO[4] c.c.core2.encoder.Xenc.ors_t[0].tmp[11] c.c.core2.encoder.dly_x[0].dly[2].bufchain[10].y c.c1_syn_mon_AMZI[68] c.c.core1.encoder.dly_x[4].dly[0].bufchain[12]._y c.c._qdi2bd.dly.dly[7].a c.c.core2.encoder.dly_y[3].dly[1].bufchain[14].y c.c2_enc_inx[9].a c.c1_syn_pu[0].r c.c.core2.encoder.dly_y[0].dly[1].y c.c2_nrn_pd_x[11].a c.c1_nrn_pd_y[2].a c.c1_syn_pu[8].r c.c.core2.encoder.dly_x[1].dly[1].bufchain[9].y c.c._bd2qdi.dly2.out c.c.core2.encoder.dly_x[8].dly[0].bufchain[7].y c.c._qdi2bd.dly.dly[2].bufchain[10]._y c.c2_syn_pu[14].r c.c.core1.encoder.dly_x[1].dly[1].bufchain[7]._y c.c.core2.encoder.dly_x[12].dly[0].bufchain[3].y c.bd_dly_cfg[2] c.c._bd2qdi.dly.dly[10].bufchain[5].y c.c1_nrn_mon_AMZI[3] c.c2_syn_mon_AMZO[3] c.c.core1.encoder.Xarb.tmp[24].r c.c2_syn_mon_AMZI[56] c.c._bd2qdi.dly2.dly[0].bufchain[10].y c.c.core2.encoder.Xarb.tmp[23].r c.c1_nrn_mon_AMZI[22] c.c.core1.encoder.dly_x[2].dly[2].bufchain[5]._y c.c._bd2qdi.dly.dly[11].bufchain[8].y c.c.core1.decoder._ortree.in[3] c.c.core1.encoder.buf.vc.ct.in[1] c.c.core2.encoder.dly_y[0].dly[1].bufchain[12].y c.c.core1.decoder._ortree.in[8] c.c._bd2qdi.dly.dly[14].bufchain[5].y c.c.core2.encoder.dly_x[3].dly[1].bufchain[11].y c.c.core2.encoder.Xenc._inX[6] c.c._qdi2bd.dly.dly[7].bufchain[4].y c.c.core2.encoder.dly_y[0].dly[2].bufchain[12].y c.c.core1.encoder._r_x c.c.core1.encoder.pd_y[2].in c.c._loopback_dropper.and_f[0].b c.c.core2.encoder.Yarb.tmp[9].r c.c1_nrn_pd_x[5].a c.c._qdi2bd.dly.dly[4].bufchain[7]._y c.c.core1.encoder.dly_y[4].dly[2].bufchain[0].y c.c.core2.encoder.dly_x[5].dly[2].bufchain[8]._y c.c1_nrn_mon_AMZO[5] c.c2_syn_mon_AMZI[7] c.c.core1.encoder.dly_x[3].dly[0].bufchain[2].y c.c._qdi2bd.dly.dly[14].bufchain[11]._y c.c1_nrn_mon_AMZI[99] c.c.core1.encoder.dly_y[5].dly[0].bufchain[1]._y c.c._qdi2bd.dly.dly[5].bufchain[13]._y c.c.core1.nrn_x_AMZI_tbuf[2].y c.c.core1.encoder.dly_x[6].dly[2].bufchain[4].y c.c.core1.encoder.dly_x[11].dly[2].bufchain[3].y c.c.core2.encoder.dly_x[0].dly[1].bufchain[2].y c.c.core1.encoder.dly_x[6].dly[1].bufchain[0].y c.c.core1.encoder.dly_y[0].dly[0].bufchain[2].y c.c.core1.decoder._ortree.in[0] c.c2_nrn_mon_AMZI[64] c.c._qdi2bd.dly.dly[4].bufchain[14].y c.c.core2.encoder.dly_x[8].dly[0].bufchain[10].y c.c.core1.encoder.dly_x[2].dly[1].y c.c.core2.encoder.dly_x[13].dly[0].bufchain[15]._y c.c._qdi2bd.buf._out_a_BX[0] c.c2_nrn_mon_AMZO[1] c.c.coreLine truncated

test/unit_tests/texel_dualcore_innovus/test.act

@@ -0,0 +1,149 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/chips.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+
+
+pint N_IN = 32;
+
+pint N_NRN_X = 15;
+pint N_NRN_Y = 6;
+pint NC_NRN_X = 4;
+pint NC_NRN_Y = 3;
+
+pint N_SYN_X = 15;
+pint N_SYN_Y = 348;
+pint NC_SYN_X = 6;
+pint NC_SYN_Y = 9;
+
+pint N_SYN_DLY_CFG = 4;
+pint N_BD_DLY_CFG = 4;
+pint N_BD_DLY_CFG2 = 2;
+
+pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
+pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
+
+pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
+pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N
+
+pint N_MON_AMZO_PER_SYN = 5;
+pint N_MON_AMZO_PER_NRN = 7;
+
+pint N_FLAGS_PER_SYN = 4; // Syn: Must be at least 3 (since those ones have special safety)
+pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
+
+pint N_BUFFERS = 3;
+
+pint N_LINE_PD_DLY = 3;
+
+pint REG_NCA = 6;
+pint REG_M = 1<<REG_NCA;
+pint REG_NCW = 23;
+
+
+defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+
+    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
+
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+    
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+    
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    bool? reset_B, reset_reg_B
+    ){
+
+    // bool _reset_B; 
+    // prs {
+    //     Reset => _reset_B-
+    // }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    texel_dualcore<N_IN,
+    N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
+    NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+    N_SYN_DLY_CFG,
+    N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+    N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
+    N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
+    N_BUFFERS,
+    N_LINE_PD_DLY,
+    N_BD_DLY_CFG, N_BD_DLY_CFG2,
+    REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
+        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
+        .loopback_en = loopback_en, .supply = supply, .reset_B = reset_B, .reset_reg_B = reset_reg_B);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+chip_texel_dualcore_innovus c; 

test/unit_tests/texel_dualcore_innovus/test.prsim

@@ -0,0 +1,19 @@
+# watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+
+set-bd-channel-neutral "c.in" 32
+set c.out.a 0
+set c.loopback_en 1
+# set c.loopback_en 0
+# set R
+
+cycle