bics
/
actlib_dataflow_neuro
18
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

chip unit tests passing baybeeeeee

This commit is contained in:
alexmadison 2022-04-05 18:21:36 +02:00
parent 3697d21698
commit 41d76de718
4 changed files with 23972 additions and 10964 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29590
test/unit_tests/chip_nomap/run/prsim.out
View File

File diff suppressed because one or more lines are too long

5228
test/unit_tests/chip_nomap/run/test.prs
View File

File diff suppressed because it is too large Load Diff

20
test/unit_tests/chip_nomap/test.act
View File

@ -39,7 +39,7 @@ open std::data;
open tmpl::dataflow_neuro;
defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
bool? bd_dly_cfg[4], loopback_en){
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
bool _reset_B;
prs {
@ -67,6 +67,7 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
pint N_SYN_DLY_CFG = 4;
pint N_BD_DLY_CFG = 4;
pint N_BD_DLY_CFG2 = 2;
pint N_NRN_MON_X = 2;
pint N_NRN_MON_Y = 4;
@ -88,12 +89,23 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_BUFFERS,
N_LINE_PD_DLY,
N_BD_DLY_CFG,
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
.bd_dly_cfg = bd_dly_cfg, .loopback_en = loopback_en,
.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
.reset_B = _reset_B, .supply = supply);
c.synapses = c.neurons; // Connect each synapse hs to a neuron hs
// Spawn in some buffers as a conduit between neurons and synapses.
pint N_SYNS = N_SYN_X * N_SYN_Y;
BUF_X4 syn2nrns_r[N_SYNS];
BUF_X4 syn2nrns_a[N_SYNS];
(i:N_SYNS:
syn2nrns_r[i].a = c.synapses[i].r;
syn2nrns_r[i].y = c.neurons[i].r;
syn2nrns_a[i].a = c.neurons[i].a;
syn2nrns_a[i].y = c.synapses[i].a;
)
// c.synapses = c.neurons; // Connect each synapse hs to a neuron hs
}

98
test/unit_tests/chip_nomap/test.prsim
View File

@ -6,8 +6,10 @@ set c.bd_dly_cfg[1] 1
set c.bd_dly_cfg[2] 1
set c.bd_dly_cfg[3] 1
set c.bd_dly_cfg2[0] 1
set c.bd_dly_cfg2[1] 1
set-bd-channel-neutral "c.in" 14
# set-bd-channel-neutral "c.out" 14
set c.out.a 0
set c.loopback_en 1
set Reset 1
@ -21,6 +23,96 @@ status X
set Reset 0
cycle
set-bd-channel-valid "c.in" 14 16128
# Reading address 0
set c.in.d[0] 0
set c.in.d[1] 0
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 0
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 0
set c.in.d[11] 0
set c.in.d[12] 0
set c.in.d[13] 1
cycle
assert-bd-channel-valid "c.out" 14 16128
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Should first get loopback
assert-bd-channel-valid "c.out" 14 8192
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Expect register read packet to arrive
assert-bd-channel-valid "c.out" 14 4080
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Disable loopback cus it's annoying
set c.loopback_en 0
cycle
# Writing 68 to address 1
set c.in.d[0] 1
set c.in.d[1] 0
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 1
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 1
set c.in.d[11] 0
set c.in.d[12] 1
set c.in.d[13] 1
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Reading address 1
set c.in.d[0] 1
set c.in.d[1] 0
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 0
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 0
set c.in.d[11] 0
set c.in.d[12] 0
set c.in.d[13] 1
cycle
set c.in.r 1
cycle
assert c.in.a 1
assert-bd-channel-valid "c.out" 14 1089