added license, moved cell libs into repo
added buffer (not tested),
This commit is contained in:
29
dataflow_neuro/Makefile
Normal file
29
dataflow_neuro/Makefile
Normal file
@ -0,0 +1,29 @@
|
||||
# -----------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
#
|
||||
# This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
#
|
||||
# You may redistribute and modify this documentation and make products
|
||||
# using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
# This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
# WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
# AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
# for applicable conditions.
|
||||
#
|
||||
# Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
#
|
||||
# As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
# these sources, You must maintain the Source Location visible in its
|
||||
# documentation.
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
TARGETACT=__all__.act stdcells.act acells.act primitives.act
|
||||
SUBDIRS=
|
||||
# template because its a template based appoach no syntesis so it would be wrong in syn
|
||||
TARGETACTSUBDIR=template/dataflow_neuro
|
||||
|
||||
include $(ACT_HOME)/scripts/Makefile.std
|
||||
|
||||
-include Makefile.deps
|
||||
27
dataflow_neuro/__all__.act
Normal file
27
dataflow_neuro/__all__.act
Normal file
@ -0,0 +1,27 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
import template::dataflow_neuro::cell_lib_std;
|
||||
import template::dataflow_neuro::cell_lib_async;
|
||||
import template::dataflow_neuro::primitives;
|
||||
446
dataflow_neuro/cell_lib_async.act
Normal file
446
dataflow_neuro/cell_lib_async.act
Normal file
@ -0,0 +1,446 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
namespace template {
|
||||
namespace dataflow_neuro {
|
||||
|
||||
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) {
|
||||
bool _y;
|
||||
prs{
|
||||
(~p1 & ~c1)|~pr_B -> _y+
|
||||
c1 & n1 & n2 & sr_B -> _y-
|
||||
_y => y-
|
||||
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}
|
||||
}
|
||||
}
|
||||
|
||||
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) {
|
||||
prs{
|
||||
(~p1 & ~c1)|~pr_B -> y-
|
||||
c1 & n1 & n2 & sr_B -> y+
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1, vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~p1 & ~c1 -> y+
|
||||
c1 & n1 -> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_1C1P_B (bool! y; bool? c1, p1, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
~p1 & ~c1 -> _y-
|
||||
c1 -> _y+
|
||||
_y => y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1} }
|
||||
}
|
||||
|
||||
|
||||
export defcell A_1C1P (bool! y; bool? c1, p1, vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~p1 & ~c1 -> y+
|
||||
c1 -> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1, vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~p1 & ~p2 & ~c1 -> y+
|
||||
c1 & n1 -> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
~p1 & ~p2 & ~c1 -> _y-
|
||||
c1 -> _y+
|
||||
_y => y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1} }
|
||||
}
|
||||
}
|
||||
|
||||
export defcell A_1C2P (bool! y; bool? c1, p1, p2, vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~p1 & ~p2 & ~c1 -> y+
|
||||
c1 -> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5 n1, n2, pr_B, sr_B, vdd, vss)
|
||||
{
|
||||
prs{
|
||||
(~p1 & ~p2 & ~p3 & ~c1)|(~p4&~p5&~c1)|~pr_B -> y+
|
||||
c1 & n1 & n2 & sr_B -> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~pr_B -> _y+
|
||||
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~pr_B -> _y+
|
||||
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-2}; _y{-1}}
|
||||
}
|
||||
|
||||
|
||||
export defcell A_2C2N2N_RB_X4 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~pr_B -> _y+
|
||||
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-4}; _y{-1}}
|
||||
}
|
||||
|
||||
|
||||
export defcell A_2C2N2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
(~c1 & ~c2) | ~pr_B -> y+
|
||||
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C2N_R_B_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~rp_B -> _y+
|
||||
c1 & c2 & n1 & n2 & rs_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C2N_R_B_X2 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~rp_B -> _y+
|
||||
c1 & c2 & n1 & n2 & rs_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-2}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C2N_R_B_X4 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~rp_B -> _y+
|
||||
c1 & c2 & n1 & n2 & rs_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-4}; _y{-1}}
|
||||
}
|
||||
|
||||
|
||||
export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
(~c1 & ~c2) | ~rp_B -> y+
|
||||
c1 & c2 & n1 & n2 & rs_B -> y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C_B_X1 (bool ! y; bool? c1, c2; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
~c1 & ~c2 -> _y+
|
||||
c1 & c2 -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C_RB_X1 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2) | ~pr_B -> _y+
|
||||
c1 & c2 & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C_R_X1 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
(~c1 & ~c2) | ~pr_B -> y+
|
||||
c1 & c2 & sr_B -> y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_2C_X1 (bool ! y; bool? c1, c2; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~c1 & ~c2 -> y+
|
||||
c1 & c2 -> y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_3C_RB_X1 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3) | ~pr_B -> _y+
|
||||
c1 & c2 & c3 & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_3C_RB_X2 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3) | ~pr_B -> _y+
|
||||
c1 & c2 & c3 & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-2}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_3C_RB_X4 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3) | ~pr_B -> _y+
|
||||
c1 & c2 & c3 & sr_B -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-4}; _y{-1}}
|
||||
}
|
||||
|
||||
export defcell A_3C_R_X1 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3) | ~pr_B -> y+
|
||||
c1 & c2 & c3 & sr_B -> y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_3C_X1 (bool ! y; bool? c1, c2, c3; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~c1 & ~c2 & ~c3 -> y+
|
||||
c1 & c2 & c3 -> y-
|
||||
}
|
||||
sizing {
|
||||
leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export deffcell A_4C_RB_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3 & ~c4) | ~pr_B -> _y+
|
||||
c1 & c2 & c3 & c4 & sr_B-> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing { leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1}}
|
||||
}
|
||||
|
||||
export deffcell A_4C_RB_X2 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3 & ~c4) | ~pr_B -> _y+
|
||||
c1 & c2 & c3 & c4 & sr_B-> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-2}; _y{-1}}
|
||||
}
|
||||
|
||||
export deffcell A_4C_RB_X4 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3 & ~c4) | ~pr_B -> _y+
|
||||
c1 & c2 & c3 & c4 & sr_B-> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-4}; _y{-1}}
|
||||
}
|
||||
|
||||
export deffcell A_4C_R_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
(~c1 & ~c2 & ~c3 & ~c4) | ~pr_B -> y+
|
||||
c1 & c2 & c3 & c4 & sr_B-> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
|
||||
export defcell A_4P1N1N_B_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs{
|
||||
~p1 & ~p2 & ~p3 & ~p4 -> _y+
|
||||
n1 | n2 -> _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}; _y{-1} }
|
||||
}
|
||||
|
||||
export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
|
||||
{
|
||||
prs{
|
||||
~p1 & ~p2 & ~p3 & ~p4 -> y+
|
||||
n1 | n2 -> y-
|
||||
}
|
||||
sizing {leak_adjust <- 1;
|
||||
p_n_mode <- 1;
|
||||
y {-1}}
|
||||
}
|
||||
}
|
||||
|
||||
xp018_cell_lib_async::A_1C1P_B_X1 cell1;
|
||||
|
||||
280
dataflow_neuro/cell_lib_std.act
Normal file
280
dataflow_neuro/cell_lib_std.act
Normal file
@ -0,0 +1,280 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library
|
||||
*
|
||||
* Copyright (c) 2020-2021 Rajit Manohar
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
namespace template {
|
||||
namespace dataflow_neuro {
|
||||
|
||||
export defproc TIELO_X1(bool! y; bool? vdd, vss)
|
||||
{
|
||||
y = vss;
|
||||
}
|
||||
|
||||
export defproc TIEHI_X1(bool! y; bool? vdd, vss)
|
||||
{
|
||||
y = vdd;
|
||||
}
|
||||
|
||||
/*-- inverters --*/
|
||||
|
||||
defproc inv (bool! y; bool? a, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a => y-
|
||||
}
|
||||
}
|
||||
|
||||
template<pint nf>
|
||||
defproc szinv <: inv()
|
||||
{
|
||||
[nf = 0 -> sizing { y {-1} }
|
||||
[] else -> sizing { y {-2*nf,svt,nf} }
|
||||
]
|
||||
}
|
||||
|
||||
export defcell INV_X1<: szinv<0>() { }
|
||||
export defcell INV_X2<: szinv<1>() { }
|
||||
export defcell INV_X4<: szinv<2>() { }
|
||||
export defcell INV_X8<: szinv<4>() { }
|
||||
|
||||
/*-- clock delay buffers --*/
|
||||
|
||||
template<pint N>
|
||||
defproc dbuf (bool! y; bool? a, vdd, vss)
|
||||
{
|
||||
{N > 0 : "Delay buffer needs at least one stage!"};
|
||||
bool sig[2*N+1];
|
||||
sig[0] = a;
|
||||
sig[2*N] = y;
|
||||
prs {
|
||||
(i:2*N: ~sig[i] <80;2> -> sig[i+1]+
|
||||
sig[i] <40;2> -> sig[i+1]-
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
export defproc CLKBUF1 <: dbuf<2>() { }
|
||||
export defproc CLKBUF2 <: dbuf<3>() { }
|
||||
export defproc CLKBUF3 <: dbuf<4>() { }
|
||||
|
||||
|
||||
/*-- signal buffers --*/
|
||||
|
||||
defproc buf (bool! y; bool? a, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs {
|
||||
a => _y-
|
||||
_y => y-
|
||||
}
|
||||
}
|
||||
|
||||
export defcell BUF_X2<: buf()
|
||||
{
|
||||
sizing { _y {-1}; y {-2} }
|
||||
}
|
||||
|
||||
export defcell BUF_X4<: buf()
|
||||
{
|
||||
sizing { _y {-1.5}; y {-4,2} }
|
||||
}
|
||||
|
||||
|
||||
/*-- simple gates --*/
|
||||
|
||||
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a | b => y-
|
||||
}
|
||||
sizing { y {-1} }
|
||||
}
|
||||
|
||||
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a | b | c => y-
|
||||
}
|
||||
sizing { y {-1} }
|
||||
}
|
||||
|
||||
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs {
|
||||
a | b => _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing { _y{-1}; y{-1} }
|
||||
}
|
||||
|
||||
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs {
|
||||
a | b => _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing { _y{-1}; y{-2} }
|
||||
}
|
||||
|
||||
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a & b => y-
|
||||
}
|
||||
sizing { y{-1} }
|
||||
}
|
||||
|
||||
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a & b & c => y-
|
||||
}
|
||||
sizing { y{-1} }
|
||||
}
|
||||
|
||||
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs {
|
||||
a & b => _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing { _y{-1}; y{-1} }
|
||||
}
|
||||
|
||||
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
bool _y;
|
||||
prs {
|
||||
a & b => _y-
|
||||
_y => y-
|
||||
}
|
||||
sizing { _y{-1}; y{-2} }
|
||||
}
|
||||
|
||||
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
bool _a, _b;
|
||||
prs {
|
||||
a => _a-
|
||||
b => _b-
|
||||
|
||||
[keeper=0] ~b & ~_a | ~_b & ~a -> y+
|
||||
_b & _a | b & a -> y-
|
||||
}
|
||||
sizing { _a{-1}; _b{-1}; y{-1} }
|
||||
}
|
||||
|
||||
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
|
||||
{
|
||||
bool _a, _b;
|
||||
prs {
|
||||
a => _a-
|
||||
b => _b-
|
||||
|
||||
[keeper=0] ~b & ~a | ~_b & ~_a -> y+
|
||||
b & _a | _b & a -> y-
|
||||
}
|
||||
sizing { _a{-1}; _b{-1}; y{-1} }
|
||||
}
|
||||
|
||||
export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss)
|
||||
{
|
||||
// y = !( S ? a : b )
|
||||
bool _S;
|
||||
prs {
|
||||
S => _S-
|
||||
|
||||
[keeper=0] ~a & ~_S | ~b & ~S -> y+
|
||||
a & S | b & _S -> y-
|
||||
}
|
||||
sizing { _S{-1}; y{-1} }
|
||||
}
|
||||
|
||||
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
(a | b) & c => y-
|
||||
}
|
||||
sizing { y{-1} }
|
||||
}
|
||||
|
||||
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a & b | c => y-
|
||||
}
|
||||
sizing { y{-1} }
|
||||
}
|
||||
|
||||
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
|
||||
{
|
||||
// y = !((a|b) & (c|d))
|
||||
prs {
|
||||
(a | b) & (c | d) => y-
|
||||
}
|
||||
sizing { y{-1} }
|
||||
}
|
||||
|
||||
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
|
||||
{
|
||||
prs {
|
||||
a & b | c & d => y-
|
||||
}
|
||||
sizing { y{-1} }
|
||||
}
|
||||
|
||||
|
||||
/*--- buffered transmission gates ---*/
|
||||
|
||||
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
|
||||
{
|
||||
bool _en;
|
||||
prs {
|
||||
en => _en-
|
||||
|
||||
~a & ~_en -> y+
|
||||
a & en -> y-
|
||||
}
|
||||
sizing { _en{-1}; y{-1} }
|
||||
}
|
||||
|
||||
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
|
||||
{
|
||||
bool _en;
|
||||
prs {
|
||||
en => _en-
|
||||
|
||||
~a & ~_en -> y+
|
||||
a & en -> y-
|
||||
}
|
||||
sizing { _en{-2}; y{-2,2} }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
144
dataflow_neuro/primitives.act
Normal file
144
dataflow_neuro/primitives.act
Normal file
@ -0,0 +1,144 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
import template::dataflow_neuro::cell_lib_std;
|
||||
import template::dataflow_neuro::cell_lib_async;
|
||||
import std::channel;
|
||||
open std::channel;
|
||||
|
||||
namespace template {
|
||||
namespace dataflow_neuro {
|
||||
|
||||
// @ole talk to rajit, we use valid the wrong way arround according to stdlib
|
||||
template<pbool reset; pint V; pint M>
|
||||
defchan gen_avMx1of2 <: chan(int<M>) (std::data::Mx1of2?!<M> d; bool!? a; bool!? v)
|
||||
{
|
||||
{ 0 <= V & std::ceil_log2(V) < M : "Initial token value out of range" };
|
||||
|
||||
methods {
|
||||
/*-- initialize channel, sender end --*/
|
||||
send_init {
|
||||
[ reset -> (,i:M: [ ((V >> i) & 1) = 0 -> d.d[i].f+ [] else -> d.d[i].t+ ]);[v]
|
||||
[] else -> (,i:M: d.d[i].t-,d.d[i].f-);[~v]
|
||||
]
|
||||
}
|
||||
|
||||
/*-- set output data --*/
|
||||
set {
|
||||
(,i:M: [((self >> i) & 1) = 0 -> d.d[i].f+ [] else -> d.d[i].t+ ]);[v]
|
||||
}
|
||||
|
||||
/*-- finish synchronization --*/
|
||||
send_up {
|
||||
[a]
|
||||
}
|
||||
|
||||
/*-- reset part of the protocol --*/
|
||||
send_rest {
|
||||
(,i:M: d.d[i].t-,d.d[i].f-);[~v],[~a]
|
||||
}
|
||||
|
||||
/*-- initialize channel, receiver end --*/
|
||||
recv_init {
|
||||
v-;a-
|
||||
}
|
||||
|
||||
/*-- get value --*/
|
||||
get {
|
||||
[(&i:M: d.d[i].t | d.d[i].f)];
|
||||
self := 0;
|
||||
(;i:M: [ d.d[i].t -> self := self | (1 << i)
|
||||
[] else -> skip
|
||||
]
|
||||
)
|
||||
}
|
||||
|
||||
/*-- finish synchronization action --*/
|
||||
recv_up {
|
||||
v+,a+
|
||||
}
|
||||
|
||||
/*-- reset part of the protocol --*/
|
||||
recv_rest {
|
||||
[(&i:M:~d.d[i].t & ~d.d[i].f)];v-,a-
|
||||
}
|
||||
|
||||
/*-- probe expression on receiver --*/
|
||||
// i think this deadlocks with recv_up
|
||||
recv_probe = v;
|
||||
|
||||
// no sender probe
|
||||
}
|
||||
}
|
||||
export defchan avMx1of2 <: gen_avMx1of2<false,0> () { }
|
||||
export defchan avrMx1of2 <: gen_avMx1of2<true,0> () { }
|
||||
|
||||
|
||||
/**
|
||||
* the buffer template gives you a standart buffer of bitwidth N
|
||||
*
|
||||
*/
|
||||
export template<pint N>
|
||||
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; rsp reset; power supply) {
|
||||
//control
|
||||
bool _en,_en_X,_preset_X,_sreset_X;
|
||||
A_3C_RB_X4 inack_ctl(c1=en_X,c2=in.v,c3=out.v,y=in.a,pr_B=_preset_X,sr_B=_sreset_X,vdd=supply.vdd,vss=supply.vss);
|
||||
A_1C1P_X1 en_ctl(c1=in.a,p1=out.v,y=_en,vdd=supply.vdd,vss=supply.vss);
|
||||
sigbuf en_buf<N*2>(a=_en, y=_en_X, power=supply);
|
||||
sigbuf preset_buf<N*2>(a=reset.p,y=preset_X, power=supply);
|
||||
sigbuf sreset_buf<N*2>(a=reset.s,y=sreset_X, power=supply);
|
||||
|
||||
//validity
|
||||
bool _in_v;
|
||||
ctree vc<N>(in=in.d,y=_in_v, power=supply);
|
||||
sigbuf in_v_buf<12>(a=_in_v, y=in.v);
|
||||
|
||||
//function
|
||||
bool _out_a_BX, _out_a_B;
|
||||
A_2C1N_RB_X4 f_buf_func[N];
|
||||
A_2C1N_RB_X4 t_buf_func[N];
|
||||
INV_X1 out_a_inv(a=out.a,y=_out_a_B);
|
||||
sigbuf out_a_B_buf<N*2>(a=_out_a_B,y=_out_a_BX);
|
||||
// check if you can also do single var to array connect a=b[N]
|
||||
// and remove them from the loop
|
||||
(i:N:
|
||||
f_buf_func[i].y=out.d.d[i].f;
|
||||
t_buf_func[i].y=out.d.d[i].t;
|
||||
f_buf_func[i].c1=_en_X;
|
||||
t_buf_func[i].c1=_en_X;
|
||||
f_buf_func[i].c2=_out_a_BX;
|
||||
t_buf_func[i].c2=_out_a_BX;
|
||||
f_buf_func[i].n1=in.d.d[i].f;
|
||||
t_buf_func[i].n1=in.d.d[i].t;
|
||||
f_buf_func[i].pr_B=_preset_X;
|
||||
t_buf_func[i].pr_B=_preset_X;
|
||||
f_buf_func[i].sr_B=_sreset_X;
|
||||
t_buf_func[i].sr_B=_sreset_X;
|
||||
f_buf_func[i].vdd=supply.vdd;
|
||||
t_buf_func[i].vdd=supply.vdd;
|
||||
f_buf_func[i].vss=supply.vss;
|
||||
t_buf_func[i].vss=supply.vss;
|
||||
)
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user