added license, moved cell libs into repo

added buffer (not tested),
This commit is contained in:
2022-02-21 00:14:02 +01:00
parent 4bf73a8566
commit 48b691d7d4
17 changed files with 1571 additions and 91 deletions

85
test/repeat_unit.sh Executable file
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# repeatedly run prsim on one unit_test's PRs
bold=$(tput bold)
normal=$(tput sgr0)
und=$(tput smul)
i=${unit}
proc="$i<>"
echo ""
echo "${bold}******************************************"
echo "* ${i} repetitions , show warnings=${warning}*"
echo "******************************************${normal}"
cd "unit_tests"
echo "${bold}... checking aflat${normal}"
# check aflat
if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
then
echo "${bold}... aflat complete, checking in prsim${normal}"
# run prsim on prs
(($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
then
echo "FAILED in first prsim"
else
# show warnings setting
if [ "${warning}" = "1" ];
then
echo "${bold}Exit on prsim warnings turned ON${normal}"
else
echo "${bold}Exit on prsim warnings turned OFF${normal}"
fi
echo ""
# begin prsim test loop
has_failed=0
iter=0
echo "${bold}using random_seed${normal}"
echo "\nusing random_seed" >> "$i/prsim.out"
while [ has_failed=0 ]
do
# write prsim test file with random seed appended to top of file
(echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
(cat "$i/test.prsim" >> "$i/test_rand.prsim");
(echo "\nTEST $iter\n" >> "$i/prsim.out");
# validate prsim output
if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
then
if [ "${warning}" = "1" ];
then
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
else
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
fi
else
has_failed=1
exit 0
fi
done
(cd ".."; pwd);
exit 1
fi
else
echo "FAILED in aflat conversion"
fi

73
test/run.sh Executable file
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#!/bin/sh
fail=0
faildirs=""
proc=""
bold=$(tput bold)
normal=$(tput sgr0)
und=$(tput smul)
faildirs=""
failed=0
#
# run_test name [option]
#
run_test () {
echo "Testing ${bold}$1 ${normal}"
# clear run directory
if [ -d $1/run ]; then
rm -rf $1/run
fi
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed ***${normal}"
faildirs="${faildirs} ${1}-sim"
failed=1
echo
fi
else
echo "${bold}*** circuit construction failed ***${normal}"
faildirs="${faildirs} ${1}-ckt"
failed=1
echo
fi
}
if [ ! ( command -v aflat && command -v prsim ) ];
then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi
if [ ! -d "unit_tests" ];
then
echo "${bold}Error:${bold} no unit_tests directory."
exit 1
fi
cd "unit_tests"
# run all test except single one is specified
if [ -z $1 ]; then
for i in *
do
if [ -d $i -a -f $i/test.act ]; then
run_test $i
fi
done
else
run_test $1
fi
if [ $failed -eq 1 ]; then
echo ""
echo "${bold}*********************************"
echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
echo "*********************************${normal}"
fi
exit $failed

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import template::dataflow_neuro
defproc fifo3_8bit (avMx1of2<8> A; avMx1of2<8> Y)
{
avMx1of2<8> _0to1,_1to2;
buffer<8> buf0 (.in=A, .out=_0to1);
buffer<8> buf1 (.in=_0to1, .out=_1to2);
buffer<8> buf2 (.in=_1to2, .out=Y);
}

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set-channel-neutral "t.A" 8
set t.Y.a 0
cycle
system "echo 'reset completed'"
status X
set Reset 0
mode run
cycle
assert t.A.a 0
assert-channel-neutral "t.Y" 8
set-channel-valid "t.A" 8 2
system "echo 'sending first set A'"
cycle
assert t.A.a 1
set-channel-neutral "t.A" 8
cycle
assert t.A.a 0
system "echo 'checking first set'"
assert-channel-valid "t.Y" 8 2
set t.Y.a 1
cycle
assert-channel-neutral "t.Y" 8
set t.Y.a 0
system "echo 'sending second set'"
set-channel-valid "t.A" 8 95
cycle
assert t.A.a 1
set-channel-neutral "t.A" 8
cycle
system "echo 'checking second set'"
assert t.A.a 0
assert-channel-valid "t.Y" 8 95

124
test/unit_tests/helper.scm Normal file
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(define % (lambda (x y) (- x (* y (truncate (/ x y))))))
(define dualrail-bit
(lambda (x i)
(let ((tmp
(string-append x
(string-append ".d["
(string-append (number->string i) "]")
)
)
))
(list (string-append tmp ".f") (string-append tmp ".t"))
)
)
)
(define assert-var-bit
(lambda (x i v)
(let ((tmp (dualrail-bit x i)))
(begin
(assert (car tmp) (- 1 v))
(assert (cadr tmp) v)
)
)
)
)
(define assert-var-int
(lambda (x width value)
(letrec ((assert-one-bit
(lambda (v i)
(cond
((=? i width) #t)
(#t (begin
(assert-var-bit x i (% v 2))
(assert-one-bit (truncate (/ v 2)) (+ i 1))
)
)
)
)
))
(assert-one-bit value 0)
)
)
)
(define assert-channel-valid
(lambda (ch width value)
(assert-var-int (string-append ch ".d") width value)
)
)
(define assert-channel-neutral
(lambda (ch width)
(letrec ((helper
(lambda (i)
(cond
((=? i width) #t)
(#t (let ((tmp (dualrail-bit (string-append ch ".d") i)))
(begin
(assert (car tmp) 0)
(assert (cadr tmp) 0)
(helper (+ 1 i))
)
)
)
)
)
)
)
(helper 0)
)
)
)
(define set-channel-neutral
(lambda (ch width)
(letrec ((ch-name (string-append ch ".d"))
(helper
(lambda (i)
(cond
((=? i width) #t)
(#t (let ((tmp (dualrail-bit ch-name i)))
(begin
(set (car tmp) 0)
(set (cadr tmp) 0)
(helper (+ 1 i))
)
)
)
)
)
))
(helper 0)
)
)
)
(define set-channel-valid
(lambda (ch width val)
(letrec ((ch-name (string-append ch ".d"))
(helper
(lambda (i v)
(cond
((=? i width) #t)
(#t (let ((tmp (dualrail-bit ch-name i)))
(begin
(set (car tmp) (- 1 (% v 2)))
(set (cadr tmp) (% v 2))
(helper (+ 1 i) (truncate (/ v 2)))
)
)
)
)
)
))
(helper 0 val)
)
)
)
(define assert-var-bool (lambda (x v) (assert-var-int x 1 v)))

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initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
mode reset
set Reset 1
cycle
status U