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final final generation of tdc_glue i swear

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This commit is contained in:
alexmadison 2022-06-23 17:51:16 +02:00
parent 144d89fb90
commit 4e01e252b8
144 changed files with 262069 additions and 319051 deletions
test/unit_tests/texel_dualcore_glue
netlist.vnetlist_clean.v
split_modules
texel__dualcore__glue/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_37_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ctree_39_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__2d__synapse__hs_315_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_39_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0delayprog_32_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit_330_730_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit_331_731_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit__msb_330_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0demux__bit__msb_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0dummy__neuron__core_358_790_715_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_73_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_313_73_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0fifo_313_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_329_73_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0fifo_329_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_330_73_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0fifo_330_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_331_73_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0fifo_331_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_332_73_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0fifo_332_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fifo_37_73_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0fifo_37_75_4/netlist
master.tagverilog.v
tmpl_0_0dataflow__neuro_0_0fork_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0merge_331_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0merge_332_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0nrn__hs__2d/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_315_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_34_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_358_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_364_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0ortree_38_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0register__wr__array_36_723_764_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_3124_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4/netlist
verilog.v
tmpl_0_0dataflow__neuro_0_0sigbuf_323_4/netlist
verilog.v
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174775
test/unit_tests/texel_dualcore_glue/netlist.v

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174600
test/unit_tests/texel_dualcore_glue/netlist_clean.v

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58566
test/unit_tests/texel_dualcore_glue/split_modules/texel__dualcore__glue/netlist/verilog.v

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11868
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0and__grid_315_7348_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

6
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/verilog.v

@ -7,10 +7,10 @@ module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vs
output out;
// -- signals ---
wire Iin1 ;
wire out ;
wire Iin0 ;
wire Iin2 ;
wire Iin0 ;
wire out ;
wire Iin1 ;
// --- instances
AND3_X1 Iand3s0 (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));

8
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/verilog.v

@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0andtree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out,
output out;
// -- signals ---
wire Itmp5 ;
wire Iin0 ;
wire Itmp4 ;
wire out ;
wire Iin2 ;
wire Iin3 ;
wire Iin2 ;
wire Iin1 ;
wire out ;
wire Iin0 ;
wire Itmp5 ;
// --- instances
AND2_X1 Iand2s0 (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

10
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/verilog.v

@ -9,14 +9,14 @@ module tmpl_0_0dataflow__neuro_0_0andtree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin0 ;
wire Iin3 ;
wire out ;
wire Iin1 ;
wire Iin4 ;
wire Iin3 ;
wire Iin1 ;
wire out ;
wire Itmp6 ;
wire Iin0 ;
wire Itmp5 ;
wire Iin2 ;
wire Itmp6 ;
// --- instances
AND3_X1 Iand3s0 (.y(Itmp6 ), .a(Iin2 ), .b(Iin3 ), .c(Iin4 ), .vdd(vdd), .vss(vss));

10
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/verilog.v

@ -11,15 +11,15 @@ module tmpl_0_0dataflow__neuro_0_0andtree_36_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
// -- signals ---
wire Itmp8 ;
wire Iin0 ;
wire Iin3 ;
wire Iin5 ;
wire Iin2 ;
wire out ;
wire Iin0 ;
wire Itmp6 ;
wire Iin3 ;
wire Iin1 ;
wire Iin4 ;
wire out ;
wire Itmp6 ;
wire Itmp7 ;
wire Iin2 ;
// --- instances
AND3_X1 Iand3s0 (.y(out), .a(Itmp6 ), .b(Itmp7 ), .c(Itmp8 ), .vdd(vdd), .vss(vss));

24
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/verilog.v

@ -13,22 +13,22 @@ module tmpl_0_0dataflow__neuro_0_0andtree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin3 ;
wire Iin5 ;
wire Iin8 ;
wire Itmp13 ;
wire Iin1 ;
wire Iin7 ;
wire Itmp11 ;
wire Itmp9 ;
wire out ;
wire Iin0 ;
wire Iin6 ;
wire Itmp12 ;
wire Iin5 ;
wire Iin2 ;
wire Iin8 ;
wire Iin4 ;
wire Iin1 ;
wire Itmp9 ;
wire Itmp14 ;
wire Itmp13 ;
wire Itmp11 ;
wire Itmp12 ;
wire Itmp10 ;
wire Iin7 ;
wire Iin2 ;
wire Iin6 ;
wire Itmp14 ;
wire Iin3 ;
// --- instances
AND3_X1 Iand3s0 (.y(Itmp12 ), .a(Iin6 ), .b(Iin7 ), .c(Iin8 ), .vdd(vdd), .vss(vss));

100
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/verilog.v

@ -62,65 +62,65 @@ module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d15_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d19_d0 ;
wire Isb_in ;
wire Iin_d_d0_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d12_d0 ;
wire Isb_in ;
wire Iin_d_d19_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d17_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d13_d0 ;
// --- instances

120
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/verilog.v

@ -66,70 +66,70 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d23_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d31_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d2_d0 ;
wire Isb_in ;
wire Iin_d_d9_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d6_d0 ;
wire Isb_in ;
wire Iin_d_d28_d0 ;
wire Iin_d_d17_d1 ;
output Iout_d_d31_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d16_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

110
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v

@ -66,70 +66,70 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d25_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d31_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d19_d1 ;
wire Isb_in ;
wire Iin_d_d9_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d14_d0 ;
wire Isb_in ;
wire Iin_d_d8_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d31_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d11_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

24
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v

@ -18,22 +18,22 @@ module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
// -- signals ---
wire Iin_d_d6_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d7_d0 ;
wire Iin_d_d4_d1 ;
wire Isb_in ;
wire Iin_d_d5_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d6_d0 ;
output Iout_d_d7_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d5_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));

14
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v

@ -9,14 +9,14 @@ module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d
input Iout_a ;
// -- signals ---
wire _y1_arb ;
wire _y2_arb ;
wire Iout_a ;
output Iout_d_d0 ;
output Iin1_a ;
wire Iin2_d_d0 ;
output Iin2_a ;
wire Iin1_d_d0 ;
output Iout_d_d0 ;
wire Iout_a ;
wire _y2_arb ;
wire _y1_arb ;
output Iin2_a ;
wire Iin2_d_d0 ;
output Iin1_a ;
// --- instances
A_2C_B_X1 Iack_cell1 (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));

102
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/verilog.v

@ -35,64 +35,64 @@ module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 ,
input Iout_a ;
// -- signals ---
wire Iin11_d_d0 ;
output Iout_d_d0 ;
wire Iout_a ;
wire Itmp21_d_d0 ;
wire Itmp16_d_d0 ;
output Iin9_a ;
output Iin7_a ;
wire Itmp17_d_d0 ;
output Iin14_a ;
wire Itmp15_a ;
wire Iin8_d_d0 ;
wire Iin7_d_d0 ;
output Iin6_a ;
output Iin5_a ;
output Iin3_a ;
output Iin2_a ;
wire Itmp27_a ;
wire Itmp25_a ;
output Iin12_a ;
wire Iin9_d_d0 ;
output Iin8_a ;
wire Itmp19_a ;
wire Itmp19_d_d0 ;
output Iin6_a ;
wire Iin14_d_d0 ;
output Iin7_a ;
output Iin0_a ;
wire Itmp15_d_d0 ;
wire Itmp21_d_d0 ;
output Iin13_a ;
output Iin5_a ;
wire Iin10_d_d0 ;
output Iin14_a ;
wire Itmp25_d_d0 ;
wire Iin2_d_d0 ;
wire Itmp18_a ;
wire Iin5_d_d0 ;
wire Itmp26_d_d0 ;
wire Itmp17_a ;
wire Iin1_d_d0 ;
wire Iin13_d_d0 ;
wire Itmp20_d_d0 ;
output Iin4_a ;
wire Itmp16_a ;
wire Itmp27_d_d0 ;
wire Itmp21_a ;
wire Iin12_d_d0 ;
output Iin10_a ;
wire Itmp17_d_d0 ;
wire Itmp28_d_d0 ;
wire Itmp24_d_d0 ;
wire Iin3_d_d0 ;
wire Itmp26_a ;
wire Iin7_d_d0 ;
output Iin2_a ;
wire Itmp28_a ;
wire Itmp24_a ;
wire Itmp23_d_d0 ;
output Iin8_a ;
wire Itmp17_a ;
output Iin0_a ;
wire Iin0_d_d0 ;
wire Itmp28_d_d0 ;
wire Itmp21_a ;
wire Itmp20_a ;
wire Itmp20_d_d0 ;
wire Itmp18_a ;
wire Itmp18_d_d0 ;
wire Iin4_d_d0 ;
wire Itmp26_a ;
wire Iin6_d_d0 ;
wire Itmp27_d_d0 ;
wire Itmp26_d_d0 ;
wire Itmp24_d_d0 ;
wire Itmp23_a ;
wire Itmp19_a ;
wire Iin1_d_d0 ;
output Iin4_a ;
output Iin1_a ;
wire Iin14_d_d0 ;
wire Iin12_d_d0 ;
wire Iin3_d_d0 ;
wire Iin13_d_d0 ;
wire Itmp25_d_d0 ;
output Iin10_a ;
wire Itmp19_d_d0 ;
wire Itmp16_d_d0 ;
output Iin11_a ;
wire Iin10_d_d0 ;
wire Iin2_d_d0 ;
wire Itmp15_d_d0 ;
output Iin13_a ;
wire Iin9_d_d0 ;
output Iout_d_d0 ;
wire Iin5_d_d0 ;
wire Itmp16_a ;
wire Itmp27_a ;
wire Iin11_d_d0 ;
wire Iin8_d_d0 ;
wire Iin6_d_d0 ;
output Iin3_a ;
wire Itmp15_a ;
wire Iin0_d_d0 ;
wire Itmp23_d_d0 ;
output Iin12_a ;
output Iin9_a ;
wire Iin4_d_d0 ;
wire Itmp23_a ;
output Iin1_a ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));

32
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/verilog.v

@ -17,27 +17,27 @@ module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 ,
input Iout_a ;
// -- signals ---
output Iout_d_d0 ;
output Iin1_a ;
wire Itmp10_d_d0 ;
output Iin5_a ;
wire Iin5_d_d0 ;
wire Itmp10_a ;
wire Iin4_d_d0 ;
wire Itmp7_d_d0 ;
wire Itmp10_d_d0 ;
wire Itmp6_a ;
wire Iout_a ;
output Iin3_a ;
wire Iin3_d_d0 ;
output Iin0_a ;
wire Iin2_d_d0 ;
wire Itmp7_a ;
wire Itmp9_d_d0 ;
output Iin4_a ;
wire Iin5_d_d0 ;
wire Itmp7_d_d0 ;
wire Itmp9_a ;
wire Itmp6_d_d0 ;
wire Iin3_d_d0 ;
wire Iin1_d_d0 ;
output Iin2_a ;
wire Itmp7_a ;
output Iin3_a ;
output Iin5_a ;
output Iout_d_d0 ;
output Iin0_a ;
wire Itmp9_d_d0 ;
wire Iout_a ;
wire Iin2_d_d0 ;
output Iin1_a ;
wire Itmp6_d_d0 ;
wire Iin4_d_d0 ;
output Iin4_a ;
wire Iin0_d_d0 ;
// --- instances

270
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/verilog.v

@ -110,156 +110,156 @@ module tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4(Iin_d0 , Iin_d1 , Iin_d2 ,
input reset_B;
// -- signals ---
output Iout_d_d20_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d12_d1 ;
wire Iin_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d30_d1 ;
wire I_reset_BXX0 ;
wire Idly_cfg1 ;
wire Idly2_out ;
wire I_inB7 ;
output Iout_d_d23_d1 ;
wire Iin_d13 ;
output Iout_d_d23_d0 ;
output Iout_d_d16_d0 ;
wire I_inB12 ;
wire Iin_d12 ;
wire I_inB27 ;
wire I_inB21 ;
output Iout_d_d9_d0 ;
output Iout_d_d25_d1 ;
wire Idly_cfg2 ;
wire Idly_cfg20 ;
wire Iin_d20 ;
wire Iin_d31 ;
wire Iin_d16 ;
wire Iin_d29 ;
output Iout_d_d6_d0 ;
output Iout_d_d15_d0 ;
wire _en ;
output Iout_d_d11_d1 ;
wire Iin_d18 ;
wire Iin_d27 ;
wire _reqX ;
wire I_inB4 ;
wire Iin_d8 ;
output Iout_d_d14_d0 ;
wire Iin_r ;
wire If_buf_func31_c2 ;
output Iout_d_d28_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d4_d0 ;
wire I_inB23 ;
wire Iin_d1 ;
wire I_inB15 ;
output Iout_d_d7_d0 ;
output Iout_d_d31_d0 ;
wire Iin_d2 ;
output Iout_d_d30_d0 ;
wire I_inB2 ;
wire Iin_d21 ;
wire Iin_d24 ;
output Iout_d_d19_d0 ;
output Iout_d_d19_d1 ;
wire Idly_cfg3 ;
wire Idly_cfg21 ;
wire I_inB3 ;
wire Iin_d17 ;
wire Iin_d23 ;
wire _req ;
wire I_inB11 ;
wire Iin_d28 ;
output Iout_d_d8_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d0_d1 ;
wire I_inB28 ;
output Iout_d_d3_d0 ;
wire I_inB30 ;
wire reset_B;
wire Iin_d9 ;
output Iout_d_d31_d1 ;
output Iout_d_d15_d1 ;
wire Iin_d6 ;
wire _out_a_B ;
output Iout_d_d1_d1 ;
output Iout_d_d13_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d4 ;
output Iout_d_d26_d1 ;
wire I_inB22 ;
output Iout_d_d7_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d0 ;
wire I_inB26 ;
output Iout_d_d21_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d22 ;
wire I_inB31 ;
output Iout_d_d29_d0 ;
wire I_inB23 ;
output Iout_d_d26_d0 ;
wire I_inB2 ;
wire Iin_d7 ;
wire Iin_d9 ;
wire Iin_d26 ;
output Iout_d_d17_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d20_d1 ;
wire _req ;
wire I_inB20 ;
wire Iin_d29 ;
wire I_inB12 ;
wire Iin_d27 ;
output Iout_d_d4_d0 ;
wire I_inB4 ;
wire Iin_d25 ;
output Iout_d_d16_d0 ;
output Iout_d_d18_d1 ;
wire Iin_d0 ;
wire Iin_d16 ;
wire _req_slowfall ;
wire Idly_cfg3 ;
output Iout_d_d2_d0 ;
output Iout_d_d0_d1 ;
wire Idly_cfg1 ;
wire I_inB13 ;
wire Iin_d24 ;
wire Iin_d10 ;
wire I_inB24 ;
output Iout_d_d28_d0 ;
output Iout_d_d7_d1 ;
wire I_inB7 ;
wire I_inB9 ;
output Iout_d_d10_d1 ;
output Iout_d_d16_d1 ;
wire I_inB8 ;
wire I_reqXX0 ;
output Iout_d_d17_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d15_d1 ;
wire I_inB6 ;
wire Iin_d14 ;
output Iout_d_d9_d0 ;
wire _reqX ;
wire I_inB26 ;
output Iout_d_d0_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d8 ;
output Iout_d_d12_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d23_d0 ;
wire I_inB27 ;
output Iout_d_d13_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d2 ;
output Iout_d_d3_d1 ;
wire Idly_cfg21 ;
wire Idly_cfg2 ;
wire Iin_d17 ;
wire Iin_r ;
output Iout_d_d11_d0 ;
wire Iin_d19 ;
output Iout_d_d30_d1 ;
output Iout_d_d22_d1 ;
wire Iin_d11 ;
output Iout_d_d13_d1 ;
wire _reset_BX ;
wire Idly_cfg0 ;
wire Idly_cfg20 ;
wire Iin_d12 ;
wire I_inB28 ;
wire Idly2_out ;
wire reset_B;
output Iout_d_d15_d0 ;
output Iout_d_d31_d1 ;
output Iout_d_d21_d1 ;
wire I_inB30 ;
output Iout_d_d1_d1 ;
wire I_inB25 ;
output Iout_d_d14_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d5 ;
wire Iin_d18 ;
wire If_buf_func31_c2 ;
output Iout_d_d10_d0 ;
output Iout_d_d9_d1 ;
wire I_reset_BXX0 ;
wire Iout_a ;
wire Iin_d6 ;
wire I_inB17 ;
wire Iin_d28 ;
wire _en ;
wire Iin_d30 ;
output Iout_d_d24_d0 ;
output Iout_d_d3_d1 ;
wire Ien_buf_out0 ;
wire Iin_d7 ;
wire I_inB13 ;
output Iout_d_d5_d1 ;
wire I_inB9 ;
output Iout_d_d24_d1 ;
wire I_inB18 ;
wire Iin_d19 ;
wire Iin_d26 ;
output Iout_d_d23_d1 ;
wire I_inB29 ;
output Iout_d_d18_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d2_d1 ;
wire I_inB25 ;
output Iin_a ;
wire _reset_BX ;
wire I_inB6 ;
wire I_inB20 ;
wire I_inB31 ;
output Iout_d_d26_d0 ;
output Iout_d_d14_d1 ;
wire Iout_a ;
wire I_inB10 ;
wire I_reqXX0 ;
output Iout_d_d27_d0 ;
wire I_inB3 ;
wire I_inB16 ;
wire Iin_d14 ;
wire Iin_d22 ;
output Iout_d_d17_d0 ;
output Iout_d_d29_d0 ;
wire I_inB1 ;
output Iout_d_d22_d0 ;
output Iout_d_d22_d1 ;
output Iout_d_d11_d0 ;
output Iout_d_d12_d0 ;
wire I_inB24 ;
output Iout_d_d0_d0 ;
output Iout_d_d1_d0 ;
wire I_inB19 ;
output Iout_d_d2_d0 ;
output Iout_d_d4_d1 ;
wire Idly_cfg0 ;
wire I_inB5 ;
wire Iin_d15 ;
wire Iin_d5 ;
wire I_inB15 ;
output Iout_d_d21_d1 ;
wire Iin_d11 ;
output Iout_d_d25_d0 ;
output Iout_d_d5_d1 ;
wire I_inB18 ;
wire I_inB0 ;
wire I_inB14 ;
wire Iin_d25 ;
wire Iout_v ;
wire I_inB1 ;
wire I_inB10 ;
output Iout_d_d27_d1 ;
wire _req_slowfall ;
wire Iin_d10 ;
output Iout_d_d17_d1 ;
output Iout_d_d19_d1 ;
wire Ien_buf_out0 ;
wire I_inB14 ;
wire Iin_d21 ;
wire I_inB29 ;
wire I_inB21 ;
output Iout_d_d1_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d24_d1 ;
output Iin_a ;
wire Iout_v ;
wire I_inB11 ;
output Iout_d_d6_d0 ;
wire I_inB5 ;
wire Iin_d20 ;
output Iout_d_d27_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d3 ;
wire I_inB17 ;
output Iout_d_d5_d0 ;
wire Iin_d4 ;
wire _out_a_B ;
wire Iin_d15 ;
wire I_inB19 ;
wire Iin_d23 ;
wire Iin_d31 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

110
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/verilog.v

@ -60,70 +60,70 @@ module tmpl_0_0dataflow__neuro_0_0buffer_313_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d4_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d3_d1 ;
wire Iin_d_d9_d1 ;
output Iout_d_d10_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d7_d1 ;
wire reset_B;
wire Iin_d_d7_d1 ;
wire Iin_d_d12_d1 ;
wire _out_a_B ;
wire _en ;
wire Iin_d_d6_d1 ;
wire Iin_d_d2_d1 ;
wire _reset_BX ;
output Iout_d_d2_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d10_d0 ;
wire Iin_d_d11_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d5_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d11_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d1_d1 ;
wire Iin_d_d11_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d1_d1 ;
wire _in_v ;
output Iout_d_d12_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d9_d1 ;
output Iout_d_d3_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d8_d1 ;
output Iout_d_d8_d0 ;
wire Iout_a ;
output Iout_d_d4_d0 ;
wire Iin_d_d2_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d11_d1 ;
output Iin_v ;
output Iout_d_d8_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d3_d0 ;
wire _reset_BX ;
output Iout_d_d6_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d10_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d7_d0 ;
output Iout_d_d0_d1 ;
wire Iout_a ;
output Iin_v ;
output Iout_d_d9_d1 ;
wire Iout_v ;
output Iout_d_d11_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d10_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d12_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d8_d0 ;
wire I_out_a_BX0 ;
output Iout_d_d12_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d0_d1 ;
wire _in_v ;
output Iout_d_d7_d0 ;
output Iout_d_d9_d0 ;
output Iout_d_d6_d0 ;
output Iout_d_d3_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
wire _out_a_B ;
output Iout_d_d2_d1 ;
wire Iout_v ;
wire Iin_d_d12_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d0_d1 ;
output Iin_a ;
output Iout_d_d4_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d5_d1 ;
wire _en ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

242
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/verilog.v

@ -124,134 +124,134 @@ module tmpl_0_0dataflow__neuro_0_0buffer_329_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d15_d1 ;
output Iout_d_d14_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d23_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d25_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d26_d0 ;
output Iout_d_d13_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d5_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d6_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d12_d0 ;
wire _in_v ;
output Iout_d_d20_d1 ;
output Iout_d_d2_d1 ;
wire Ien_buf_out0 ;
wire Iin_d_d11_d0 ;
wire _reset_BX ;
output Iout_d_d8_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d2_d0 ;
output Iout_d_d28_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d10_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d24_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d7_d0 ;
wire I_out_a_BX0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d0_d0 ;
wire Iout_a ;
wire Iin_d_d17_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d10_d1 ;
wire _out_a_B ;
output Iout_d_d27_d1 ;
wire Iin_d_d23_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d17_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d22_d0 ;
output Iout_d_d9_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d11_d1 ;
output Iin_a ;
output Iout_d_d20_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d13_d1 ;
output Iin_v ;
output Iout_d_d18_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d6_d1 ;
wire Iin_d_d6_d0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d18_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d0_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d_d0_d1 ;
wire Iout_v ;
wire reset_B;
wire Iin_d_d5_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d0_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d24_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d6_d0 ;
wire _in_v ;
output Iout_d_d12_d1 ;
output Iout_d_d11_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d8_d1 ;
wire _en ;
wire Iin_d_d26_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d22_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d2_d1 ;
wire Iin_d_d8_d0 ;
output Iout_d_d22_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d13_d0 ;
wire _en ;
output Iout_d_d26_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d10_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d17_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d3_d1 ;
output Iin_a ;
wire Iin_d_d27_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d12_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d13_d0 ;
output Iout_d_d23_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d13_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d18_d1 ;
wire Iout_v ;
output Iout_d_d7_d1 ;
output Iout_d_d5_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d9_d1 ;
wire _reset_BX ;
output Iout_d_d19_d0 ;
wire Iin_d_d1_d1 ;
wire _out_a_B ;
output Iout_d_d14_d0 ;
output Iout_d_d9_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d12_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d8_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d_d28_d0 ;
wire Ien_buf_out0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d21_d1 ;
output Iin_v ;
output Iout_d_d7_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d16_d1 ;
wire Iin_d_d21_d0 ;
wire Iout_a ;
output Iout_d_d16_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d5_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d21_d1 ;
wire Iin_d_d0_d1 ;
output Iout_d_d21_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d3_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d1_d0 ;
wire I_out_a_BX0 ;
output Iout_d_d25_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d25_d1 ;
wire reset_B;
wire Iin_d_d20_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d2_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d0_d0 ;
wire Iin_d_d18_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

246
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_330_4/netlist/verilog.v

@ -128,138 +128,138 @@ module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
wire Iin_d_d5_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d27_d1 ;
output Iin_a ;
wire Iin_d_d0_d0 ;
wire Iout_a ;
wire Iin_d_d13_d1 ;
wire Iin_d_d21_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d3_d0 ;
wire Iin_d_d25_d0 ;
output Iout_d_d24_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d26_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d_d11_d1 ;
wire _reset_BX ;
wire Iin_d_d4_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d18_d1 ;
wire I_reset_BXX0 ;
wire _in_v ;
wire Iin_d_d7_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d28_d1 ;
output Iin_v ;
wire Iin_d_d1_d0 ;
output Iout_d_d12_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d11_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d20_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d28_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d27_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d5_d1 ;
wire Iout_a ;
wire Iin_d_d24_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d_d7_d0 ;
output Iin_v ;
wire Iin_d_d4_d1 ;
wire Iin_d_d25_d0 ;
output Iout_d_d28_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d6_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d_d0_d1 ;
wire Iout_v ;
wire Iin_d_d12_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d11_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d25_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d21_d1 ;
wire Ien_buf_out0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d11_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d8_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d11_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d17_d1 ;
output Iout_d_d6_d1 ;
output Iin_a ;
output Iout_d_d24_d0 ;
wire _in_v ;
wire Iin_d_d27_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d13_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d17_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d14_d0 ;
output Iout_d_d8_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d21_d0 ;
wire Iin_d_d5_d0 ;
output Iout_d_d23_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d10_d0 ;
output Iout_d_d23_d1 ;
wire _reset_BX ;
wire Iin_d_d26_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d2_d1 ;
wire reset_B;
wire Iin_d_d8_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d18_d1 ;
wire _en ;
wire Iin_d_d19_d1 ;
output Iout_d_d17_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d16_d0 ;
output Iout_d_d1_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d17_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d10_d0 ;
wire Iin_d_d14_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d9_d0 ;
output Iout_d_d19_d0 ;
wire _out_a_B ;
wire Iin_d_d29_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d16_d0 ;
output Iout_d_d17_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d22_d1 ;
wire Iin_d_d18_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d27_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d13_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d23_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d13_d1 ;
wire Iout_v ;
wire Iin_d_d27_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d8_d1 ;
output Iout_d_d15_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d_d7_d1 ;
wire Iin_d_d17_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d19_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d3_d0 ;
wire I_out_a_BX0 ;
wire Iin_d_d3_d0 ;
output Iout_d_d24_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d24_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d4_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d27_d1 ;
wire Iin_d_d7_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d23_d1 ;
wire Iin_d_d25_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d19_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d27_d1 ;
output Iout_d_d17_d0 ;
wire _out_a_B ;
wire Iin_d_d15_d1 ;
wire _en ;
output Iout_d_d15_d1 ;
output Iout_d_d1_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

256
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/verilog.v

@ -132,142 +132,142 @@ module tmpl_0_0dataflow__neuro_0_0buffer_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d25_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d1_d1 ;
wire I_out_a_BX0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d15_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d17_d1 ;
wire reset_B;
output Iout_d_d3_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d23_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d25_d1 ;
output Iout_d_d22_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d27_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d16_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d8_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d6_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d20_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d27_d0 ;
wire Iout_v ;
wire Iin_d_d5_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d14_d0 ;
wire _reset_BX ;
wire Iin_d_d1_d0 ;
wire Iin_d_d30_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d17_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d7_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d2_d1 ;
wire _out_a_B ;
output Iout_d_d20_d1 ;
wire Iin_d_d9_d0 ;
output Iout_d_d14_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d15_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d24_d0 ;
wire _in_v ;
wire Iin_d_d25_d0 ;
output Iin_v ;
wire Iin_d_d3_d1 ;
output Iout_d_d25_d0 ;
wire Iin_d_d7_d0 ;
output Iout_d_d27_d1 ;
wire _en ;
wire Iin_d_d14_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d30_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d21_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d_d7_d1 ;
wire Ien_buf_out0 ;
output Iout_d_d6_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d28_d0 ;
wire Iout_a ;
wire Iin_d_d11_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d28_d1 ;
output Iout_d_d26_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d4_d0 ;
wire Iin_d_d2_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d24_d0 ;
output Iin_a ;
wire Iin_d_d13_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d11_d1 ;
wire Iout_v ;
wire Iin_d_d10_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d22_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d22_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d13_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d20_d0 ;
wire _in_v ;
output Iout_d_d26_d1 ;
wire Iin_d_d16_d0 ;
wire _reset_BX ;
wire Iin_d_d7_d0 ;
wire Iin_d_d19_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d7_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d17_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d12_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d13_d1 ;
output Iin_a ;
wire Iin_d_d30_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d22_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d8_d0 ;
wire _out_a_B ;
wire I_out_a_BX0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d23_d1 ;
wire Iout_a ;
wire Iin_d_d2_d0 ;
output Iout_d_d1_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d15_d0 ;
wire Ien_buf_out0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d23_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d_d4_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d24_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d8_d0 ;
output Iout_d_d3_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d16_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d29_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d6_d1 ;
wire reset_B;
output Iout_d_d15_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d29_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d29_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d11_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d17_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d23_d0 ;
output Iin_v ;
wire Iin_d_d14_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d16_d0 ;
wire I_reset_BXX0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d30_d1 ;
output Iout_d_d30_d0 ;
output Iout_d_d22_d1 ;
wire _en ;
wire Iin_d_d18_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d30_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d19_d0 ;
wire Iin_d_d23_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d10_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

260
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/verilog.v

@ -136,146 +136,146 @@ module tmpl_0_0dataflow__neuro_0_0buffer_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
output Iout_d_d23_d0 ;
output Iin_a ;
wire Iin_d_d16_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d3_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d24_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d23_d1 ;
wire reset_B;
output Iout_d_d8_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d21_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d26_d1 ;
output Iout_d_d31_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d30_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d25_d0 ;
wire Iout_v ;
wire Iin_d_d13_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d25_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d31_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d20_d0 ;
wire _in_v ;
output Iout_d_d22_d1 ;
output Iout_d_d27_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d21_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d27_d0 ;
output Iout_d_d11_d1 ;
wire Iin_d_d11_d1 ;
wire _out_a_B ;
output Iout_d_d4_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d8_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d23_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d12_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d28_d0 ;
output Iout_d_d8_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d24_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d_d17_d1 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d9_d0 ;
wire _en ;
wire Iin_d_d3_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d16_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d27_d1 ;
wire Iin_d_d29_d0 ;
output Iout_d_d31_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d13_d0 ;
wire _in_v ;
wire Iin_d_d1_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d9_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d24_d1 ;
wire I_out_a_BX0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d18_d1 ;
output Iout_d_d19_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d12_d1 ;
wire _reset_BX ;
wire Iin_d_d4_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d12_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d20_d1 ;
output Iout_d_d8_d1 ;
wire Iin_d_d27_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d29_d1 ;
wire Iin_d_d9_d0 ;
wire Ien_buf_out0 ;
wire Iin_d_d30_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d21_d0 ;
output Iin_v ;
output Iout_d_d30_d1 ;
output Iout_d_d11_d0 ;
output Iout_d_d2_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d18_d0 ;
output Iout_d_d17_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d26_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d28_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d20_d0 ;
output Iout_d_d20_d1 ;
wire Iin_d_d27_d1 ;
output Iout_d_d20_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d12_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d31_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d7_d0 ;
output Iout_d_d15_d0 ;
wire _out_a_B ;
wire Iin_d_d28_d0 ;
output Iout_d_d15_d1 ;
wire Iin_d_d31_d1 ;
output Iout_d_d4_d1 ;
output Iout_d_d10_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d11_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d1_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d0_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d6_d1 ;
output Iout_d_d22_d1 ;
wire Iin_d_d10_d0 ;
wire Iout_a ;
output Iout_d_d5_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d9_d1 ;
wire Iout_v ;
output Iout_d_d23_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d18_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d0_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d_d30_d0 ;
output Iout_d_d24_d0 ;
wire Iin_d_d1_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d20_d1 ;
wire _reset_BX ;
output Iout_d_d17_d0 ;
output Iout_d_d29_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d13_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d30_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d1_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d25_d0 ;
output Iout_d_d15_d1 ;
wire _en ;
wire Ien_buf_out0 ;
output Iout_d_d5_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d27_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d14_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d28_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d29_d1 ;
output Iin_a ;
wire Iin_d_d10_d0 ;
wire Iin_d_d31_d0 ;
output Iout_d_d14_d1 ;
output Iout_d_d15_d0 ;
output Iin_v ;
wire Iin_d_d5_d0 ;
wire Iin_d_d9_d1 ;
wire Iout_a ;
wire Iin_d_d27_d1 ;
wire Iin_d_d31_d1 ;
output Iout_d_d12_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

64
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/verilog.v

@ -36,46 +36,46 @@ module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
input reset_B;
// -- signals ---
output Iout_d_d1_d0 ;
wire _reset_BX ;
wire Iin_d_d6_d1 ;
wire Iout_v ;
wire Iin_d_d1_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d2_d0 ;
output Iin_a ;
output Iout_d_d5_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d1_d1 ;
wire reset_B;
output Iout_d_d4_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d3_d1 ;
wire _en ;
wire Iin_d_d5_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d4_d0 ;
wire Iin_d_d0_d1 ;
wire I_out_a_BX0 ;
output Iout_d_d0_d1 ;
wire Iout_a ;
wire Ien_buf_out0 ;
output Iin_v ;
output Iout_d_d6_d0 ;
wire Iin_d_d1_d0 ;
wire _en ;
output Iout_d_d3_d1 ;
output Iout_d_d1_d1 ;
wire I_reset_BXX0 ;
wire _in_v ;
output Iout_d_d0_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d4_d1 ;
wire reset_B;
wire Iin_d_d4_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d4_d1 ;
wire Iin_d_d3_d0 ;
wire _in_v ;
wire _reset_BX ;
wire Iin_d_d5_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d5_d0 ;
output Iin_v ;
wire _out_a_B ;
wire Ien_buf_out0 ;
wire Iin_d_d0_d0 ;
wire I_out_a_BX0 ;
wire Iin_d_d6_d0 ;
output Iout_d_d2_d0 ;
output Iin_a ;
output Iout_d_d2_d1 ;
wire Iout_v ;
output Iout_d_d6_d0 ;
output Iout_d_d0_d1 ;
wire Iout_a ;
output Iout_d_d4_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

36
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/verilog.v

@ -17,29 +17,29 @@ module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp20 ;
wire Iin4 ;
wire Iin8 ;
wire Iin7 ;
wire Iin10 ;
wire Iin12 ;
wire Iin1 ;
wire Itmp18 ;
wire Itmp17 ;
wire Iin6 ;
wire Itmp21 ;
wire Iin0 ;
wire Itmp16 ;
wire Iin5 ;
wire Iin9 ;
wire Iin7 ;
wire Iin12 ;
wire Iin10 ;
wire Itmp19 ;
wire Iin8 ;
wire Itmp21 ;
wire Itmp20 ;
wire Iin2 ;
wire Iin1 ;
wire Itmp15 ;
wire Itmp14 ;
wire Iin3 ;
wire out ;
wire Iin4 ;
wire Iin11 ;
wire Itmp18 ;
wire Itmp19 ;
wire Itmp13 ;
wire Itmp15 ;
wire out ;
wire Iin11 ;
wire Iin9 ;
wire Iin6 ;
wire Iin3 ;
wire Itmp14 ;
wire Iin0 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp13 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

78
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/verilog.v

@ -27,48 +27,48 @@ module tmpl_0_0dataflow__neuro_0_0ctree_323_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp31 ;
wire Iin2 ;
wire Itmp33 ;
wire Iin15 ;
wire Iin9 ;
wire Iin3 ;
wire out ;
wire Iin4 ;
wire Itmp25 ;
wire Iin22 ;
wire Iin8 ;
wire Itmp38 ;
wire Iin21 ;
wire Itmp39 ;
wire Itmp28 ;
wire Iin5 ;
wire Itmp34 ;
wire Itmp29 ;
wire Iin7 ;
wire Itmp24 ;
wire Itmp27 ;
wire Iin17 ;
wire Itmp35 ;
wire Iin13 ;
wire Itmp26 ;
wire Itmp40 ;
wire Itmp37 ;
wire Iin6 ;
wire Iin20 ;
wire Iin18 ;
wire Itmp36 ;
wire Itmp30 ;
wire Iin0 ;
wire Iin16 ;
wire Iin11 ;
wire Itmp23 ;
wire Iin1 ;
wire Iin19 ;
wire Iin12 ;
wire Iin7 ;
wire Itmp37 ;
wire Itmp34 ;
wire Iin0 ;
wire Itmp40 ;
wire Iin21 ;
wire Iin19 ;
wire Iin22 ;
wire Itmp35 ;
wire Itmp32 ;
wire Iin10 ;
wire Itmp31 ;
wire Iin14 ;
wire Iin8 ;
wire Itmp28 ;
wire Iin17 ;
wire Itmp29 ;
wire Iin4 ;
wire Iin9 ;
wire Iin10 ;
wire Iin16 ;
wire out ;
wire Iin20 ;
wire Itmp26 ;
wire Itmp25 ;
wire Iin3 ;
wire Itmp33 ;
wire Itmp36 ;
wire Iin5 ;
wire Iin13 ;
wire Itmp38 ;
wire Itmp39 ;
wire Iin18 ;
wire Itmp23 ;
wire Itmp24 ;
wire Itmp30 ;
wire Iin15 ;
wire Itmp27 ;
wire Iin1 ;
wire Iin11 ;
wire Iin2 ;
wire Iin6 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp23 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

94
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/verilog.v

@ -33,60 +33,60 @@ module tmpl_0_0dataflow__neuro_0_0ctree_329_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp48 ;
wire Itmp51 ;
wire Iin13 ;
wire Itmp52 ;
wire Itmp42 ;
wire Iin23 ;
wire Itmp34 ;
wire Itmp50 ;
wire Iin17 ;
wire Iin11 ;
wire Iin5 ;
wire out ;
wire Itmp29 ;
wire Itmp45 ;
wire Iin16 ;
wire Iin9 ;
wire Itmp39 ;
wire Iin10 ;
wire Iin21 ;
wire Iin15 ;
wire Iin2 ;
wire Iin14 ;
wire Iin26 ;
wire Iin6 ;
wire Itmp43 ;
wire Itmp40 ;
wire Itmp36 ;
wire Itmp46 ;
wire Iin4 ;
wire Itmp47 ;
wire Itmp44 ;
wire Iin25 ;
wire Iin8 ;
wire Itmp32 ;
wire Iin1 ;
wire Iin7 ;
wire Iin28 ;
wire Iin19 ;
wire Iin24 ;
wire Itmp49 ;
wire Itmp38 ;
wire Itmp31 ;
wire Iin18 ;
wire Itmp33 ;
wire Iin27 ;
wire Itmp37 ;
wire Iin12 ;
wire Iin28 ;
wire Itmp50 ;
wire out ;
wire Itmp52 ;
wire Itmp39 ;
wire Itmp47 ;
wire Iin4 ;
wire Iin3 ;
wire Iin14 ;
wire Iin11 ;
wire Itmp33 ;
wire Iin26 ;
wire Itmp31 ;
wire Iin13 ;
wire Iin21 ;
wire Iin9 ;
wire Iin15 ;
wire Itmp38 ;
wire Iin12 ;
wire Iin25 ;
wire Iin24 ;
wire Iin22 ;
wire Itmp44 ;
wire Itmp35 ;
wire Itmp41 ;
wire Iin20 ;
wire Itmp30 ;
wire Iin10 ;
wire Itmp29 ;
wire Itmp51 ;
wire Iin5 ;
wire Iin0 ;
wire Itmp42 ;
wire Iin16 ;
wire Itmp34 ;
wire Itmp49 ;
wire Itmp45 ;
wire Itmp41 ;
wire Itmp37 ;
wire Itmp36 ;
wire Iin1 ;
wire Iin27 ;
wire Iin17 ;
wire Itmp43 ;
wire Iin20 ;
wire Iin7 ;
wire Iin8 ;
wire Iin6 ;
wire Itmp48 ;
wire Iin2 ;
wire Itmp30 ;
wire Itmp32 ;
wire Iin23 ;
wire Itmp40 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp29 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

102
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/verilog.v

@ -34,62 +34,62 @@ module tmpl_0_0dataflow__neuro_0_0ctree_330_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin4 ;
wire Itmp48 ;
wire Iin14 ;
wire Itmp39 ;
wire Itmp36 ;
wire Itmp35 ;
wire Iin6 ;
wire Iin26 ;
wire Iin25 ;
wire Iin19 ;
wire Iin12 ;
wire Iin11 ;
wire Iin5 ;
wire Itmp50 ;
wire Itmp51 ;
wire Itmp49 ;
wire Iin8 ;
wire Itmp54 ;
wire Itmp32 ;
wire Itmp52 ;
wire Itmp46 ;
wire Itmp44 ;
wire Itmp43 ;
wire Iin24 ;
wire Iin20 ;
wire Iin16 ;
wire Iin1 ;
wire out ;
wire Iin28 ;
wire Iin23 ;
wire Iin7 ;
wire Itmp33 ;
wire Iin29 ;
wire Itmp53 ;
wire Iin17 ;
wire Itmp37 ;
wire Iin0 ;
wire Iin21 ;
wire Iin18 ;
wire Iin15 ;
wire Iin10 ;
wire Itmp45 ;
wire Iin2 ;
wire Iin13 ;
wire Iin9 ;
wire Iin3 ;
wire Itmp40 ;
wire Iin27 ;
wire Itmp41 ;
wire Itmp39 ;
wire Itmp30 ;
wire Itmp47 ;
wire Itmp49 ;
wire Iin3 ;
wire Iin26 ;
wire Iin1 ;
wire Itmp51 ;
wire Iin21 ;
wire Iin12 ;
wire Iin28 ;
wire Iin19 ;
wire Itmp44 ;
wire Iin4 ;
wire Itmp52 ;
wire Iin22 ;
wire Iin10 ;
wire Itmp50 ;
wire Itmp54 ;
wire out ;
wire Iin14 ;
wire Iin27 ;
wire Itmp32 ;
wire Iin0 ;
wire Itmp53 ;
wire Itmp46 ;
wire Iin29 ;
wire Itmp43 ;
wire Iin7 ;
wire Itmp35 ;
wire Iin8 ;
wire Iin6 ;
wire Itmp45 ;
wire Iin20 ;
wire Iin17 ;
wire Iin16 ;
wire Itmp34 ;
wire Itmp40 ;
wire Iin18 ;
wire Itmp31 ;
wire Iin9 ;
wire Iin5 ;
wire Itmp48 ;
wire Iin23 ;
wire Itmp41 ;
wire Itmp37 ;
wire Iin2 ;
wire Iin24 ;
wire Itmp42 ;
wire Itmp38 ;
wire Itmp34 ;
wire Itmp31 ;
wire Iin22 ;
wire Iin15 ;
wire Itmp36 ;
wire Itmp47 ;
wire Iin25 ;
wire Iin13 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp30 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

102
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/verilog.v

@ -35,63 +35,63 @@ module tmpl_0_0dataflow__neuro_0_0ctree_331_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp52 ;
wire Itmp49 ;
wire Iin18 ;
wire Iin8 ;
wire Itmp35 ;
wire Iin1 ;
wire Itmp45 ;
wire Itmp48 ;
wire Iin22 ;
wire Iin27 ;
wire Itmp42 ;
wire Itmp41 ;
wire out ;
wire Iin16 ;
wire Iin19 ;
wire Iin12 ;
wire Itmp33 ;
wire Itmp47 ;
wire Iin7 ;
wire Itmp54 ;
wire Iin26 ;
wire Iin5 ;
wire Iin10 ;
wire Itmp50 ;
wire Iin22 ;
wire Iin28 ;
wire Itmp44 ;
wire Itmp32 ;
wire Iin20 ;
wire Iin17 ;
wire Iin23 ;
wire Itmp36 ;
wire Iin3 ;
wire Itmp42 ;
wire Itmp53 ;
wire Itmp44 ;
wire Itmp46 ;
wire Itmp34 ;
wire Itmp43 ;
wire Iin11 ;
wire Iin4 ;
wire Itmp31 ;
wire Itmp40 ;
wire Itmp39 ;
wire Iin27 ;
wire Iin17 ;
wire Iin0 ;
wire Iin20 ;
wire Itmp38 ;
wire Itmp51 ;
wire Itmp55 ;
wire Iin28 ;
wire Itmp41 ;
wire Iin9 ;
wire Iin30 ;
wire Iin24 ;
wire Iin14 ;
wire Iin25 ;
wire Iin21 ;
wire Itmp37 ;
wire Itmp47 ;
wire Iin2 ;
wire Iin15 ;
wire Iin1 ;
wire Itmp52 ;
wire Itmp51 ;
wire Itmp33 ;
wire Itmp43 ;
wire Iin30 ;
wire Iin19 ;
wire Iin12 ;
wire Iin0 ;
wire Itmp31 ;
wire Itmp39 ;
wire Iin24 ;
wire Iin18 ;
wire Itmp35 ;
wire Iin21 ;
wire Iin8 ;
wire Iin7 ;
wire Iin25 ;
wire Iin6 ;
wire Itmp32 ;
wire Iin29 ;
wire Iin15 ;
wire Iin13 ;
wire Iin11 ;
wire Iin9 ;
wire Iin4 ;
wire Itmp46 ;
wire Iin26 ;
wire Itmp40 ;
wire Iin10 ;
wire Iin5 ;
wire Itmp34 ;
wire Itmp55 ;
wire Iin29 ;
wire Itmp54 ;
wire Itmp50 ;
wire Itmp49 ;
wire Itmp37 ;
wire Itmp45 ;
wire Iin3 ;
wire Iin16 ;
wire Itmp48 ;
wire Itmp53 ;
wire Iin14 ;
wire Itmp38 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp31 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

108
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/verilog.v

@ -36,68 +36,68 @@ module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Itmp56 ;
wire Iin4 ;
wire Iin24 ;
wire Iin21 ;
wire Itmp41 ;
wire Iin2 ;
wire Itmp45 ;
wire Itmp60 ;
wire Iin23 ;
wire Iin22 ;
wire Iin15 ;
wire Itmp53 ;
wire Itmp50 ;
wire Iin29 ;
wire Iin23 ;
wire Iin16 ;
wire Iin28 ;
wire Iin27 ;
wire Itmp38 ;
wire Iin9 ;
wire Iin21 ;
wire Iin6 ;
wire Iin4 ;
wire Itmp56 ;
wire Itmp52 ;
wire Iin30 ;
wire Iin29 ;
wire Itmp42 ;
wire Iin19 ;
wire Iin11 ;
wire Iin5 ;
wire Itmp35 ;
wire Itmp44 ;
wire Iin8 ;
wire Iin24 ;
wire Iin31 ;
wire Itmp39 ;
wire Iin18 ;
wire Itmp36 ;
wire Iin20 ;
wire Iin13 ;
wire Iin12 ;
wire Iin10 ;
wire Itmp37 ;
wire Iin1 ;
wire Itmp57 ;
wire Iin9 ;
wire out ;
wire Itmp47 ;
wire Iin17 ;
wire Itmp51 ;
wire Iin25 ;
wire Itmp61 ;
wire Itmp54 ;
wire Itmp52 ;
wire Iin25 ;
wire Iin1 ;
wire Itmp36 ;
wire Iin13 ;
wire Iin11 ;
wire Itmp37 ;
wire Itmp49 ;
wire Iin8 ;
wire Itmp34 ;
wire Iin6 ;
wire Itmp43 ;
wire Iin12 ;
wire Iin15 ;
wire Iin7 ;
wire Itmp59 ;
wire Itmp55 ;
wire Iin19 ;
wire Itmp53 ;
wire Iin20 ;
wire Itmp48 ;
wire Iin14 ;
wire Itmp33 ;
wire out ;
wire Itmp42 ;
wire Iin18 ;
wire Iin3 ;
wire Iin31 ;
wire Iin17 ;
wire Iin0 ;
wire Iin30 ;
wire Itmp46 ;
wire Iin5 ;
wire Itmp51 ;
wire Itmp44 ;
wire Iin10 ;
wire Itmp58 ;
wire Itmp40 ;
wire Itmp57 ;
wire Iin16 ;
wire Iin27 ;
wire Itmp41 ;
wire Itmp43 ;
wire Itmp49 ;
wire Iin26 ;
wire Itmp39 ;
wire Itmp45 ;
wire Itmp40 ;
wire Iin14 ;
wire Iin2 ;
wire Itmp33 ;
wire Itmp55 ;
wire Itmp46 ;
wire Iin3 ;
wire Iin22 ;
wire Iin0 ;
wire Itmp48 ;
wire Itmp58 ;
wire Itmp38 ;
wire Itmp34 ;
wire Itmp59 ;
wire Itmp60 ;
wire Itmp32 ;
// --- instances

8
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_34_4/netlist/verilog.v

@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0ctree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vd
output out;
// -- signals ---
wire Itmp5 ;
wire Iin1 ;
wire Itmp4 ;
wire Iin1 ;
wire out ;
wire Iin3 ;
wire Iin2 ;
wire Iin0 ;
wire Iin2 ;
wire Iin3 ;
wire Itmp5 ;
// --- instances
A_2C_B_X1 IC2Els0 (.y(Itmp4 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

10
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_37_4/netlist/verilog.v

@ -12,15 +12,15 @@ module tmpl_0_0dataflow__neuro_0_0ctree_37_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
// -- signals ---
wire Iin4 ;
wire out ;
wire Iin5 ;
wire Iin3 ;
wire Iin2 ;
wire Itmp9 ;
wire Iin5 ;
wire Iin1 ;
wire Iin3 ;
wire Itmp8 ;
wire Iin6 ;
wire Iin0 ;
wire Iin2 ;
wire Itmp8 ;
wire out ;
wire Itmp7 ;
// --- instances

22
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_39_4/netlist/verilog.v

@ -13,21 +13,21 @@ module tmpl_0_0dataflow__neuro_0_0ctree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin1 ;
wire Itmp10 ;
wire Itmp9 ;
wire Iin6 ;
wire Iin3 ;
wire Iin7 ;
wire Itmp13 ;
wire Iin4 ;
wire out ;
wire Iin0 ;
wire Itmp12 ;
wire Itmp14 ;
wire Iin5 ;
wire Itmp9 ;
wire Iin0 ;
wire Iin3 ;
wire Itmp14 ;
wire out ;
wire Iin4 ;
wire Iin6 ;
wire Iin7 ;
wire Iin1 ;
wire Iin8 ;
wire Itmp10 ;
wire Itmp11 ;
wire Itmp13 ;
wire Iin2 ;
// --- instances

1757
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

21602
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__2d__synapse__hs_315_7348_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

168
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4/netlist/verilog.v

@ -79,94 +79,94 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4(Iin_d0_d0 , Iin_d0_
// -- signals ---
wire Iin_d1_d0 ;
output Iout46 ;
output Iout24 ;
output Iout54 ;
output Iout52 ;
wire Iatree61_in1 ;
output Iout37 ;
wire Iin_d5_d0 ;
wire Iin_d0_d0 ;
output Iout15 ;
output Iout3 ;
output Iout14 ;
wire Iin_d3_d0 ;
output Iout43 ;
output Iout42 ;
output Iout33 ;
output Iout29 ;
wire Iatree47_in4 ;
wire Iin_d0_d1 ;
output Iout48 ;
output Iout18 ;
output Iout4 ;
wire Iatree63_in5 ;
output Iout25 ;
output Iout60 ;
output Iout31 ;
output Iout17 ;
output Iout58 ;
output Iout27 ;
output Iout56 ;
output Iout22 ;
output Iout51 ;
output Iout13 ;
wire Iatree63_in3 ;
output Iout55 ;
wire Iin_d4_d0 ;
output Iout63 ;
output Iout62 ;
output Iout32 ;
output Iout28 ;
wire Iin_d2_d1 ;
wire Iin_d1_d1 ;
output Iout39 ;
wire Iatree55_in3 ;
wire Iatree59_in2 ;
output Iout35 ;
wire Iatree63_in4 ;
output Iout5 ;
output Iout2 ;
wire Iin_d2_d0 ;
output Iout21 ;
wire Iin_d5_d1 ;
output Iout34 ;
output Iout7 ;
wire Iatree62_in0 ;
output Iout59 ;
output Iout47 ;
output Iout26 ;
output Iout0 ;
output Iout61 ;
output Iout16 ;
wire Iin_d3_d1 ;
output Iout49 ;
output Iout11 ;
output Iout9 ;
output Iout6 ;
output Iout1 ;
wire Iin_d4_d1 ;
output Iout19 ;
output Iout10 ;
output Iout8 ;
output Iout40 ;
output Iout30 ;
output Iout20 ;
output Iout12 ;
wire Iatree63_in1 ;
output Iout45 ;
wire Iatree63_in2 ;
output Iout50 ;
output Iout44 ;
output Iout23 ;
output Iout53 ;
output Iout36 ;
wire Iatree31_in5 ;
output Iout6 ;
output Iout5 ;
output Iout49 ;
output Iout29 ;
output Iout26 ;
output Iout19 ;
output Iout48 ;
output Iout37 ;
output Iout57 ;
output Iout41 ;
output Iout38 ;
output Iout21 ;
output Iout4 ;
output Iout20 ;
output Iout9 ;
wire Iatree62_in0 ;
wire Iin_d4_d0 ;
output Iout45 ;
output Iout39 ;
wire Iatree63_in2 ;
output Iout17 ;
wire Iatree63_in3 ;
output Iout60 ;
output Iout51 ;
output Iout11 ;
output Iout62 ;
output Iout46 ;
output Iout40 ;
output Iout33 ;
output Iout16 ;
output Iout1 ;
wire Iin_d0_d0 ;
output Iout63 ;
output Iout27 ;
output Iout14 ;
output Iout2 ;
wire Iatree63_in0 ;
output Iout47 ;
wire Iatree63_in5 ;
output Iout0 ;
output Iout53 ;
output Iout31 ;
output Iout12 ;
output Iout8 ;
output Iout52 ;
output Iout50 ;
output Iout43 ;
output Iout25 ;
output Iout7 ;
wire Iin_d0_d1 ;
wire Iatree63_in1 ;
wire Iatree47_in4 ;
wire Iin_d4_d1 ;
output Iout38 ;
wire Iatree59_in2 ;
output Iout55 ;
output Iout30 ;
output Iout13 ;
output Iout10 ;
output Iout54 ;
output Iout34 ;
output Iout23 ;
output Iout18 ;
wire Iatree63_in4 ;
wire Iin_d2_d1 ;
output Iout35 ;
output Iout61 ;
output Iout28 ;
wire Iin_d5_d0 ;
wire Iin_d1_d0 ;
wire Iin_d3_d1 ;
wire Iin_d1_d1 ;
output Iout42 ;
wire Iatree55_in3 ;
wire Iin_d2_d0 ;
output Iout58 ;
output Iout44 ;
output Iout56 ;
output Iout41 ;
output Iout32 ;
output Iout24 ;
wire Iatree61_in1 ;
wire Iin_d5_d1 ;
output Iout59 ;
output Iout36 ;
wire Iin_d3_d0 ;
output Iout22 ;
output Iout3 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

42
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist/verilog.v

@ -16,32 +16,32 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4(Iin_d0_d0 , Iin_
// -- signals ---
wire Isb_en_out0 ;
wire Ien_ands_f0_y ;
output Iout4 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout1 ;
wire Ien_ands_f2_y ;
wire Iin_d1_d0 ;
wire Idecoder_final_refresh_d2_d0 ;
wire Ien_ands_t0_y ;
wire Idecoder_final_refresh_d1_d0 ;
wire en;
wire Idecoder_final_refresh_d1_d1 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Ien_ands_f1_y ;
wire Iin_d1_d1 ;
output Iout0 ;
output Iout5 ;
output Iout3 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout2 ;
wire Ien_ands_t1_y ;
wire Iin_d2_d0 ;
wire Iin_d0_d0 ;
wire Idecoder_final_refresh_d1_d1 ;
wire Isb_en_out0 ;
output Iout2 ;
wire Ien_ands_t2_y ;
wire Iin_d2_d1 ;
wire Ien_ands_f0_y ;
wire Idecoder_final_refresh_d0_d0 ;
wire Ien_ands_t1_y ;
wire Iin_d0_d0 ;
wire Ien_ands_f2_y ;
wire Idecoder_final_refresh_d2_d0 ;
output Iout4 ;
wire Iin_d1_d0 ;
output Iout3 ;
wire Iin_d1_d1 ;
wire Idecoder_final_refresh_d1_d0 ;
wire Idecoder_final_refresh_d0_d1 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Iin_d0_d1 ;
wire Ien_ands_t0_y ;
wire Iin_d2_d1 ;
output Iout5 ;
output Iout0 ;
output Iout1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .vdd(vdd), .vss(vss));

112
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist/verilog.v

@ -44,68 +44,68 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4(Iin_d0_d0 , Iin
// -- signals ---
output Iout5 ;
wire Iin_d0_d0 ;
output Iout16 ;
output Iout2 ;
wire Ien_ands_t3_y ;
output Iout17 ;
wire Ien_ands_f4_y ;
output Iout29 ;
output Iout25 ;
wire Iin_d4_d0 ;
wire Idecoder_final_refresh_d4_d1 ;
output Iout9 ;
wire Idecoder_final_refresh_d2_d0 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Iin_d3_d0 ;
wire Iin_d2_d0 ;
wire Iin_d1_d0 ;
output Iout7 ;
wire Iin_d0_d1 ;
wire Idecoder_final_refresh_d3_d0 ;
wire Idecoder_final_refresh_d4_d0 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout10 ;
wire Ien_ands_t1_y ;
output Iout19 ;
output Iout3 ;
wire Iin_d4_d1 ;
wire Iin_d3_d1 ;
wire Idecoder_final_refresh_d3_d1 ;
output Iout11 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout23 ;
output Iout21 ;
wire Idecoder_final_refresh_d1_d0 ;
wire Ien_ands_t2_y ;
wire Ien_ands_f0_y ;
wire Iin_d1_d1 ;
output Iout22 ;
wire Isb_en_out0 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout28 ;
wire Ien_ands_f3_y ;
wire Iin_d2_d1 ;
wire Ien_ands_f4_y ;
wire Ien_ands_f0_y ;
wire Idecoder_final_refresh_d3_d0 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout25 ;
output Iout16 ;
wire Ien_ands_t0_y ;
output Iout29 ;
output Iout12 ;
wire Iin_d4_d0 ;
wire Iin_d3_d0 ;
output Iout28 ;
output Iout11 ;
output Iout5 ;
wire Iin_d4_d1 ;
output Iout24 ;
output Iout2 ;
wire Iin_d0_d0 ;
output Iout8 ;
wire Ien_ands_t4_y ;
wire Ien_ands_t3_y ;
output Iout26 ;
wire en;
output Iout10 ;
wire Iin_d0_d1 ;
wire Idecoder_final_refresh_d4_d1 ;
wire Iin_d1_d1 ;
output Iout13 ;
output Iout22 ;
output Iout9 ;
wire Ien_ands_t1_y ;
output Iout20 ;
output Iout7 ;
output Iout27 ;
output Iout14 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout23 ;
output Iout18 ;
output Iout1 ;
output Iout0 ;
output Iout24 ;
output Iout4 ;
output Iout27 ;
output Iout20 ;
wire Ien_ands_f1_y ;
output Iout13 ;
wire Ien_ands_t4_y ;
wire Ien_ands_f2_y ;
wire en;
output Iout8 ;
output Iout14 ;
output Iout15 ;
wire Idecoder_final_refresh_d2_d1 ;
wire Idecoder_final_refresh_d2_d0 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout19 ;
output Iout0 ;
output Iout6 ;
wire Ien_ands_t0_y ;
output Iout26 ;
output Iout15 ;
wire Iin_d1_d0 ;
wire Idecoder_final_refresh_d3_d1 ;
output Iout21 ;
wire Ien_ands_t2_y ;
wire Iin_d2_d0 ;
output Iout17 ;
wire Ien_ands_f2_y ;
wire Iin_d3_d1 ;
wire Iin_d2_d1 ;
wire Idecoder_final_refresh_d1_d0 ;
output Iout4 ;
wire Idecoder_final_refresh_d4_d0 ;
output Iout3 ;
wire Ien_ands_f3_y ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .vdd(vdd), .vss(vss));

178
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4/netlist/verilog.v

@ -76,104 +76,104 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4(Iin_d0_d0 , Iin
// -- signals ---
wire Isb_en_out0 ;
output Iout4 ;
wire Iin_d3_d0 ;
output Iout41 ;
output Iout25 ;
wire Iin_d2_d1 ;
output Iout44 ;
wire Ien_ands_t3_y ;
wire Iin_d4_d0 ;
wire Iin_d1_d0 ;
wire Idecoder_final_refresh_d5_d1 ;
wire Idecoder_final_refresh_d4_d1 ;
output Iout32 ;
output Iout21 ;
wire Ien_ands_f2_y ;
output Iout53 ;
output Iout43 ;
output Iout38 ;
wire Ien_ands_f1_y ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout40 ;
output Iout31 ;
output Iout6 ;
wire Iin_d4_d1 ;
output Iout33 ;
wire Iin_d5_d0 ;
wire Idecoder_final_refresh_d2_d1 ;
output Iout34 ;
output Iout10 ;
output Iout5 ;
wire Iin_d5_d1 ;
output Iout36 ;
output Iout23 ;
output Iout13 ;
wire Idecoder_final_refresh_d3_d0 ;
wire Idecoder_final_refresh_d2_d0 ;
wire en;
wire Idecoder_final_refresh_d1_d1 ;
output Iout56 ;
output Iout51 ;
output Iout30 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout59 ;
output Iout47 ;
output Iout22 ;
output Iout20 ;
output Iout16 ;
output Iout15 ;
output Iout12 ;
output Iout54 ;
output Iout49 ;
wire Idecoder_final_refresh_d5_d0 ;
wire Idecoder_final_refresh_d4_d0 ;
output Iout58 ;
wire Ien_ands_t2_y ;
output Iout17 ;
wire Iin_d5_d1 ;
wire en;
wire Idecoder_final_refresh_d4_d1 ;
output Iout0 ;
wire Ien_ands_f3_y ;
output Iout51 ;
wire Ien_ands_f2_y ;
output Iout39 ;
output Iout9 ;
output Iout2 ;
wire Ien_ands_f5_y ;
wire Ien_ands_t1_y ;
output Iout45 ;
wire Iin_d0_d0 ;
output Iout55 ;
output Iout28 ;
output Iout26 ;
output Iout1 ;
output Iout0 ;
wire Idecoder_final_refresh_d1_d0 ;
output Iout24 ;
output Iout47 ;
output Iout21 ;
wire Idecoder_final_refresh_d5_d0 ;
wire Idecoder_final_refresh_d4_d0 ;
output Iout35 ;
wire Iin_d4_d1 ;
wire Iin_d2_d1 ;
wire Ien_ands_t5_y ;
wire Idecoder_final_refresh_d2_d1 ;
output Iout55 ;
output Iout43 ;
output Iout42 ;
wire Iin_d3_d1 ;
output Iout23 ;
output Iout12 ;
output Iout8 ;
output Iout54 ;
output Iout48 ;
output Iout1 ;
output Iout37 ;
output Iout31 ;
wire Ien_ands_t4_y ;
wire Iin_d0_d1 ;
output Iout56 ;
output Iout25 ;
output Iout59 ;
output Iout44 ;
output Iout33 ;
output Iout27 ;
wire Idecoder_final_refresh_d3_d1 ;
output Iout52 ;
output Iout18 ;
wire Ien_ands_f0_y ;
wire Iin_d4_d0 ;
wire Idecoder_final_refresh_d0_d1 ;
output Iout15 ;
wire Ien_ands_t3_y ;
wire Ien_ands_t2_y ;
wire Iin_d5_d0 ;
output Iout58 ;
output Iout57 ;
wire Ien_ands_f4_y ;
output Iout32 ;
wire Idecoder_final_refresh_d1_d0 ;
wire Isb_en_out0 ;
wire Iin_d0_d0 ;
wire Idecoder_final_refresh_d2_d0 ;
output Iout17 ;
output Iout13 ;
output Iout4 ;
wire Iin_d3_d0 ;
output Iout53 ;
output Iout50 ;
output Iout19 ;
output Iout3 ;
wire Idecoder_final_refresh_d5_d1 ;
output Iout29 ;
output Iout28 ;
output Iout7 ;
output Iout5 ;
wire Ien_ands_f1_y ;
wire Iin_d1_d0 ;
wire Iin_d1_d1 ;
wire Idecoder_final_refresh_d1_d1 ;
output Iout49 ;
output Iout40 ;
output Iout30 ;
output Iout10 ;
output Iout6 ;
output Iout46 ;
output Iout36 ;
output Iout26 ;
wire Ien_ands_t0_y ;
output Iout34 ;
wire Iin_d2_d0 ;
wire Idecoder_final_refresh_d0_d0 ;
output Iout41 ;
wire Idecoder_final_refresh_d3_d0 ;
output Iout14 ;
output Iout11 ;
wire Ien_ands_f0_y ;
wire Iin_d2_d0 ;
output Iout18 ;
wire Ien_ands_f5_y ;
wire Iin_d0_d1 ;
output Iout48 ;
output Iout8 ;
output Iout39 ;
output Iout46 ;
output Iout42 ;
output Iout7 ;
output Iout3 ;
output Iout27 ;
output Iout22 ;
output Iout2 ;
wire Ien_ands_f4_y ;
wire Ien_ands_t0_y ;
wire Ien_ands_f3_y ;
wire Idecoder_final_refresh_d3_d1 ;
output Iout57 ;
output Iout52 ;
output Iout50 ;
output Iout37 ;
output Iout35 ;
output Iout19 ;
output Iout9 ;
wire Iin_d3_d1 ;
wire Ien_ands_t4_y ;
output Iout20 ;
wire Ien_ands_t5_y ;
// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iin_d5_d0 (Ien_ands_f5_y ), .Iin_d5_d1 (Ien_ands_t5_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Iout30 (Iout30 ), .Iout31 (Iout31 ), .Iout32 (Iout32 ), .Iout33 (Iout33 ), .Iout34 (Iout34 ), .Iout35 (Iout35 ), .Iout36 (Iout36 ), .Iout37 (Iout37 ), .Iout38 (Iout38 ), .Iout39 (Iout39 ), .Iout40 (Iout40 ), .Iout41 (Iout41 ), .Iout42 (Iout42 ), .Iout43 (Iout43 ), .Iout44 (Iout44 ), .Iout45 (Iout45 ), .Iout46 (Iout46 ), .Iout47 (Iout47 ), .Iout48 (Iout48 ), .Iout49 (Iout49 ), .Iout50 (Iout50 ), .Iout51 (Iout51 ), .Iout52 (Iout52 ), .Iout53 (Iout53 ), .Iout54 (Iout54 ), .Iout55 (Iout55 ), .Iout56 (Iout56 ), .Iout57 (Iout57 ), .Iout58 (Iout58 ), .Iout59 (Iout59 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .Ifinal_refresh_d5_d0 (Idecoder_final_refresh_d5_d0 ), .Ifinal_refresh_d5_d1 (Idecoder_final_refresh_d5_d1 ), .vdd(vdd), .vss(vss));

798
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_39_7348_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

24
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4/netlist/verilog.v

@ -21,24 +21,24 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4(Iin_d0_d0 ,
// -- signals ---
output Iout3 ;
output Iout5 ;
wire Iin_d0_d1 ;
output Iout0 ;
output Ifinal_refresh_d2_d0 ;
output Iout4 ;
output Iout1 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d2_d0 ;
output Ifinal_refresh_d2_d1 ;
output Ifinal_refresh_d1_d0 ;
wire Iin_d1_d1 ;
wire Iin_d0_d0 ;
output Iout1 ;
output Ifinal_refresh_d0_d0 ;
output Iout5 ;
output Ifinal_refresh_d0_d1 ;
output Iout2 ;
wire Iin_d2_d1 ;
output Ifinal_refresh_d1_d1 ;
output Ifinal_refresh_d2_d0 ;
output Iout0 ;
wire Iin_d2_d0 ;
output Ifinal_refresh_d2_d1 ;
output Iout3 ;
output Ifinal_refresh_d1_d0 ;
wire Iin_d1_d0 ;
wire Iin_d1_d1 ;
wire Iin_d2_d1 ;
wire Iin_d0_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

44
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4/netlist/verilog.v

@ -34,37 +34,37 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4(Iin_d0_d0
// -- signals ---
wire Iin_d2_d1 ;
output Iout2 ;
output Iout12 ;
output Iout9 ;
wire Iin_d3_d1 ;
output Iout5 ;
output Iout4 ;
wire Iin_d3_d0 ;
output Ifinal_refresh_d3_d1 ;
output Iout1 ;
wire Iin_d1_d1 ;
output Ifinal_refresh_d0_d0 ;
output Iout10 ;
output Ifinal_refresh_d2_d0 ;
output Iout6 ;
output Iout13 ;
output Iout4 ;
output Iout7 ;
output Iout5 ;
wire Iin_d1_d0 ;
output Iout8 ;
output Ifinal_refresh_d0_d0 ;
output Ifinal_refresh_d2_d1 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d0_d0 ;
output Ifinal_refresh_d0_d1 ;
output Iout14 ;
output Iout12 ;
output Iout11 ;
wire Iin_d0_d1 ;
output Ifinal_refresh_d3_d0 ;
output Ifinal_refresh_d2_d0 ;
wire Iin_d3_d1 ;
output Ifinal_refresh_d3_d1 ;
output Iout6 ;
wire Iin_d2_d1 ;
output Iout0 ;
output Ifinal_refresh_d1_d0 ;
output Iout8 ;
wire Iin_d3_d0 ;
wire Iin_d2_d0 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d1_d0 ;
output Ifinal_refresh_d3_d0 ;
wire Iin_d0_d1 ;
output Iout3 ;
output Iout2 ;
output Iout13 ;
output Iout9 ;
output Iout1 ;
wire Iin_d1_d1 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d0_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

84
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4/netlist/verilog.v

@ -53,56 +53,56 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4(Iin_d0_d0
// -- signals ---
output Iout25 ;
output Iout12 ;
output Iout20 ;
output Iout3 ;
output Ifinal_refresh_d4_d1 ;
output Iout10 ;
wire Iin_d4_d1 ;
wire Iin_d3_d0 ;
output Iout22 ;
output Iout19 ;
output Iout24 ;
wire Iin_d3_d1 ;
output Iout18 ;
wire Iin_d1_d1 ;
output Iout2 ;
output Iout27 ;
output Iout5 ;
output Iout1 ;
output Ifinal_refresh_d4_d0 ;
output Iout28 ;
output Iout13 ;
output Iout9 ;
wire Iin_d1_d0 ;
output Iout14 ;
output Ifinal_refresh_d0_d1 ;
output Iout29 ;
output Iout11 ;
wire Iin_d2_d1 ;
output Ifinal_refresh_d1_d1 ;
output Iout17 ;
output Iout9 ;
output Iout6 ;
wire Iin_d4_d0 ;
output Iout7 ;
output Iout22 ;
output Iout17 ;
output Ifinal_refresh_d4_d1 ;
output Iout15 ;
output Ifinal_refresh_d2_d1 ;
output Ifinal_refresh_d3_d0 ;
wire Iin_d0_d0 ;
output Iout23 ;
output Ifinal_refresh_d0_d0 ;
wire Iin_d2_d0 ;
output Iout15 ;
output Iout8 ;
output Ifinal_refresh_d1_d0 ;
wire Iin_d4_d1 ;
output Iout21 ;
output Iout4 ;
output Iout16 ;
output Ifinal_refresh_d2_d0 ;
wire Iin_d1_d1 ;
output Iout25 ;
output Iout3 ;
wire Iin_d0_d1 ;
output Iout26 ;
output Iout14 ;
output Iout23 ;
output Ifinal_refresh_d3_d1 ;
output Iout2 ;
wire Iin_d4_d0 ;
output Iout29 ;
output Iout7 ;
output Iout4 ;
wire Iin_d2_d0 ;
output Iout28 ;
output Iout26 ;
output Iout13 ;
output Iout11 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d0_d0 ;
output Iout0 ;
output Ifinal_refresh_d1_d0 ;
output Iout20 ;
output Iout1 ;
output Iout24 ;
output Ifinal_refresh_d2_d0 ;
output Ifinal_refresh_d0_d0 ;
wire Iin_d3_d1 ;
output Iout21 ;
output Iout8 ;
wire Iin_d1_d0 ;
output Iout19 ;
output Iout16 ;
output Iout27 ;
output Ifinal_refresh_d0_d1 ;
output Iout18 ;
output Iout12 ;
output Iout10 ;
output Iout5 ;
output Ifinal_refresh_d4_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

150
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4/netlist/verilog.v

@ -87,90 +87,90 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4(Iin_d0_d0
// -- signals ---
output Iout58 ;
output Iout45 ;
wire Iin_d5_d1 ;
output Iout38 ;
output Iout4 ;
output Iout31 ;
output Ifinal_refresh_d3_d1 ;
output Iout57 ;
output Iout18 ;
output Iout6 ;
output Iout5 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d2_d1 ;
output Iout34 ;
wire Iin_d2_d0 ;
output Iout59 ;
output Iout8 ;
output Iout30 ;
output Iout27 ;
output Ifinal_refresh_d2_d0 ;
wire Iin_d4_d0 ;
output Iout55 ;
output Iout20 ;
output Iout15 ;
output Iout1 ;
output Ifinal_refresh_d5_d0 ;
wire Iin_d1_d1 ;
output Iout52 ;
output Iout24 ;
output Iout11 ;
output Ifinal_refresh_d4_d0 ;
output Iout56 ;
output Iout7 ;
output Iout37 ;
output Iout30 ;
output Iout2 ;
output Iout59 ;
output Iout36 ;
output Iout14 ;
output Ifinal_refresh_d3_d0 ;
output Iout55 ;
output Iout35 ;
output Iout5 ;
output Ifinal_refresh_d2_d1 ;
wire Iin_d1_d0 ;
wire Iin_d3_d1 ;
output Ifinal_refresh_d1_d0 ;
output Iout29 ;
output Iout57 ;
output Iout27 ;
output Iout13 ;
output Iout4 ;
output Ifinal_refresh_d5_d0 ;
wire Iin_d4_d0 ;
output Iout28 ;
output Iout12 ;
output Iout52 ;
output Iout33 ;
output Iout26 ;
output Iout22 ;
output Ifinal_refresh_d1_d0 ;
wire Iin_d0_d1 ;
output Iout32 ;
output Iout23 ;
output Iout12 ;
output Iout49 ;
output Iout41 ;
output Iout39 ;
wire Iin_d5_d0 ;
output Iout28 ;
output Iout48 ;
output Iout46 ;
output Iout42 ;
output Iout35 ;
output Iout33 ;
output Iout47 ;
wire Iin_d4_d1 ;
output Ifinal_refresh_d4_d1 ;
output Iout9 ;
wire Iin_d3_d0 ;
output Iout36 ;
output Iout2 ;
wire Iin_d0_d0 ;
output Iout50 ;
output Ifinal_refresh_d5_d1 ;
output Iout45 ;
output Iout21 ;
output Iout14 ;
output Iout53 ;
output Iout40 ;
output Iout25 ;
output Iout29 ;
output Iout37 ;
output Ifinal_refresh_d0_d0 ;
output Iout17 ;
output Ifinal_refresh_d0_d1 ;
output Iout43 ;
output Iout19 ;
output Iout13 ;
output Iout3 ;
output Iout0 ;
output Ifinal_refresh_d3_d0 ;
output Iout54 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_d3_d0 ;
wire Iin_d4_d1 ;
output Iout42 ;
output Iout32 ;
wire Iin_d3_d1 ;
output Iout44 ;
output Iout10 ;
output Iout56 ;
output Iout51 ;
output Iout6 ;
wire Iin_d5_d1 ;
output Iout49 ;
output Iout25 ;
wire Iin_d0_d0 ;
output Iout1 ;
wire Iin_d2_d1 ;
output Iout54 ;
output Ifinal_refresh_d3_d1 ;
output Iout58 ;
output Iout53 ;
output Iout48 ;
output Iout38 ;
output Iout50 ;
output Iout24 ;
output Iout0 ;
output Ifinal_refresh_d4_d1 ;
output Iout8 ;
output Iout23 ;
output Iout20 ;
output Iout19 ;
wire Iin_d5_d0 ;
output Iout46 ;
output Iout43 ;
output Iout18 ;
wire Iin_d1_d0 ;
wire Iin_d0_d1 ;
output Iout41 ;
output Iout3 ;
wire Iin_d1_d1 ;
output Iout16 ;
output Iout7 ;
output Iout11 ;
output Ifinal_refresh_d0_d1 ;
wire Iin_d2_d0 ;
output Iout17 ;
output Ifinal_refresh_d0_d0 ;
output Iout34 ;
output Ifinal_refresh_d5_d1 ;
output Iout10 ;
output Iout47 ;
output Iout9 ;
output Iout51 ;
output Iout40 ;
output Iout39 ;
output Iout15 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

848
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4/netlist/verilog.v

@ -387,444 +387,444 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4(Iin_d0_d0
// -- signals ---
output Iout87 ;
output Iout153 ;
wire Iin_fX32_a ;
wire Iin_d6_d0 ;
output Iout36 ;
output Iout111 ;
output Iout157 ;
output Ifinal_refresh_d3_d0 ;
output Iout257 ;
output Iout244 ;
output Iout43 ;
output Iout134 ;
wire Iin_tX30_a ;
wire Iin_d1_d1 ;
output Iout329 ;
output Iout237 ;
output Iout15 ;
output Iout139 ;
output Ifinal_refresh_d5_d1 ;
wire Iin_tX28_a ;
output Iout65 ;
output Iout52 ;
output Iout164 ;
output Iout182 ;
output Iout268 ;
wire Iin_fX33_a ;
output Iout159 ;
output Iout221 ;
wire Iin_tX24_a ;
output Iout79 ;
output Iout104 ;
output Iout127 ;
output Iout141 ;
output Iout334 ;
output Ifinal_refresh_d7_d0 ;
wire Iin_fX25_a ;
output Iout108 ;
output Ifinal_refresh_d1_d1 ;
output Iout49 ;
output Iout82 ;
wire Iin_d1_d0 ;
output Iout107 ;
output Iout186 ;
wire Iin_fX29_a ;
output Iout193 ;
output Iout199 ;
output Iout27 ;
output Iout6 ;
output Iout83 ;
output Iout0 ;
output Iout340 ;
output Iout301 ;
output Iout85 ;
wire Iin_fX16_a ;
output Iout80 ;
output Iout316 ;
output Iout260 ;
output Iout100 ;
output Iout13 ;
output Iout222 ;
wire Iin_d3_d0 ;
output Iout317 ;
output Iout233 ;
output Iout114 ;
output Iout128 ;
output Iout299 ;
output Iout154 ;
output Iout188 ;
output Iout253 ;
wire Iin_tX14_a ;
output Ifinal_refresh_d3_d1 ;
output Iout118 ;
output Iout146 ;
output Iout194 ;
output Iout292 ;
output Iout78 ;
output Iout77 ;
output Iout10 ;
output Iout297 ;
output Iout267 ;
output Iout53 ;
output Iout34 ;
output Iout113 ;
output Iout158 ;
output Iout303 ;
wire Iin_tX11_a ;
output Iout152 ;
wire Iin_d4_d0 ;
output Iout242 ;
output Iout229 ;
output Iout92 ;
output Iout293 ;
wire Iin_fX14_a ;
wire Iin_d8_d1 ;
output Iout318 ;
output Iout45 ;
wire Iin_tX12_a ;
output Iout205 ;
output Ifinal_refresh_d7_d1 ;
output Iout177 ;
output Iout259 ;
wire Iin_fX31_a ;
output Iout312 ;
wire Iin_fX12_a ;
output Iout171 ;
output Iout275 ;
output Iout20 ;
output Iout226 ;
wire Iin_fX22_a ;
output Iout9 ;
output Iout5 ;
wire Iin_tX21_a ;
output Iout204 ;
wire Iin_tX17_a ;
output Iout336 ;
output Iout276 ;
output Iout55 ;
output Iout169 ;
output Iout337 ;
output Iout236 ;
output Iout220 ;
output Iout101 ;
output Iout197 ;
wire Iin_d0_d1 ;
output Iout347 ;
output Iout29 ;
output Iout322 ;
output Iout265 ;
output Iout42 ;
output Iout106 ;
output Iout119 ;
output Iout246 ;
output Iout112 ;
output Iout314 ;
output Iout88 ;
output Iout130 ;
output Iout155 ;
output Iout335 ;
output Iout324 ;
output Iout68 ;
wire Iin_tX10_a ;
output Ifinal_refresh_d5_d0 ;
output Iout195 ;
wire Iin_fX19_a ;
output Iout123 ;
output Iout345 ;
output Iout282 ;
output Iout33 ;
output Iout12 ;
wire Iin_fX28_a ;
output Iout284 ;
output Iout251 ;
output Iout225 ;
output Iout89 ;
output Iout117 ;
output Iout138 ;
output Iout151 ;
output Iout346 ;
output Iout304 ;
output Iout213 ;
output Iout185 ;
output Iout288 ;
output Iout283 ;
output Iout62 ;
output Iout18 ;
output Iout331 ;
output Iout70 ;
output Iout196 ;
output Iout300 ;
output Iout333 ;
wire Iin_fX21_a ;
output Iout22 ;
output Iout216 ;
output Iout144 ;
output Iout191 ;
wire Iin_tX34_a ;
output Iout30 ;
output Iout202 ;
output Ifinal_refresh_d4_d0 ;
output Iout84 ;
output Iout179 ;
wire Iin_fX18_a ;
wire Iin_fX9_a ;
output Iout105 ;
output Iout41 ;
wire Iin_fX27_a ;
output Iout273 ;
wire Iin_fX20_a ;
output Iout7 ;
output Iout308 ;
output Iout231 ;
output Iout218 ;
output Iout91 ;
output Iout59 ;
output Iout40 ;
wire Iin_tX16_a ;
output Iout291 ;
output Iout286 ;
output Iout4 ;
output Iout208 ;
output Iout338 ;
output Iout315 ;
output Iout296 ;
output Iout323 ;
output Iout64 ;
output Iout200 ;
output Iout256 ;
output Iout150 ;
output Ifinal_refresh_d2_d1 ;
output Iout269 ;
output Iout215 ;
output Iout51 ;
output Iout149 ;
output Iout274 ;
output Iout61 ;
output Iout17 ;
output Iout140 ;
output Iout203 ;
output Iout341 ;
output Iout313 ;
output Iout8 ;
wire Iin_fX15_a ;
wire Iin_fX30_a ;
wire Iin_d7_d1 ;
wire Iin_d6_d1 ;
output Iout295 ;
output Ifinal_refresh_d1_d0 ;
output Iout16 ;
output Iout142 ;
output Iout261 ;
output Iout172 ;
output Iout174 ;
output Iout211 ;
wire Iin_d5_d1 ;
output Iout81 ;
output Iout1 ;
output Iout115 ;
output Iout209 ;
output Iout11 ;
output Iout131 ;
output Iout187 ;
output Iout302 ;
output Iout37 ;
output Iout178 ;
wire Iin_tX19_a ;
wire Iin_fX26_a ;
output Iout66 ;
output Iout125 ;
output Iout143 ;
output Iout332 ;
output Iout97 ;
wire Iin_tX22_a ;
output Iout163 ;
output Iout176 ;
wire Iin_d8_d0 ;
output Iout230 ;
output Iout306 ;
output Ifinal_refresh_d4_d1 ;
output Iout285 ;
output Iout210 ;
output Iout94 ;
wire Iin_fX35_a ;
output Iout280 ;
output Iout271 ;
output Iout180 ;
output Iout198 ;
output Iout289 ;
output Iout23 ;
output Iout137 ;
wire Iin_tX23_a ;
output Iout67 ;
output Iout21 ;
output Iout135 ;
output Iout344 ;
output Iout319 ;
output Iout212 ;
output Iout98 ;
output Iout63 ;
output Iout44 ;
output Iout294 ;
output Iout252 ;
output Iout93 ;
output Iout73 ;
wire Iin_tX15_a ;
output Iout19 ;
output Iout136 ;
output Iout206 ;
output Iout328 ;
output Iout50 ;
wire Iin_fX23_a ;
output Ifinal_refresh_d6_d0 ;
output Iout278 ;
output Iout69 ;
output Ifinal_refresh_d0_d0 ;
output Iout248 ;
output Iout227 ;
output Iout126 ;
wire Iin_tX31_a ;
wire Iin_fX34_a ;
output Iout238 ;
wire Iin_tX32_a ;
output Iout170 ;
output Iout183 ;
output Iout310 ;
output Iout122 ;
output Iout175 ;
output Iout121 ;
wire Iin_fX24_a ;
output Iout147 ;
output Iout189 ;
output Iout277 ;
output Iout228 ;
output Iout71 ;
output Iout58 ;
output Iout110 ;
wire Iin_d4_d1 ;
output Iout305 ;
output Iout234 ;
output Iout48 ;
output Iout35 ;
wire Iin_fX10_a ;
output Iout156 ;
output Iout192 ;
wire Iin_tX26_a ;
output Iout342 ;
output Iout72 ;
output Iout272 ;
output Iout109 ;
output Iout161 ;
wire Iin_tX35_a ;
output Iout343 ;
output Iout330 ;
output Iout325 ;
wire Iin_tX25_a ;
wire Iin_d2_d1 ;
output Iout290 ;
output Iout124 ;
output Iout166 ;
output Iout263 ;
output Iout250 ;
wire Iin_tX18_a ;
output Iout76 ;
output Iout39 ;
output Iout26 ;
output Iout132 ;
output Iout339 ;
output Iout259 ;
output Iout31 ;
output Ifinal_refresh_d0_d1 ;
output Iout241 ;
output Iout74 ;
output Iout3 ;
output Iout167 ;
wire Iin_d7_d0 ;
output Iout116 ;
output Iout129 ;
output Iout162 ;
output Iout239 ;
output Iout96 ;
output Iout165 ;
output Iout190 ;
output Iout243 ;
output Iout90 ;
output Iout32 ;
output Iout103 ;
wire Iin_d5_d0 ;
output Iout262 ;
output Iout28 ;
output Iout120 ;
output Iout148 ;
output Iout173 ;
output Iout201 ;
output Iout320 ;
output Iout2 ;
output Iout102 ;
wire Iin_tX13_a ;
output Iout14 ;
output Iout209 ;
wire Iin_d3_d1 ;
output Iout281 ;
output Iout75 ;
output Iout300 ;
output Iout244 ;
output Iout235 ;
output Iout89 ;
output Iout13 ;
output Iout19 ;
output Iout283 ;
output Iout273 ;
output Iout269 ;
output Iout85 ;
output Iout32 ;
output Iout347 ;
output Iout305 ;
output Iout146 ;
wire Iin_tX26_a ;
output Iout317 ;
output Iout221 ;
output Iout73 ;
output Iout116 ;
output Iout180 ;
output Iout192 ;
output Iout280 ;
output Iout69 ;
output Iout41 ;
output Iout18 ;
output Iout112 ;
output Iout129 ;
output Iout345 ;
output Iout242 ;
wire Iin_fX15_a ;
output Iout327 ;
output Iout264 ;
output Iout14 ;
output Iout111 ;
output Iout128 ;
wire Iin_d2_d1 ;
output Iout310 ;
output Iout67 ;
wire Iin_fX10_a ;
output Iout326 ;
output Iout231 ;
wire Iin_tX24_a ;
wire Iin_tX23_a ;
output Iout38 ;
output Iout125 ;
output Iout187 ;
wire Iin_d0_d0 ;
output Iout25 ;
output Iout170 ;
output Iout268 ;
output Iout258 ;
output Iout230 ;
output Iout171 ;
output Iout306 ;
output Iout48 ;
output Iout105 ;
output Iout114 ;
output Iout10 ;
output Ifinal_refresh_d6_d0 ;
output Iout276 ;
output Iout266 ;
wire Iin_tX18_a ;
output Iout160 ;
output Iout197 ;
output Ifinal_refresh_d0_d1 ;
output Iout87 ;
output Iout21 ;
wire Iin_fX14_a ;
wire Iin_d4_d0 ;
wire Iin_d0_d1 ;
output Iout340 ;
wire Iin_fX33_a ;
output Iout7 ;
output Iout154 ;
output Iout332 ;
output Iout144 ;
output Iout174 ;
wire Iin_fX35_a ;
output Iout205 ;
output Iout220 ;
output Iout210 ;
output Iout167 ;
output Iout33 ;
output Iout184 ;
output Iout311 ;
output Iout298 ;
output Iout25 ;
output Iout160 ;
output Iout267 ;
output Iout106 ;
output Iout156 ;
output Ifinal_refresh_d6_d1 ;
output Iout255 ;
output Iout135 ;
output Iout179 ;
output Iout328 ;
output Iout72 ;
output Iout107 ;
output Iout152 ;
wire Iin_tX28_a ;
output Iout196 ;
output Iout92 ;
output Iout88 ;
output Iout39 ;
output Iout101 ;
output Iout59 ;
output Iout103 ;
output Iout208 ;
output Iout323 ;
output Iout247 ;
output Iout60 ;
output Iout235 ;
output Iout258 ;
output Iout249 ;
wire Iin_fX17_a ;
output Iout133 ;
output Iout321 ;
output Iout54 ;
output Iout168 ;
output Iout219 ;
output Iout46 ;
output Iout56 ;
output Ifinal_refresh_d8_d1 ;
wire Iin_fX23_a ;
output Iout338 ;
output Iout295 ;
output Iout254 ;
output Iout224 ;
output Iout181 ;
output Iout223 ;
output Ifinal_refresh_d8_d0 ;
output Iout270 ;
wire Iin_tX20_a ;
output Iout279 ;
output Iout266 ;
output Iout99 ;
output Iout47 ;
wire Iin_fX11_a ;
wire Iin_tX29_a ;
output Iout309 ;
output Ifinal_refresh_d2_d0 ;
output Iout217 ;
output Iout95 ;
output Iout38 ;
wire Iin_fX13_a ;
output Iout145 ;
wire Iin_tX15_a ;
output Iout54 ;
output Iout120 ;
output Iout162 ;
output Iout173 ;
output Iout261 ;
output Iout34 ;
output Iout194 ;
output Iout226 ;
output Iout75 ;
output Iout110 ;
wire Iin_d2_d0 ;
output Iout307 ;
output Ifinal_refresh_d3_d0 ;
output Iout74 ;
output Iout79 ;
output Iout55 ;
output Iout117 ;
output Iout122 ;
output Iout132 ;
output Iout343 ;
wire Iin_fX19_a ;
wire Iin_tX10_a ;
output Iout223 ;
output Iout315 ;
output Ifinal_refresh_d5_d1 ;
output Iout91 ;
output Iout150 ;
output Iout246 ;
output Iout12 ;
output Iout1 ;
output Iout193 ;
output Iout290 ;
output Iout121 ;
output Iout149 ;
output Iout245 ;
output Iout131 ;
output Iout299 ;
output Iout113 ;
output Iout161 ;
wire Iin_fX27_a ;
output Iout301 ;
output Iout297 ;
wire Iin_d4_d1 ;
output Iout313 ;
output Iout100 ;
output Iout93 ;
output Iout47 ;
output Iout138 ;
wire Iin_fX34_a ;
output Iout191 ;
output Iout341 ;
output Iout334 ;
output Iout319 ;
output Iout275 ;
output Iout94 ;
output Iout80 ;
wire Iin_tX27_a ;
wire Iin_d7_d1 ;
output Iout253 ;
output Iout227 ;
output Iout293 ;
output Iout284 ;
wire Iin_fX22_a ;
output Iout166 ;
wire Iin_d1_d1 ;
output Iout232 ;
wire Iin_tX32_a ;
output Iout163 ;
output Iout201 ;
wire Iin_d6_d0 ;
output Iout324 ;
output Iout271 ;
output Iout198 ;
output Iout203 ;
output Ifinal_refresh_d5_d0 ;
output Iout5 ;
wire Iin_tX21_a ;
output Iout104 ;
output Iout181 ;
output Iout272 ;
output Iout260 ;
output Iout9 ;
output Iout153 ;
output Iout336 ;
output Iout252 ;
output Iout126 ;
output Iout199 ;
output Iout291 ;
output Ifinal_refresh_d2_d1 ;
output Ifinal_refresh_d7_d0 ;
output Iout240 ;
output Iout86 ;
wire Iin_d0_d0 ;
output Iout327 ;
output Iout326 ;
output Iout287 ;
output Iout264 ;
output Iout245 ;
output Iout214 ;
output Iout172 ;
output Iout102 ;
output Iout155 ;
output Iout233 ;
output Iout288 ;
output Iout318 ;
output Iout304 ;
output Iout248 ;
wire Iin_tX22_a ;
output Iout178 ;
output Iout188 ;
wire Iin_d8_d0 ;
output Iout250 ;
output Iout320 ;
wire Iin_fX11_a ;
output Iout239 ;
output Iout137 ;
output Iout195 ;
output Iout346 ;
output Iout303 ;
output Iout53 ;
output Iout265 ;
output Iout36 ;
output Iout29 ;
output Iout159 ;
output Iout57 ;
wire Iin_tX33_a ;
wire Iin_tX27_a ;
output Iout232 ;
output Iout24 ;
wire Iin_fX30_a ;
output Iout329 ;
output Iout90 ;
output Iout44 ;
output Iout35 ;
wire Iin_tX17_a ;
output Iout289 ;
output Iout82 ;
output Iout202 ;
output Iout40 ;
wire Iin_tX11_a ;
output Iout134 ;
wire Iin_fX31_a ;
wire Iin_tX16_a ;
wire Iin_d6_d1 ;
wire Iin_fX25_a ;
output Iout43 ;
output Iout335 ;
output Iout236 ;
wire Iin_fX20_a ;
output Iout78 ;
output Iout63 ;
output Iout109 ;
output Iout22 ;
output Iout277 ;
output Iout218 ;
output Iout23 ;
output Iout186 ;
output Iout237 ;
output Iout68 ;
output Iout6 ;
output Iout169 ;
output Iout212 ;
output Iout58 ;
wire Iin_fX16_a ;
output Iout115 ;
output Iout123 ;
wire Iin_tX13_a ;
output Iout11 ;
output Iout157 ;
output Iout294 ;
output Iout279 ;
output Iout84 ;
wire Iin_tX25_a ;
output Iout342 ;
output Ifinal_refresh_d1_d1 ;
wire Iin_fX21_a ;
wire Iin_tX12_a ;
output Iout4 ;
output Iout136 ;
output Iout215 ;
wire Iin_fX26_a ;
output Iout65 ;
output Iout312 ;
output Iout97 ;
output Iout17 ;
wire Iin_tX9_a ;
output Iout308 ;
wire Iin_fX32_a ;
wire Iin_fX17_a ;
output Iout142 ;
output Iout148 ;
output Iout337 ;
output Ifinal_refresh_d1_d0 ;
output Iout314 ;
output Iout270 ;
output Iout70 ;
output Iout325 ;
output Iout228 ;
output Iout175 ;
output Iout322 ;
output Iout257 ;
wire Iin_tX19_a ;
output Iout20 ;
wire Iin_fX12_a ;
output Iout296 ;
output Iout234 ;
output Iout81 ;
output Iout222 ;
output Iout16 ;
wire Iin_tX30_a ;
output Iout330 ;
output Iout52 ;
output Iout42 ;
wire Iin_fX24_a ;
output Iout331 ;
output Iout309 ;
output Iout216 ;
output Iout99 ;
output Iout130 ;
output Iout140 ;
output Iout27 ;
output Iout118 ;
output Iout207 ;
wire Iin_d7_d0 ;
output Iout56 ;
output Iout3 ;
wire Iin_fX13_a ;
output Iout168 ;
output Iout145 ;
output Iout190 ;
wire Iin_d1_d0 ;
output Ifinal_refresh_d2_d0 ;
output Iout256 ;
output Iout49 ;
wire Iin_fX9_a ;
output Iout177 ;
output Ifinal_refresh_d7_d1 ;
output Iout238 ;
output Ifinal_refresh_d3_d1 ;
wire Iin_tX33_a ;
output Iout316 ;
output Iout263 ;
output Iout133 ;
output Iout219 ;
output Iout127 ;
wire Iin_tX14_a ;
output Iout24 ;
output Iout164 ;
output Iout200 ;
output Iout333 ;
output Iout307 ;
output Ifinal_refresh_d4_d1 ;
output Iout302 ;
output Iout274 ;
output Iout61 ;
wire Iin_fX29_a ;
output Iout255 ;
output Iout45 ;
output Iout139 ;
output Iout206 ;
output Iout262 ;
output Iout225 ;
output Iout224 ;
output Iout98 ;
output Iout30 ;
output Iout108 ;
output Iout165 ;
wire Iin_tX29_a ;
wire Iin_d5_d1 ;
output Ifinal_refresh_d0_d0 ;
output Iout251 ;
output Iout229 ;
output Iout26 ;
output Iout292 ;
output Iout285 ;
output Iout143 ;
output Iout151 ;
output Iout158 ;
output Iout213 ;
output Iout83 ;
wire Iin_tX34_a ;
output Iout344 ;
output Iout278 ;
output Iout243 ;
output Iout241 ;
output Iout66 ;
output Iout15 ;
wire Iin_d3_d0 ;
output Iout287 ;
output Iout64 ;
wire Iin_tX31_a ;
wire Iin_d5_d0 ;
output Iout46 ;
wire Iin_tX35_a ;
output Iout60 ;
output Iout50 ;
output Iout189 ;
output Iout298 ;
output Iout37 ;
output Iout28 ;
output Ifinal_refresh_d8_d0 ;
wire Iin_tX20_a ;
output Iout182 ;
output Iout185 ;
output Iout286 ;
output Iout281 ;
output Iout95 ;
output Iout51 ;
output Iout217 ;
output Iout62 ;
output Iout8 ;
output Iout119 ;
output Iout147 ;
wire Iin_d8_d1 ;
output Iout321 ;
output Iout211 ;
output Iout282 ;
output Iout77 ;
output Iout176 ;
output Iout249 ;
output Iout141 ;
output Iout0 ;
output Iout183 ;
output Iout204 ;
output Iout339 ;
output Iout214 ;
output Iout96 ;
wire Iin_fX18_a ;
output Iout76 ;
output Iout2 ;
output Ifinal_refresh_d8_d1 ;
output Iout71 ;
output Iout124 ;
wire Iin_fX28_a ;
// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_39_4 Iatree0 (.Iin0 (Iin_fX9_a ), .Iin1 (Iin_fX10_a ), .Iin2 (Iin_fX11_a ), .Iin3 (Iin_fX12_a ), .Iin4 (Iin_fX13_a ), .Iin5 (Iin_fX14_a ), .Iin6 (Iin_fX15_a ), .Iin7 (Iin_fX16_a ), .Iin8 (Iin_fX17_a ), .out(Iout0 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delay__chain_32_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0delay__chain_32_4(out, in, vdd, vss);
input in;
// -- signals ---
wire in;
wire out ;
wire in;
wire Idly1_a ;
// --- instances

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delay__chain_33_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

17
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delay__chain_33_4/netlist/verilog.v

@ -1,17 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0delay__chain_33_4(out, in, vdd, vss);
input vdd;
input vss;
output out;
input in;
// -- signals ---
wire Idly1_a ;
wire out ;
wire Idly2_a ;
wire in;
// --- instances
DLY4_X1 Idly0 (.y(Idly1_a ), .a(in), .vdd(vdd), .vss(vss));
DLY4_X1 Idly1 (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
DLY4_X1 Idly2 (.y(out), .a(Idly2_a ), .vdd(vdd), .vss(vss));
endmodule

8
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_32_4/netlist/verilog.v

@ -7,14 +7,14 @@ module tmpl_0_0dataflow__neuro_0_0delayprog_32_4(out, in, Is0 , Is1 , vdd, vss);
input Is1 ;
// -- signals ---
wire Idly2_a ;
wire Idly1_a ;
wire Is0 ;
wire Idly2_y ;
wire in;
wire out ;
wire Is1 ;
wire Is0 ;
wire Idly1_a ;
wire Idly2_a ;
wire I_a1 ;
wire out ;
wire Idly0_a ;
wire Idly0_y ;

42
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/verilog.v

@ -9,34 +9,34 @@ module tmpl_0_0dataflow__neuro_0_0delayprog_34_4(out, in, Is0 , Is1 , Is2 , Is3
input Is3 ;
// -- signals ---
wire Idly0_y ;
wire Idly13_a ;
wire I_a3 ;
wire Idly7_a ;
wire in;
wire Idly6_a ;
wire Idly5_a ;
wire Is3 ;
wire Idly9_a ;
wire Idly4_a ;
wire Is1 ;
wire out ;
wire Is0 ;
wire in;
wire I_a1 ;
wire Idly7_a ;
wire Idly14_a ;
wire Idly1_a ;
wire I_a2 ;
wire Idly1_a ;
wire Idly11_a ;
wire Is2 ;
wire Idly0_a ;
wire Idly14_a ;
wire Idly2_a ;
wire Idly2_y ;
wire Idly3_a ;
wire Idly6_y ;
wire Is3 ;
wire Idly12_a ;
wire I_a1 ;
wire Idly10_a ;
wire Idly8_a ;
wire Is1 ;
wire Idly13_a ;
wire Idly4_a ;
wire Idly6_y ;
wire Idly11_a ;
wire Idly2_a ;
wire I_a3 ;
wire Idly0_y ;
wire Idly9_a ;
wire Idly14_y ;
wire Idly2_y ;
wire Idly12_a ;
wire Idly6_a ;
wire Is2 ;
wire Idly3_a ;
wire Idly0_a ;
// --- instances
AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));

384
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0demux_330_4/netlist/verilog.v

@ -193,209 +193,209 @@ module tmpl_0_0dataflow__neuro_0_0demux_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
// -- signals ---
output Iout1_d_d27_d1 ;
output Iout2_d_d2_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d16_d1 ;
output Iout1_d_d27_d0 ;
wire _out1_a_B ;
output Iout2_d_d25_d1 ;
output Iout2_d_d10_d0 ;
wire Iin_d_d12_d0 ;
output Iout1_d_d16_d1 ;
wire I_c_t_buf0 ;
wire Iin_d_d1_d1 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d11_d1 ;
output Iout1_d_d29_d1 ;
output Iout1_d_d7_d0 ;
wire Iin_d_d13_d1 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d14_d0 ;
output Iout1_d_d24_d1 ;
output Iout1_d_d12_d0 ;
output Iout2_d_d29_d1 ;
output Iout2_d_d12_d0 ;
output Iout1_d_d14_d1 ;
output Iout1_d_d8_d0 ;
wire Iin_d_d3_d1 ;
output Iout2_d_d15_d1 ;
wire Iin_d_d21_d1 ;
wire Iout1_v ;
output Iout2_d_d0_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d7_d0 ;
output Iout2_d_d22_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d29_d0 ;
output Iout1_d_d4_d0 ;
output Iin_v ;
wire _en ;
wire _reset_BX ;
wire Iout2_a ;
output Iout2_d_d3_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d21_d0 ;
output Iout2_d_d27_d0 ;
wire _out_v ;
output Iout2_d_d3_d1 ;
wire Iin_d_d4_d0 ;
output Iout2_d_d15_d0 ;
output Iout2_d_d19_d0 ;
output Iout1_d_d20_d1 ;
output Iout1_d_d15_d0 ;
output Iout1_d_d13_d1 ;
output Iout1_d_d7_d1 ;
output Iout2_d_d14_d1 ;
output Iout1_d_d2_d1 ;
wire Iin_d_d27_d0 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d9_d0 ;
output Iout2_d_d23_d1 ;
wire Iin_d_d24_d1 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d6_d0 ;
output Iout2_d_d6_d0 ;
output Iout1_d_d25_d0 ;
output Iout1_d_d16_d0 ;
wire Iin_d_d19_d1 ;
output Iout2_d_d8_d0 ;
output Iout1_d_d25_d1 ;
output Iout2_d_d17_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d11_d1 ;
output Iout2_d_d21_d1 ;
wire Iout2_v ;
output Iout2_d_d0_d0 ;
output Iout1_d_d28_d1 ;
wire Iin_d_d9_d1 ;
output Iout2_d_d2_d0 ;
output Iout1_d_d3_d0 ;
wire I_reset_BXX0 ;
output Iout2_d_d27_d1 ;
wire Iin_d_d2_d0 ;
output Iout2_d_d9_d0 ;
output Iout1_d_d24_d0 ;
output Iout1_d_d9_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d14_d0 ;
output Iout1_d_d9_d1 ;
wire _c_v ;
wire Iin_d_d25_d1 ;
output Iout2_d_d18_d0 ;
output Iout2_d_d20_d1 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d11_d0 ;
wire Icond_d_d0_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d22_d0 ;
output Iout2_d_d29_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d18_d0 ;
output Iout1_d_d21_d1 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d28_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d16_d0 ;
output Iout1_d_d28_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d15_d0 ;
output Iout1_d_d14_d0 ;
wire Iin_d_d7_d1 ;
output Iout2_d_d22_d1 ;
output Iout2_d_d9_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d14_d0 ;
output Iout1_d_d22_d0 ;
output Iout1_d_d9_d0 ;
output Icond_v ;
wire Iin_d_d11_d1 ;
wire Iin_d_d12_d1 ;
output Iout1_d_d16_d0 ;
output Iout1_d_d11_d0 ;
wire I_reset_BXX0 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d1_d0 ;
output Iout2_d_d2_d1 ;
output Iout1_d_d24_d0 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d15_d1 ;
wire Iin_d_d22_d0 ;
output Iout2_d_d23_d0 ;
output Iout1_d_d17_d1 ;
output Iout1_d_d15_d1 ;
wire _in_v ;
wire Iin_d_d28_d1 ;
output Iout1_d_d17_d0 ;
output Iout1_d_d24_d1 ;
wire Iout1_a ;
output Iout2_d_d11_d0 ;
output Iout1_d_d28_d0 ;
output Iout2_d_d19_d1 ;
output Iout2_d_d16_d0 ;
output Iout2_d_d26_d0 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d5_d1 ;
output Iout2_d_d24_d1 ;
output Iout1_d_d19_d0 ;
wire Icond_d_d0_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d8_d0 ;
output Iout2_d_d7_d1 ;
output Iout2_d_d17_d0 ;
wire Iin_d_d25_d0 ;
output Iout1_d_d23_d1 ;
wire Iin_d_d23_d1 ;
output Iout1_d_d0_d1 ;
output Iout1_d_d18_d0 ;
output Iout1_d_d5_d0 ;
wire Iout1_a_B_buf_out0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d10_d1 ;
output Iout2_d_d13_d0 ;
output Iout1_d_d22_d1 ;
output Iout2_d_d28_d1 ;
wire Iin_d_d28_d0 ;
wire Iout_en_buf_out0 ;
output Iout2_d_d18_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d2_d1 ;
output Iout2_d_d26_d1 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d11_d1 ;
output Iout1_d_d1_d1 ;
output Iout1_d_d13_d0 ;
output Iin_a ;
output Iout2_d_d6_d1 ;
output Iout1_d_d10_d0 ;
wire Iout2_a_B_buf_out0 ;
output Iout2_d_d8_d1 ;
output Iout1_d_d19_d1 ;
output Iout1_d_d20_d0 ;
output Iout2_d_d11_d1 ;
output Iout2_d_d13_d1 ;
output Iout2_d_d25_d0 ;
output Icond_v ;
wire _out2_a_B ;
wire Iin_d_d7_d1 ;
output Iout2_d_d19_d1 ;
wire Iin_d_d6_d0 ;
output Iout2_d_d7_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d3_d0 ;
wire I_c_f_buf0 ;
output Iout2_d_d4_d0 ;
wire Iin_d_d19_d0 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d22_d0 ;
output Iout1_d_d0_d0 ;
output Iout2_d_d24_d0 ;
output Iout1_d_d2_d0 ;
wire Iin_d_d15_d0 ;
output Iout1_d_d3_d1 ;
output Iout2_d_d4_d1 ;
output Iout1_d_d26_d0 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d17_d1 ;
output Iout2_d_d20_d0 ;
output Iout2_d_d10_d1 ;
wire Iin_d_d17_d0 ;
output Iout1_d_d5_d1 ;
output Iout2_d_d16_d1 ;
wire Iin_d_d26_d0 ;
output Iout1_d_d21_d0 ;
wire Iout2_a ;
output Iout2_d_d6_d0 ;
output Iout1_d_d7_d1 ;
wire Iin_d_d18_d1 ;
output Iout2_d_d29_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d23_d0 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d10_d1 ;
output Iout2_d_d24_d1 ;
output Iout1_d_d3_d1 ;
output Iout1_d_d15_d0 ;
output Iout1_d_d12_d0 ;
output Iout2_d_d4_d1 ;
wire Iin_d_d24_d1 ;
output Iout1_d_d3_d0 ;
output Iin_v ;
output Iout2_d_d7_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d7_d0 ;
wire _reset_BX ;
wire Iin_d_d3_d1 ;
output Iout2_d_d18_d1 ;
output Iout2_d_d12_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d11_d0 ;
output Iout1_d_d25_d0 ;
wire _out1_a_B ;
output Iout2_d_d16_d1 ;
output Iout2_d_d5_d1 ;
output Iout1_d_d12_d1 ;
output Iout1_d_d23_d0 ;
wire reset_B;
output Iout2_d_d13_d1 ;
wire Iin_d_d0_d0 ;
output Iout2_d_d11_d0 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d14_d0 ;
wire Iin_d_d20_d1 ;
output Iout2_d_d22_d1 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d22_d0 ;
output Iout1_d_d8_d0 ;
output Iout1_d_d5_d0 ;
output Iout2_d_d4_d0 ;
output Iout2_d_d0_d0 ;
output Iout2_d_d13_d0 ;
output Iout1_d_d6_d1 ;
output Iout1_d_d1_d0 ;
wire Iout1_a ;
output Iin_a ;
output Iout2_d_d26_d1 ;
output Iout2_d_d25_d0 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d19_d0 ;
output Iout1_d_d17_d0 ;
output Iout2_d_d29_d0 ;
wire Iin_d_d27_d0 ;
wire Iout1_v ;
wire Iout_en_buf_out0 ;
output Iout2_d_d14_d1 ;
wire Iin_d_d20_d1 ;
output Iout2_d_d27_d1 ;
wire Iin_d_d9_d0 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d28_d0 ;
output Iout2_d_d12_d0 ;
output Iout1_d_d0_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d16_d0 ;
wire Icond_d_d0_d1 ;
output Iout2_d_d7_d0 ;
wire I_c_f_buf0 ;
output Iout2_d_d2_d0 ;
wire Iin_d_d12_d0 ;
output Iout2_d_d18_d0 ;
output Iout1_d_d16_d1 ;
output Iout1_d_d21_d0 ;
wire Iin_d_d5_d1 ;
output Iout2_d_d21_d1 ;
output Iout2_d_d23_d1 ;
wire Iin_d_d18_d0 ;
output Iout1_d_d28_d1 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d23_d1 ;
output Iout1_d_d15_d1 ;
output Iout1_d_d14_d1 ;
wire Iout1_a_B_buf_out0 ;
wire _out_v ;
output Iout2_d_d20_d1 ;
wire Iin_d_d6_d0 ;
output Iout2_d_d15_d0 ;
output Iout1_d_d17_d1 ;
output Iout1_d_d27_d0 ;
wire Iout2_v ;
output Iout2_d_d26_d0 ;
wire Iin_d_d2_d1 ;
output Iout1_d_d20_d1 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d3_d0 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d26_d0 ;
output Iout1_d_d20_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d24_d0 ;
output Iout1_d_d5_d1 ;
output Iout2_d_d17_d0 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d23_d0 ;
output Iout2_d_d10_d0 ;
output Iout1_d_d29_d1 ;
output Iout2_d_d11_d1 ;
output Iout2_d_d10_d1 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d0_d1 ;
output Iout2_d_d8_d0 ;
output Iout1_d_d25_d1 ;
output Iout1_d_d4_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d8_d0 ;
output Iout2_d_d0_d1 ;
output Iout1_d_d29_d0 ;
output Iout1_d_d10_d0 ;
output Iout2_d_d20_d0 ;
output Iout2_d_d27_d0 ;
wire Iin_d_d28_d1 ;
output Iout2_d_d19_d0 ;
output Iout1_d_d6_d0 ;
output Iout2_d_d3_d0 ;
wire Icond_d_d0_d0 ;
wire Iin_d_d28_d0 ;
output Iout2_d_d6_d1 ;
wire Iin_d_d25_d0 ;
wire _c_v ;
wire I_c_t_buf0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d22_d1 ;
output Iout2_d_d14_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d13_d0 ;
output Iout1_d_d2_d1 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d23_d1 ;
output Iout2_d_d25_d1 ;
output Iout1_d_d21_d1 ;
output Iout1_d_d8_d1 ;
wire Iout2_a_B_buf_out0 ;
wire Iin_d_d27_d1 ;
output Iout2_d_d28_d1 ;
wire Iin_d_d5_d0 ;
output Iout1_d_d19_d1 ;
output Iout1_d_d7_d0 ;
output Iout1_d_d2_d0 ;
output Iout2_d_d9_d1 ;
output Iout1_d_d27_d1 ;
output Iout1_d_d22_d1 ;
wire Iin_d_d4_d0 ;
output Iout1_d_d13_d1 ;
output Iout1_d_d18_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d21_d0 ;
output Iout1_d_d9_d1 ;
wire _in_v ;
wire reset_B;
wire Iin_d_d19_d1 ;
wire Iin_d_d21_d1 ;
output Iout1_d_d19_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d20_d0 ;
wire _en ;
wire _out2_a_B ;
wire Iin_d_d6_d1 ;
output Iout2_d_d17_d1 ;
output Iout2_d_d24_d0 ;
wire Iin_d_d26_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

412
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0demux_331_4/netlist/verilog.v

@ -199,215 +199,215 @@ module tmpl_0_0dataflow__neuro_0_0demux_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
// -- signals ---
output Iout1_d_d2_d1 ;
wire Iin_d_d3_d0 ;
output Iout2_d_d8_d0 ;
output Iout2_d_d12_d0 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d21_d0 ;
output Icond_v ;
wire I_c_t_buf0 ;
output Iout2_d_d7_d1 ;
output Iout2_d_d21_d1 ;
output Iout1_d_d28_d1 ;
output Iout1_d_d30_d0 ;
output Iout2_d_d28_d0 ;
output Iin_a ;
wire Iout2_a_B_buf_out0 ;
wire Iin_d_d1_d0 ;
output Iout2_d_d23_d0 ;
output Iout1_d_d15_d0 ;
wire Iin_d_d9_d1 ;
output Iout1_d_d15_d1 ;
output Iout2_d_d6_d1 ;
output Iout1_d_d10_d0 ;
output Iout1_d_d8_d0 ;
wire _out2_a_B ;
output Iout2_d_d0_d1 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d25_d1 ;
output Iout2_d_d13_d0 ;
wire Iin_d_d18_d1 ;
output Iout1_d_d16_d1 ;
output Iout1_d_d5_d1 ;
wire Iin_d_d7_d1 ;
output Iout2_d_d9_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d20_d1 ;
output Iout2_d_d18_d0 ;
wire Iin_d_d18_d0 ;
output Iout1_d_d27_d0 ;
wire Iin_d_d10_d1 ;
output Iout2_d_d24_d1 ;
wire Iout2_v ;
wire Iin_d_d0_d1 ;
output Iout2_d_d22_d1 ;
output Iout1_d_d16_d0 ;
output Iout1_d_d13_d0 ;
wire I_c_f_buf0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d27_d0 ;
wire _en ;
wire Iin_d_d8_d1 ;
output Iout2_d_d5_d0 ;
wire Iin_d_d5_d0 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d17_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d28_d1 ;
output Iout2_d_d2_d0 ;
output Iout1_d_d5_d0 ;
wire _c_v ;
output Iout2_d_d27_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d30_d1 ;
output Iout1_d_d9_d1 ;
output Iout1_d_d6_d1 ;
output Iout2_d_d3_d0 ;
output Iout1_d_d7_d0 ;
wire Iout_en_buf_out0 ;
output Iout2_d_d2_d1 ;
output Iout1_d_d3_d1 ;
wire Iin_d_d4_d1 ;
output Iout2_d_d10_d1 ;
wire Iin_d_d17_d1 ;
output Iout2_d_d4_d0 ;
output Iout2_d_d15_d0 ;
output Iout2_d_d1_d1 ;
output Iout2_d_d15_d1 ;
output Iin_v ;
wire Iin_d_d21_d0 ;
wire Iin_d_d25_d0 ;
output Iout1_d_d21_d1 ;
output Iout1_d_d29_d0 ;
wire Iout1_a_B_buf_out0 ;
wire Iin_d_d24_d1 ;
output Iout2_d_d28_d1 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d0_d0 ;
wire Iin_d_d13_d0 ;
output Iout2_d_d24_d0 ;
output Iout1_d_d20_d1 ;
wire Iin_d_d29_d1 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d0_d1 ;
wire reset_B;
output Iout2_d_d13_d1 ;
output Iout2_d_d10_d0 ;
output Iout2_d_d25_d0 ;
output Iout1_d_d1_d0 ;
output Iout2_d_d5_d1 ;
output Iout2_d_d12_d1 ;
wire Iin_d_d21_d1 ;
output Iout2_d_d20_d0 ;
output Iout1_d_d7_d1 ;
output Iout1_d_d6_d0 ;
wire Iin_d_d2_d0 ;
output Iout1_d_d3_d0 ;
wire _out_v ;
output Iout1_d_d19_d1 ;
wire Iin_d_d12_d0 ;
output Iout1_d_d11_d1 ;
output Iout1_d_d26_d0 ;
output Iout1_d_d2_d0 ;
output Iout2_d_d26_d1 ;
output Iout1_d_d24_d1 ;
wire Iin_d_d15_d1 ;
output Iout2_d_d20_d1 ;
output Iout1_d_d22_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d16_d0 ;
output Iout1_d_d25_d0 ;
wire Iin_d_d2_d1 ;
output Iout2_d_d14_d1 ;
output Iout2_d_d7_d0 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d11_d1 ;
wire Iin_d_d19_d0 ;
output Iout1_d_d30_d1 ;
wire Iout2_a ;
output Iout2_d_d4_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d11_d1 ;
output Iout2_d_d16_d1 ;
output Iout1_d_d17_d0 ;
output Iout1_d_d11_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d9_d0 ;
output Iout1_d_d23_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d19_d1 ;
output Iout1_d_d24_d0 ;
output Iout1_d_d12_d1 ;
output Iout1_d_d25_d1 ;
output Iout1_d_d9_d0 ;
wire Iin_d_d15_d0 ;
wire Icond_d_d0_d0 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d18_d1 ;
output Iout2_d_d11_d0 ;
output Iout1_d_d29_d1 ;
wire Iout1_a ;
output Iout2_d_d17_d1 ;
output Iout1_d_d12_d0 ;
wire _in_v ;
output Iout2_d_d29_d0 ;
wire Iout1_v ;
output Iout2_d_d19_d1 ;
output Iout2_d_d0_d0 ;
wire Iin_d_d22_d0 ;
output Iout1_d_d18_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d7_d0 ;
wire _reset_BX ;
wire Iin_d_d11_d0 ;
output Iout1_d_d8_d1 ;
output Iout1_d_d28_d0 ;
output Iout2_d_d3_d1 ;
wire _out1_a_B ;
output Iout2_d_d30_d0 ;
output Iout2_d_d23_d1 ;
output Iout1_d_d22_d1 ;
output Iout1_d_d1_d1 ;
output Iout1_d_d19_d0 ;
wire Icond_d_d0_d1 ;
wire Iin_d_d26_d1 ;
output Iout2_d_d27_d1 ;
output Iout2_d_d30_d1 ;
output Iout2_d_d1_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d23_d1 ;
output Iout1_d_d23_d1 ;
output Iout1_d_d20_d0 ;
output Iout1_d_d27_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d27_d1 ;
output Iout2_d_d17_d0 ;
wire Iin_d_d24_d0 ;
output Iout1_d_d14_d1 ;
wire I_reset_BXX0 ;
output Iout2_d_d29_d1 ;
output Iout1_d_d13_d1 ;
wire Iin_d_d13_d1 ;
output Iout2_d_d6_d0 ;
output Iout2_d_d16_d0 ;
wire Iin_d_d22_d1 ;
output Iout2_d_d9_d0 ;
wire Iin_d_d10_d0 ;
output Iout2_d_d22_d0 ;
wire Iin_d_d14_d1 ;
output Iout2_d_d26_d0 ;
wire Iin_d_d0_d0 ;
output Iout2_d_d14_d0 ;
output Iout1_d_d15_d1 ;
output Iout1_d_d8_d0 ;
wire Iin_d_d14_d0 ;
output Iout1_d_d8_d1 ;
output Iout1_d_d17_d1 ;
output Iout1_d_d12_d1 ;
wire _out2_a_B ;
wire Icond_d_d0_d1 ;
wire I_c_t_buf0 ;
wire Iin_d_d21_d1 ;
output Iout2_d_d19_d0 ;
output Iout2_d_d7_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d11_d1 ;
output Iout2_d_d16_d0 ;
output Iout1_d_d23_d0 ;
output Iin_v ;
output Iout2_d_d13_d1 ;
output Iout2_d_d7_d0 ;
output Iout2_d_d18_d0 ;
output Iout1_d_d19_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d22_d0 ;
output Iout1_d_d19_d0 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d9_d1 ;
output Iout1_d_d14_d0 ;
wire _c_v ;
wire Iin_d_d24_d1 ;
output Iout2_d_d25_d1 ;
wire Iin_d_d0_d0 ;
output Iout1_d_d27_d1 ;
wire reset_B;
output Iout2_d_d14_d1 ;
output Iout2_d_d18_d1 ;
wire Iin_d_d10_d0 ;
output Iout2_d_d17_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d6_d1 ;
wire Iin_d_d29_d0 ;
output Iout2_d_d29_d1 ;
wire Iin_d_d27_d0 ;
output Iout2_d_d6_d1 ;
output Iout2_d_d0_d0 ;
output Iout2_d_d21_d0 ;
output Iout1_d_d26_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d28_d0 ;
output Iout2_d_d23_d1 ;
output Iout2_d_d25_d0 ;
output Iout1_d_d30_d1 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d11_d0 ;
wire Iout1_a ;
wire Iin_d_d4_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d7_d0 ;
output Iout1_d_d24_d1 ;
output Iout1_d_d7_d0 ;
output Iout1_d_d2_d0 ;
wire Iin_d_d1_d1 ;
output Iout1_d_d9_d0 ;
wire I_c_f_buf0 ;
wire Iout2_a_B_buf_out0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d4_d0 ;
output Iout1_d_d30_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d6_d0 ;
output Iout2_d_d12_d0 ;
output Iout1_d_d24_d0 ;
wire Iin_d_d28_d1 ;
output Iout1_d_d16_d1 ;
output Iout1_d_d21_d0 ;
output Iout1_d_d18_d0 ;
output Iout2_d_d26_d0 ;
wire Iin_d_d5_d1 ;
output Iout2_d_d9_d0 ;
output Iout1_d_d0_d0 ;
output Iout2_d_d16_d1 ;
output Iout1_d_d14_d1 ;
output Iout1_d_d3_d0 ;
output Iout2_d_d27_d0 ;
wire _out_v ;
wire Iin_d_d16_d0 ;
wire Icond_d_d0_d0 ;
wire Iin_d_d9_d1 ;
output Iout2_d_d30_d1 ;
output Iout2_d_d15_d0 ;
output Iout1_d_d3_d1 ;
output Iout2_d_d9_d1 ;
output Iout2_d_d15_d1 ;
output Iout2_d_d17_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d5_d0 ;
output Iout1_d_d2_d1 ;
output Iout1_d_d12_d0 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d13_d0 ;
output Iout1_d_d10_d1 ;
wire Iout1_a_B_buf_out0 ;
output Iin_a ;
output Iout2_d_d0_d1 ;
wire Iin_d_d19_d0 ;
wire _in_v ;
output Icond_v ;
output Iout2_d_d20_d1 ;
output Iout2_d_d22_d1 ;
wire Iin_d_d23_d1 ;
output Iout2_d_d8_d0 ;
wire Iin_d_d8_d0 ;
output Iout2_d_d10_d1 ;
output Iout1_d_d28_d0 ;
output Iout1_d_d17_d0 ;
wire _reset_BX ;
wire Iin_d_d16_d1 ;
output Iout1_d_d11_d1 ;
output Iout1_d_d22_d0 ;
output Iout2_d_d28_d0 ;
wire _en ;
wire Iout1_v ;
wire Iin_d_d14_d1 ;
output Iout2_d_d1_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d15_d0 ;
output Iout2_d_d22_d0 ;
output Iout1_d_d22_d1 ;
output Iout1_d_d27_d0 ;
output Iout2_d_d19_d1 ;
output Iout2_d_d21_d1 ;
wire Iin_d_d1_d0 ;
output Iout1_d_d5_d1 ;
wire Iin_d_d18_d1 ;
output Iout2_d_d20_d0 ;
output Iout1_d_d20_d0 ;
output Iout1_d_d11_d0 ;
output Iout2_d_d2_d0 ;
output Iout2_d_d24_d0 ;
output Iout1_d_d13_d1 ;
output Iout1_d_d5_d0 ;
output Iout2_d_d29_d0 ;
wire Iin_d_d29_d1 ;
output Iout1_d_d13_d0 ;
output Iout2_d_d28_d1 ;
wire Iin_d_d25_d0 ;
output Iout1_d_d28_d1 ;
output Iout1_d_d10_d0 ;
wire Iin_d_d26_d0 ;
output Iout2_d_d8_d1 ;
output Iout2_d_d2_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d27_d1 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d25_d1 ;
output Iout1_d_d6_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d22_d1 ;
output Iout2_d_d24_d1 ;
wire Iin_d_d3_d1 ;
output Iout2_d_d5_d1 ;
wire Iin_d_d6_d1 ;
output Iout2_d_d5_d0 ;
output Iout2_d_d13_d0 ;
output Iout1_d_d7_d1 ;
output Iout1_d_d25_d0 ;
wire Iout2_a ;
wire Iin_d_d26_d1 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d29_d0 ;
output Iout2_d_d11_d1 ;
output Iout2_d_d3_d0 ;
output Iout1_d_d15_d0 ;
wire Iout2_v ;
output Iout2_d_d27_d1 ;
output Iout2_d_d6_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d18_d0 ;
output Iout2_d_d4_d0 ;
output Iout2_d_d14_d0 ;
output Iout1_d_d18_d1 ;
wire Iout_en_buf_out0 ;
wire Iin_d_d30_d0 ;
output Iout1_d_d25_d1 ;
output Iout1_d_d0_d1 ;
output Iout1_d_d29_d1 ;
output Iout1_d_d21_d1 ;
output Iout2_d_d12_d1 ;
output Iout2_d_d23_d0 ;
wire _out1_a_B ;
wire Iin_d_d12_d0 ;
output Iout1_d_d16_d0 ;
output Iout1_d_d1_d0 ;
output Iout2_d_d4_d1 ;
output Iout2_d_d26_d1 ;
output Iout2_d_d10_d0 ;
output Iout1_d_d20_d1 ;
output Iout1_d_d4_d1 ;
output Iout2_d_d30_d0 ;
wire Iin_d_d17_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

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test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4/netlist/verilog.v

@ -135,144 +135,144 @@ module tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4(Iin_d_d0_d0 , Iin_d_d
input cond;
// -- signals ---
output Iout_d_d1_d1 ;
wire Iin_d_d9_d1 ;
output Iin_a ;
wire Iin_d_d7_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d1_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d19_d1 ;
output Iout_d_d29_d1 ;
wire Iout_a ;
output Iout_d_d13_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d15_d1 ;
wire _in_vX ;
wire _drop ;
wire Iin_d_d3_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d15_d1 ;
output Iout_d_d19_d0 ;
wire cond;
wire Iin_d_d14_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d4_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d14_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d28_d1 ;
wire Ior2_b ;
output Iout_d_d14_d0 ;
output Iout_d_d3_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d31_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d12_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d0_d1 ;
wire Iand_f31_b ;
output Iout_d_d0_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d22_d0 ;
wire Ivt_out ;
output Iout_d_d4_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d13_d0 ;
wire Iin_d_d6_d1 ;
output Iout_d_d7_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d31_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d28_d0 ;
wire Iin_d_d31_d1 ;
wire Ior2_y ;
output Iout_d_d12_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d31_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d20_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d17_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d23_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d21_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d11_d1 ;
wire Iin_d_d18_d1 ;
output Iout_d_d20_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d25_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d30_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d24_d0 ;
output Iin_v ;
wire Iin_d_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d_d26_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d20_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d17_d0 ;
wire Iin_d_d20_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d7_d1 ;
wire Ior2_b ;
output Iout_d_d2_d0 ;
output Iout_d_d22_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d14_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d27_d1 ;
wire Ior2_y ;
wire Iin_d_d24_d1 ;
wire Iin_d_d16_d0 ;
output Iin_a ;
wire Iout_a ;
wire Iin_d_d12_d1 ;
output Iout_d_d20_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d_d8_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d2_d1 ;
wire Ivt_out ;
output Iout_d_d30_d1 ;
output Iout_d_d1_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d30_d0 ;
wire _drop ;
wire Iin_d_d1_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d24_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d28_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d23_d0 ;
wire Iin_d_d22_d1 ;
output Iout_d_d3_d0 ;
wire Iin_d_d15_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d18_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d27_d1 ;
output Iout_d_d25_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d12_d0 ;
output Iin_v ;
output Iout_d_d23_d1 ;
wire Iin_d_d25_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d28_d0 ;
output Iout_d_d11_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d21_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d16_d0 ;
output Iout_d_d26_d0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d25_d0 ;
output Iout_d_d4_d1 ;
wire Iin_d_d15_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d31_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d18_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d13_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d8_d1 ;
output Iout_d_d15_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d31_d0 ;
wire cond;
wire Iin_d_d21_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d25_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d14_d1 ;
wire Iin_d_d31_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d17_d1 ;
output Iout_d_d10_d1 ;
wire Iand_f31_b ;
output Iout_d_d31_d0 ;
output Iout_d_d5_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d10_d1 ;
output Iout_d_d26_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d8_d0 ;
wire _in_vX ;
output Iout_d_d6_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d29_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d16_d1 ;
// --- instances
BUF_X4 Iin_v_buf (.y(_in_vX), .a(Ivt_out ), .vdd(vdd), .vss(vss));

26
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4/netlist/verilog.v

@ -16,25 +16,25 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4(Iin0 , Iin1 , Iin2 ,
input Isupply_vss ;
// -- signals ---
wire Iin5 ;
wire Isupply_vss ;
output Iout_d2_d1 ;
wire Iin4 ;
output Iout_d0_d0 ;
wire I_inX4 ;
wire Iin1 ;
wire I_inX1 ;
output Iout_d1_d1 ;
wire I_inX0 ;
output Iout_d0_d1 ;
wire Iin2 ;
wire I_inX3 ;
wire Iin3 ;
output Iout_d1_d0 ;
wire I_inX1 ;
output Iout_d2_d0 ;
wire Iin0 ;
wire I_inX2 ;
output Iout_d2_d1 ;
output Iout_d1_d0 ;
wire Iin3 ;
wire Iin2 ;
wire Isupply_vss ;
wire I_inX5 ;
output Iout_d0_d0 ;
wire I_inX0 ;
output Iout_d1_d1 ;
wire I_inX2 ;
wire Iin5 ;
wire I_inX4 ;
output Iout_d0_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (Isupply_vss ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));

70
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4/netlist/verilog.v

@ -27,45 +27,45 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4(Iin0 , Iin1 , Iin2
input Isupply_vss ;
// -- signals ---
output Iout_d3_d0 ;
output Iout_d2_d1 ;
wire Iin12 ;
wire I_inX13 ;
wire Iin13 ;
wire Iin8 ;
wire Iin2 ;
output Iout_d3_d1 ;
wire Iin14 ;
wire I_inX12 ;
wire I_inX2 ;
wire Iin11 ;
wire I_inX5 ;
wire Iin4 ;
wire I_inX3 ;
wire Iin0 ;
output Iout_d0_d0 ;
output Iout_d1_d1 ;
wire I_inX0 ;
wire I_inX14 ;
wire Isupply_vss ;
wire Iin3 ;
wire I_inX4 ;
output Iout_d2_d0 ;
output Iout_d0_d1 ;
wire I_inX1 ;
wire I_inX6 ;
wire Iin10 ;
wire Iin6 ;
wire Iin1 ;
wire I_inX10 ;
output Iout_d1_d0 ;
wire Iin7 ;
wire I_inX3 ;
wire Iin13 ;
wire Iin12 ;
wire Iin11 ;
wire I_inX8 ;
output Iout_d2_d1 ;
output Iout_d1_d0 ;
wire I_inX12 ;
wire I_inX13 ;
output Iout_d2_d0 ;
wire I_inX2 ;
wire Iin6 ;
wire I_inX5 ;
output Iout_d0_d1 ;
wire Iin8 ;
output Iout_d0_d0 ;
wire Iin10 ;
wire Iin3 ;
wire I_inX0 ;
wire I_inX10 ;
wire I_inX9 ;
wire Iin1 ;
wire I_inX4 ;
wire Iin9 ;
wire I_inX14 ;
wire I_inX6 ;
wire I_inX7 ;
wire Iin5 ;
wire I_inX8 ;
wire Iin4 ;
wire Iin14 ;
wire Isupply_vss ;
wire Iin0 ;
output Iout_d3_d1 ;
wire I_inX11 ;
wire Iin9 ;
wire I_inX9 ;
output Iout_d3_d0 ;
output Iout_d1_d1 ;
wire Iin2 ;
wire I_inX1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (I_inX7 ), .Iin4 (I_inX9 ), .Iin5 (I_inX11 ), .Iin6 (I_inX13 ), .Iin7 (Isupply_vss ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));

330
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4/netlist/verilog.v

@ -121,183 +121,185 @@ module tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4(Isynapses0_d_d0 , I
input Ineuron_a ;
// -- signals ---
wire Isynapses53_d_d0 ;
output Isynapses4_a ;
output Isynapses39_a ;
output Isynapses29_a ;
wire Isynapses24_d_d0 ;
output Isynapses18_a ;
wire Isynapses12_d_d0 ;
output Isynapses12_a ;
wire Isynapses51_d_d0 ;
output Isynapses48_a ;
wire Isynapses31_d_d0 ;
wire Isynapses13_d_d0 ;
wire Isynapses42_d_d0 ;
output Isynapses37_a ;
wire Isynapses36_d_d0 ;
output Isynapses35_a ;
output Isynapses26_a ;
output Isynapses57_a ;
output Isynapses50_a ;
output Isynapses30_a ;
wire Isynapses27_d_d0 ;
wire Isynapses23_d_d0 ;
wire Ineuron_a ;
wire Isynapses57_d_d0 ;
output Isynapses25_a ;
output Isynapses22_a ;
wire Isynapses19_d_d0 ;
wire Isynapses33_d_d0 ;
wire Isynapses32_d_d0 ;
output Isynapses31_a ;
output Isynapses19_a ;
wire Isynapses15_d_d0 ;
output Isynapses9_a ;
wire Isynapses37_d_d0 ;
output Isynapses19_a ;
wire Isynapses18_d_d0 ;
wire Isynapses14_d_d0 ;
wire Isynapses3_d_d0 ;
output Isynapses56_a ;
output Isynapses34_a ;
output Isynapses28_a ;
wire Isynapses45_d_d0 ;
wire Isynapses9_d_d0 ;
output Isynapses53_a ;
output Isynapses47_a ;
wire Isynapses28_d_d0 ;
output Isynapses14_a ;
output Isynapses1_a ;
wire Isynapses0_d_d0 ;
wire Isynapses56_d_d0 ;
output Isynapses54_a ;
output Isynapses42_a ;
wire Isynapses38_d_d0 ;
output Isynapses33_a ;
output Isynapses24_a ;
wire Isynapses8_d_d0 ;
wire Isynapses2_d_d0 ;
output Isynapses55_a ;
output Isynapses52_a ;
output Isynapses40_a ;
wire Isynapses34_d_d0 ;
wire Isynapses17_d_d0 ;
output Isynapses17_a ;
output Isynapses0_a ;
output Isynapses51_a ;
wire Isynapses39_d_d0 ;
wire Isynapses16_d_d0 ;
output Isynapses8_a ;
output Isynapses2_a ;
wire Isynapses55_d_d0 ;
wire Isynapses43_d_d0 ;
wire Isynapses30_d_d0 ;
wire Isynapses10_d_d0 ;
wire Isynapses49_d_d0 ;
output Isynapses44_a ;
output Isynapses38_a ;
wire Isynapses5_d_d0 ;
wire Isynapses46_d_d0 ;
wire Isynapses21_d_d0 ;
output Isynapses13_a ;
wire Isynapses11_d_d0 ;
wire Isynapses40_d_d0 ;
output Isynapses31_a ;
output Ineuron_d_d0 ;
wire Isynapses52_d_d0 ;
output Isynapses20_a ;
output Isynapses32_a ;
wire Isynapses20_d_d0 ;
wire Isynapses7_d_d0 ;
output Isynapses55_a ;
wire Isynapses8_d_d0 ;
output Isynapses6_a ;
wire Isynapses50_d_d0 ;
output Isynapses11_a ;
wire Isynapses44_d_d0 ;
output Isynapses27_a ;
output Isynapses45_a ;
wire Isynapses29_d_d0 ;
wire Isynapses6_d_d0 ;
output Isynapses5_a ;
output Isynapses3_a ;
wire Isynapses0_d_d0 ;
wire Isynapses23_d_d0 ;
output Isynapses12_a ;
output Ineuron_d_d0 ;
wire Isynapses48_d_d0 ;
wire Isynapses47_d_d0 ;
wire Isynapses41_d_d0 ;
output Isynapses29_a ;
wire Isynapses19_d_d0 ;
output Isynapses16_a ;
output Isynapses46_a ;
output Isynapses23_a ;
wire Isynapses22_d_d0 ;
wire Isynapses4_d_d0 ;
output Isynapses49_a ;
wire Isynapses32_d_d0 ;
wire Isynapses25_d_d0 ;
output Isynapses10_a ;
output Isynapses7_a ;
wire Isynapses53_d_d0 ;
output Isynapses44_a ;
output Isynapses41_a ;
wire Isynapses29_d_d0 ;
wire Isynapses5_d_d0 ;
output Isynapses52_a ;
output Isynapses37_a ;
output Isynapses36_a ;
output Isynapses15_a ;
output Isynapses43_a ;
wire Isynapses33_d_d0 ;
output Isynapses21_a ;
wire Isynapses1_d_d0 ;
wire Inrn_ack_buf_y ;
wire Isynapses50_d_d0 ;
wire Isynapses46_d_d0 ;
wire Isynapses41_d_d0 ;
wire Isynapses37_d_d0 ;
wire Isynapses56_d_d0 ;
wire Isynapses27_d_d0 ;
output Isynapses5_a ;
output Isynapses28_a ;
output Isynapses27_a ;
wire Isynapses4_d_d0 ;
wire Isynapses57_d_d0 ;
wire Isynapses47_d_d0 ;
output Isynapses14_a ;
wire Isynapses18_d_d0 ;
output Isynapses11_a ;
wire Isynapses10_d_d0 ;
output Isynapses53_a ;
wire Isynapses52_d_d0 ;
output Isynapses22_a ;
output Isynapses10_a ;
output Isynapses50_a ;
output Isynapses39_a ;
wire Isynapses30_d_d0 ;
output Isynapses26_a ;
output Isynapses18_a ;
wire Isynapses54_d_d0 ;
output Isynapses54_a ;
output Isynapses48_a ;
wire Isynapses40_d_d0 ;
wire Isynapses36_d_d0 ;
wire Isynapses22_d_d0 ;
output Isynapses45_a ;
wire Isynapses34_d_d0 ;
output Isynapses17_a ;
wire Isynapses6_d_d0 ;
output Isynapses34_a ;
wire Isynapses1_d_d0 ;
output Isynapses15_a ;
wire Isynapses49_d_d0 ;
wire Isynapses43_d_d0 ;
output Isynapses35_a ;
wire Isynapses31_d_d0 ;
output Isynapses8_a ;
output Isynapses7_a ;
wire Isynapses51_d_d0 ;
output Isynapses49_a ;
output Isynapses42_a ;
output Isynapses23_a ;
wire Isynapses3_d_d0 ;
wire Isynapses35_d_d0 ;
wire Isynapses7_d_d0 ;
output Isynapses3_a ;
wire Isynapses39_d_d0 ;
output Isynapses32_a ;
output Isynapses30_a ;
wire Isynapses12_d_d0 ;
wire Ineuron_a ;
output Isynapses56_a ;
wire Isynapses45_d_d0 ;
output Isynapses40_a ;
output Isynapses33_a ;
wire Isynapses28_d_d0 ;
wire Isynapses25_d_d0 ;
output Isynapses24_a ;
wire Isynapses21_d_d0 ;
wire Isynapses24_d_d0 ;
wire Isynapses17_d_d0 ;
wire Isynapses38_d_d0 ;
wire Isynapses14_d_d0 ;
output Isynapses1_a ;
output Isynapses0_a ;
output Isynapses57_a ;
output Isynapses51_a ;
output Isynapses47_a ;
wire Isynapses44_d_d0 ;
wire Isynapses26_d_d0 ;
output Isynapses20_a ;
wire Isynapses16_d_d0 ;
output Isynapses13_a ;
output Isynapses4_a ;
wire Isynapses55_d_d0 ;
output Isynapses46_a ;
wire Isynapses13_d_d0 ;
wire Isynapses11_d_d0 ;
wire Isynapses42_d_d0 ;
output Isynapses38_a ;
wire Isynapses2_d_d0 ;
output Isynapses43_a ;
output Isynapses25_a ;
wire Isynapses20_d_d0 ;
wire Isynapses9_d_d0 ;
// --- instances
AND2_X1 Iands0 (.y(Isynapses0_a ), .a(Ineuron_a ), .b(Isynapses0_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands1 (.y(Isynapses1_a ), .a(Ineuron_a ), .b(Isynapses1_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands2 (.y(Isynapses2_a ), .a(Ineuron_a ), .b(Isynapses2_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands3 (.y(Isynapses3_a ), .a(Ineuron_a ), .b(Isynapses3_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands4 (.y(Isynapses4_a ), .a(Ineuron_a ), .b(Isynapses4_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands5 (.y(Isynapses5_a ), .a(Ineuron_a ), .b(Isynapses5_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands6 (.y(Isynapses6_a ), .a(Ineuron_a ), .b(Isynapses6_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands7 (.y(Isynapses7_a ), .a(Ineuron_a ), .b(Isynapses7_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands8 (.y(Isynapses8_a ), .a(Ineuron_a ), .b(Isynapses8_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands9 (.y(Isynapses9_a ), .a(Ineuron_a ), .b(Isynapses9_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands10 (.y(Isynapses10_a ), .a(Ineuron_a ), .b(Isynapses10_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands11 (.y(Isynapses11_a ), .a(Ineuron_a ), .b(Isynapses11_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands12 (.y(Isynapses12_a ), .a(Ineuron_a ), .b(Isynapses12_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands13 (.y(Isynapses13_a ), .a(Ineuron_a ), .b(Isynapses13_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands14 (.y(Isynapses14_a ), .a(Ineuron_a ), .b(Isynapses14_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands15 (.y(Isynapses15_a ), .a(Ineuron_a ), .b(Isynapses15_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands16 (.y(Isynapses16_a ), .a(Ineuron_a ), .b(Isynapses16_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands17 (.y(Isynapses17_a ), .a(Ineuron_a ), .b(Isynapses17_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands18 (.y(Isynapses18_a ), .a(Ineuron_a ), .b(Isynapses18_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands19 (.y(Isynapses19_a ), .a(Ineuron_a ), .b(Isynapses19_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands20 (.y(Isynapses20_a ), .a(Ineuron_a ), .b(Isynapses20_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands21 (.y(Isynapses21_a ), .a(Ineuron_a ), .b(Isynapses21_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands22 (.y(Isynapses22_a ), .a(Ineuron_a ), .b(Isynapses22_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands23 (.y(Isynapses23_a ), .a(Ineuron_a ), .b(Isynapses23_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands24 (.y(Isynapses24_a ), .a(Ineuron_a ), .b(Isynapses24_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands25 (.y(Isynapses25_a ), .a(Ineuron_a ), .b(Isynapses25_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands26 (.y(Isynapses26_a ), .a(Ineuron_a ), .b(Isynapses26_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands27 (.y(Isynapses27_a ), .a(Ineuron_a ), .b(Isynapses27_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands28 (.y(Isynapses28_a ), .a(Ineuron_a ), .b(Isynapses28_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands29 (.y(Isynapses29_a ), .a(Ineuron_a ), .b(Isynapses29_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands30 (.y(Isynapses30_a ), .a(Ineuron_a ), .b(Isynapses30_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands31 (.y(Isynapses31_a ), .a(Ineuron_a ), .b(Isynapses31_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands32 (.y(Isynapses32_a ), .a(Ineuron_a ), .b(Isynapses32_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands33 (.y(Isynapses33_a ), .a(Ineuron_a ), .b(Isynapses33_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands34 (.y(Isynapses34_a ), .a(Ineuron_a ), .b(Isynapses34_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands35 (.y(Isynapses35_a ), .a(Ineuron_a ), .b(Isynapses35_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands36 (.y(Isynapses36_a ), .a(Ineuron_a ), .b(Isynapses36_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands37 (.y(Isynapses37_a ), .a(Ineuron_a ), .b(Isynapses37_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands38 (.y(Isynapses38_a ), .a(Ineuron_a ), .b(Isynapses38_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands39 (.y(Isynapses39_a ), .a(Ineuron_a ), .b(Isynapses39_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands40 (.y(Isynapses40_a ), .a(Ineuron_a ), .b(Isynapses40_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands41 (.y(Isynapses41_a ), .a(Ineuron_a ), .b(Isynapses41_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands42 (.y(Isynapses42_a ), .a(Ineuron_a ), .b(Isynapses42_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands43 (.y(Isynapses43_a ), .a(Ineuron_a ), .b(Isynapses43_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands44 (.y(Isynapses44_a ), .a(Ineuron_a ), .b(Isynapses44_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands45 (.y(Isynapses45_a ), .a(Ineuron_a ), .b(Isynapses45_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands46 (.y(Isynapses46_a ), .a(Ineuron_a ), .b(Isynapses46_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands47 (.y(Isynapses47_a ), .a(Ineuron_a ), .b(Isynapses47_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands48 (.y(Isynapses48_a ), .a(Ineuron_a ), .b(Isynapses48_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands49 (.y(Isynapses49_a ), .a(Ineuron_a ), .b(Isynapses49_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands50 (.y(Isynapses50_a ), .a(Ineuron_a ), .b(Isynapses50_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands51 (.y(Isynapses51_a ), .a(Ineuron_a ), .b(Isynapses51_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands52 (.y(Isynapses52_a ), .a(Ineuron_a ), .b(Isynapses52_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands53 (.y(Isynapses53_a ), .a(Ineuron_a ), .b(Isynapses53_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands54 (.y(Isynapses54_a ), .a(Ineuron_a ), .b(Isynapses54_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands55 (.y(Isynapses55_a ), .a(Ineuron_a ), .b(Isynapses55_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands56 (.y(Isynapses56_a ), .a(Ineuron_a ), .b(Isynapses56_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands57 (.y(Isynapses57_a ), .a(Ineuron_a ), .b(Isynapses57_d_d0 ), .vdd(vdd), .vss(vss));
BUF_X12 Inrn_ack_buf (.y(Inrn_ack_buf_y ), .a(Ineuron_a ), .vdd(vdd), .vss(vss));
AND2_X1 Iands0 (.y(Isynapses0_a ), .a(Inrn_ack_buf_y ), .b(Isynapses0_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands1 (.y(Isynapses1_a ), .a(Inrn_ack_buf_y ), .b(Isynapses1_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands2 (.y(Isynapses2_a ), .a(Inrn_ack_buf_y ), .b(Isynapses2_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands3 (.y(Isynapses3_a ), .a(Inrn_ack_buf_y ), .b(Isynapses3_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands4 (.y(Isynapses4_a ), .a(Inrn_ack_buf_y ), .b(Isynapses4_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands5 (.y(Isynapses5_a ), .a(Inrn_ack_buf_y ), .b(Isynapses5_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands6 (.y(Isynapses6_a ), .a(Inrn_ack_buf_y ), .b(Isynapses6_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands7 (.y(Isynapses7_a ), .a(Inrn_ack_buf_y ), .b(Isynapses7_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands8 (.y(Isynapses8_a ), .a(Inrn_ack_buf_y ), .b(Isynapses8_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands9 (.y(Isynapses9_a ), .a(Inrn_ack_buf_y ), .b(Isynapses9_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands10 (.y(Isynapses10_a ), .a(Inrn_ack_buf_y ), .b(Isynapses10_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands11 (.y(Isynapses11_a ), .a(Inrn_ack_buf_y ), .b(Isynapses11_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands12 (.y(Isynapses12_a ), .a(Inrn_ack_buf_y ), .b(Isynapses12_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands13 (.y(Isynapses13_a ), .a(Inrn_ack_buf_y ), .b(Isynapses13_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands14 (.y(Isynapses14_a ), .a(Inrn_ack_buf_y ), .b(Isynapses14_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands15 (.y(Isynapses15_a ), .a(Inrn_ack_buf_y ), .b(Isynapses15_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands16 (.y(Isynapses16_a ), .a(Inrn_ack_buf_y ), .b(Isynapses16_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands17 (.y(Isynapses17_a ), .a(Inrn_ack_buf_y ), .b(Isynapses17_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands18 (.y(Isynapses18_a ), .a(Inrn_ack_buf_y ), .b(Isynapses18_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands19 (.y(Isynapses19_a ), .a(Inrn_ack_buf_y ), .b(Isynapses19_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands20 (.y(Isynapses20_a ), .a(Inrn_ack_buf_y ), .b(Isynapses20_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands21 (.y(Isynapses21_a ), .a(Inrn_ack_buf_y ), .b(Isynapses21_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands22 (.y(Isynapses22_a ), .a(Inrn_ack_buf_y ), .b(Isynapses22_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands23 (.y(Isynapses23_a ), .a(Inrn_ack_buf_y ), .b(Isynapses23_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands24 (.y(Isynapses24_a ), .a(Inrn_ack_buf_y ), .b(Isynapses24_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands25 (.y(Isynapses25_a ), .a(Inrn_ack_buf_y ), .b(Isynapses25_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands26 (.y(Isynapses26_a ), .a(Inrn_ack_buf_y ), .b(Isynapses26_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands27 (.y(Isynapses27_a ), .a(Inrn_ack_buf_y ), .b(Isynapses27_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands28 (.y(Isynapses28_a ), .a(Inrn_ack_buf_y ), .b(Isynapses28_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands29 (.y(Isynapses29_a ), .a(Inrn_ack_buf_y ), .b(Isynapses29_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands30 (.y(Isynapses30_a ), .a(Inrn_ack_buf_y ), .b(Isynapses30_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands31 (.y(Isynapses31_a ), .a(Inrn_ack_buf_y ), .b(Isynapses31_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands32 (.y(Isynapses32_a ), .a(Inrn_ack_buf_y ), .b(Isynapses32_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands33 (.y(Isynapses33_a ), .a(Inrn_ack_buf_y ), .b(Isynapses33_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands34 (.y(Isynapses34_a ), .a(Inrn_ack_buf_y ), .b(Isynapses34_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands35 (.y(Isynapses35_a ), .a(Inrn_ack_buf_y ), .b(Isynapses35_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands36 (.y(Isynapses36_a ), .a(Inrn_ack_buf_y ), .b(Isynapses36_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands37 (.y(Isynapses37_a ), .a(Inrn_ack_buf_y ), .b(Isynapses37_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands38 (.y(Isynapses38_a ), .a(Inrn_ack_buf_y ), .b(Isynapses38_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands39 (.y(Isynapses39_a ), .a(Inrn_ack_buf_y ), .b(Isynapses39_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands40 (.y(Isynapses40_a ), .a(Inrn_ack_buf_y ), .b(Isynapses40_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands41 (.y(Isynapses41_a ), .a(Inrn_ack_buf_y ), .b(Isynapses41_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands42 (.y(Isynapses42_a ), .a(Inrn_ack_buf_y ), .b(Isynapses42_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands43 (.y(Isynapses43_a ), .a(Inrn_ack_buf_y ), .b(Isynapses43_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands44 (.y(Isynapses44_a ), .a(Inrn_ack_buf_y ), .b(Isynapses44_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands45 (.y(Isynapses45_a ), .a(Inrn_ack_buf_y ), .b(Isynapses45_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands46 (.y(Isynapses46_a ), .a(Inrn_ack_buf_y ), .b(Isynapses46_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands47 (.y(Isynapses47_a ), .a(Inrn_ack_buf_y ), .b(Isynapses47_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands48 (.y(Isynapses48_a ), .a(Inrn_ack_buf_y ), .b(Isynapses48_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands49 (.y(Isynapses49_a ), .a(Inrn_ack_buf_y ), .b(Isynapses49_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands50 (.y(Isynapses50_a ), .a(Inrn_ack_buf_y ), .b(Isynapses50_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands51 (.y(Isynapses51_a ), .a(Inrn_ack_buf_y ), .b(Isynapses51_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands52 (.y(Isynapses52_a ), .a(Inrn_ack_buf_y ), .b(Isynapses52_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands53 (.y(Isynapses53_a ), .a(Inrn_ack_buf_y ), .b(Isynapses53_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands54 (.y(Isynapses54_a ), .a(Inrn_ack_buf_y ), .b(Isynapses54_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands55 (.y(Isynapses55_a ), .a(Inrn_ack_buf_y ), .b(Isynapses55_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands56 (.y(Isynapses56_a ), .a(Inrn_ack_buf_y ), .b(Isynapses56_d_d0 ), .vdd(vdd), .vss(vss));
AND2_X1 Iands57 (.y(Isynapses57_a ), .a(Inrn_ack_buf_y ), .b(Isynapses57_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_358_4 I_ortree (.Iin0 (Isynapses0_d_d0 ), .Iin1 (Isynapses1_d_d0 ), .Iin2 (Isynapses2_d_d0 ), .Iin3 (Isynapses3_d_d0 ), .Iin4 (Isynapses4_d_d0 ), .Iin5 (Isynapses5_d_d0 ), .Iin6 (Isynapses6_d_d0 ), .Iin7 (Isynapses7_d_d0 ), .Iin8 (Isynapses8_d_d0 ), .Iin9 (Isynapses9_d_d0 ), .Iin10 (Isynapses10_d_d0 ), .Iin11 (Isynapses11_d_d0 ), .Iin12 (Isynapses12_d_d0 ), .Iin13 (Isynapses13_d_d0 ), .Iin14 (Isynapses14_d_d0 ), .Iin15 (Isynapses15_d_d0 ), .Iin16 (Isynapses16_d_d0 ), .Iin17 (Isynapses17_d_d0 ), .Iin18 (Isynapses18_d_d0 ), .Iin19 (Isynapses19_d_d0 ), .Iin20 (Isynapses20_d_d0 ), .Iin21 (Isynapses21_d_d0 ), .Iin22 (Isynapses22_d_d0 ), .Iin23 (Isynapses23_d_d0 ), .Iin24 (Isynapses24_d_d0 ), .Iin25 (Isynapses25_d_d0 ), .Iin26 (Isynapses26_d_d0 ), .Iin27 (Isynapses27_d_d0 ), .Iin28 (Isynapses28_d_d0 ), .Iin29 (Isynapses29_d_d0 ), .Iin30 (Isynapses30_d_d0 ), .Iin31 (Isynapses31_d_d0 ), .Iin32 (Isynapses32_d_d0 ), .Iin33 (Isynapses33_d_d0 ), .Iin34 (Isynapses34_d_d0 ), .Iin35 (Isynapses35_d_d0 ), .Iin36 (Isynapses36_d_d0 ), .Iin37 (Isynapses37_d_d0 ), .Iin38 (Isynapses38_d_d0 ), .Iin39 (Isynapses39_d_d0 ), .Iin40 (Isynapses40_d_d0 ), .Iin41 (Isynapses41_d_d0 ), .Iin42 (Isynapses42_d_d0 ), .Iin43 (Isynapses43_d_d0 ), .Iin44 (Isynapses44_d_d0 ), .Iin45 (Isynapses45_d_d0 ), .Iin46 (Isynapses46_d_d0 ), .Iin47 (Isynapses47_d_d0 ), .Iin48 (Isynapses48_d_d0 ), .Iin49 (Isynapses49_d_d0 ), .Iin50 (Isynapses50_d_d0 ), .Iin51 (Isynapses51_d_d0 ), .Iin52 (Isynapses52_d_d0 ), .Iin53 (Isynapses53_d_d0 ), .Iin54 (Isynapses54_d_d0 ), .Iin55 (Isynapses55_d_d0 ), .Iin56 (Isynapses56_d_d0 ), .Iin57 (Isynapses57_d_d0 ), .out(Ineuron_d_d0 ), .vdd(vdd), .vss(vss));
endmodule

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test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dummy__neuron__core_358_790_715_4/netlist/verilog.v

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verilog.v

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test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4/netlist/verilog.v

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module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_70_4(Iinx0_d_d0 , Iinx0_a , Iinx1_d_d0 , Iinx1_a , Iinx2_d_d0 , Iinx2_a , Iinx3_d_d0 , Iinx3_a , Iinx4_d_d0 , Iinx4_a , Iinx5_d_d0 , Iinx5_a , Iinx6_d_d0 , Iinx6_a , Iinx7_d_d0 , Iinx7_a , Iinx8_d_d0 , Iinx8_a , Iinx9_d_d0 , Iinx9_a , Iinx10_d_d0 , Iinx10_a , Iinx11_d_d0 , Iinx11_a , Iinx12_d_d0 , Iinx12_a , Iinx13_d_d0 , Iinx13_a , Iinx14_d_d0 , Iinx14_a , Iiny0_d_d0 , Iiny0_a , Iiny1_d_d0 , Iiny1_a , Iiny2_d_d0 , Iiny2_a , Iiny3_d_d0 , Iiny3_a , Iiny4_d_d0 , Iiny4_a , Iiny5_d_d0 , Iiny5_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , Ito_pd_x0_d_d0 , Ito_pd_x0_a , Ito_pd_x1_d_d0 , Ito_pd_x1_a , Ito_pd_x2_d_d0 , Ito_pd_x2_a , Ito_pd_x3_d_d0 , Ito_pd_x3_a , Ito_pd_x4_d_d0 , Ito_pd_x4_a , Ito_pd_x5_d_d0 , Ito_pd_x5_a , Ito_pd_x6_d_d0 , Ito_pd_x6_a , Ito_pd_x7_d_d0 , Ito_pd_x7_a , Ito_pd_x8_d_d0 , Ito_pd_x8_a , Ito_pd_x9_d_d0 , Ito_pd_x9_a , Ito_pd_x10_d_d0 , Ito_pd_x10_a , Ito_pd_x11_d_d0 , Ito_pd_x11_a , Ito_pd_x12_d_d0 , Ito_pd_x12_a , Ito_pd_x13_d_d0 , Ito_pd_x13_a , Ito_pd_x14_d_d0 , Ito_pd_x14_a , Ito_pd_y0_d_d0 , Ito_pd_y0_a , Ito_pd_y1_d_d0 , Ito_pd_y1_a , Ito_pd_y2_d_d0 , Ito_pd_y2_a , Ito_pd_y3_d_d0 , Ito_pd_y3_a , Ito_pd_y4_d_d0 , Ito_pd_y4_a , Ito_pd_y5_d_d0 , Ito_pd_y5_a , Isupply_vss , reset_B, vdd, vss);
input vdd;
input vss;
input Iinx0_d_d0 ;
input Iinx1_d_d0 ;
input Iinx2_d_d0 ;
input Iinx3_d_d0 ;
input Iinx4_d_d0 ;
input Iinx5_d_d0 ;
input Iinx6_d_d0 ;
input Iinx7_d_d0 ;
input Iinx8_d_d0 ;
input Iinx9_d_d0 ;
input Iinx10_d_d0 ;
input Iinx11_d_d0 ;
input Iinx12_d_d0 ;
input Iinx13_d_d0 ;
input Iinx14_d_d0 ;
input Iiny0_d_d0 ;
input Iiny1_d_d0 ;
input Iiny2_d_d0 ;
input Iiny3_d_d0 ;
input Iiny4_d_d0 ;
input Iiny5_d_d0 ;
input Iout_a ;
input Iout_v ;
input Ito_pd_x0_a ;
input Ito_pd_x1_a ;
input Ito_pd_x2_a ;
input Ito_pd_x3_a ;
input Ito_pd_x4_a ;
input Ito_pd_x5_a ;
input Ito_pd_x6_a ;
input Ito_pd_x7_a ;
input Ito_pd_x8_a ;
input Ito_pd_x9_a ;
input Ito_pd_x10_a ;
input Ito_pd_x11_a ;
input Ito_pd_x12_a ;
input Ito_pd_x13_a ;
input Ito_pd_x14_a ;
input Ito_pd_y0_a ;
input Ito_pd_y1_a ;
input Ito_pd_y2_a ;
input Ito_pd_y3_a ;
input Ito_pd_y4_a ;
input Ito_pd_y5_a ;
input Isupply_vss ;
input reset_B;
// -- signals ---
wire Ito_pd_y3_a ;
output Ito_pd_y0_d_d0 ;
wire Iiny2_d_d0 ;
wire Ito_pd_y1_a ;
wire IXenc_out_d1_d0 ;
wire Iinv_buf_a ;
wire Iinx10_d_d0 ;
wire Iinx1_d_d0 ;
output Iiny2_a ;
output Iout_d_d6_d0 ;
output Ito_pd_y3_d_d0 ;
wire Ito_pd_x11_a ;
wire Isupply_vss ;
wire IXenc_out_d2_d1 ;
output Iinx9_a ;
wire Iinx0_d_d0 ;
output Ito_pd_y5_d_d0 ;
wire Iinx4_d_d0 ;
output Ito_pd_y2_d_d0 ;
output Ito_pd_x12_d_d0 ;
output Ito_pd_x11_d_d0 ;
output Ito_pd_x10_d_d0 ;
wire IXenc_out_d3_d1 ;
wire Iinx5_d_d0 ;
wire Ibuf_in_v ;
wire IYenc_out_d2_d0 ;
output Iinx14_a ;
output Iinx12_a ;
wire Iinx2_d_d0 ;
output Iinx5_a ;
output Iiny5_a ;
output Iiny1_a ;
output Iiny0_a ;
output Ito_pd_x3_d_d0 ;
output Iout_d_d3_d1 ;
wire Ito_pd_x7_a ;
output Iinx13_a ;
wire Iout_a ;
output Iout_d_d6_d1 ;
wire Ito_pd_x14_a ;
output Ito_pd_x0_d_d0 ;
wire Iinx9_d_d0 ;
output Iinx0_a ;
output Iout_d_d0_d1 ;
output Ito_pd_y1_d_d0 ;
wire Ito_pd_x12_a ;
wire Ito_pd_x10_a ;
output Iinx8_a ;
wire Ito_pd_y5_a ;
wire Ipd_y5_reset_B ;
wire Iinx11_d_d0 ;
output Ito_pd_x7_d_d0 ;
wire IXenc_out_d0_d0 ;
output Ito_pd_x13_d_d0 ;
wire Ito_pd_x3_a ;
wire _r_y ;
output Iout_d_d3_d0 ;
wire IXenc_out_d2_d0 ;
wire _a_y ;
wire Iinx7_d_d0 ;
output Iinx4_a ;
output Iinx1_a ;
wire Iiny0_d_d0 ;
wire Ito_pd_x9_a ;
wire Ia_x_Cel_c1 ;
output Iout_d_d2_d1 ;
wire IYenc_out_d1_d1 ;
output Iinx7_a ;
output Iinx2_a ;
output Iiny4_a ;
wire IYenc_out_d2_d1 ;
wire Ito_pd_y4_a ;
wire _r_x ;
output Iinx3_a ;
output Iiny3_a ;
output Iout_d_d4_d1 ;
wire IXenc_out_d3_d0 ;
wire Iinx6_d_d0 ;
wire Iiny3_d_d0 ;
wire IYenc_out_d0_d0 ;
wire Ito_pd_y0_a ;
wire _a_x ;
wire Ito_pd_y2_a ;
wire Ito_pd_x0_a ;
wire reset_B;
wire Ito_pd_x5_a ;
wire IXenc_out_d1_d1 ;
wire Iinx14_d_d0 ;
output Iinx11_a ;
output Iinx10_a ;
wire Iinx8_d_d0 ;
output Iout_d_d4_d0 ;
wire Iiny4_d_d0 ;
output Iout_d_d5_d0 ;
wire Ito_pd_x13_a ;
wire Ito_pd_x8_a ;
output Ito_pd_x6_d_d0 ;
output Ito_pd_x2_d_d0 ;
wire Ito_pd_x1_a ;
wire Iinx3_d_d0 ;
wire Iout_v ;
output Iout_d_d5_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d1_d0 ;
output Ito_pd_x9_d_d0 ;
wire Iinx13_d_d0 ;
output Iinx6_a ;
wire Iiny5_d_d0 ;
output Iout_d_d1_d1 ;
output Ito_pd_x14_d_d0 ;
output Ito_pd_x8_d_d0 ;
output Ito_pd_x1_d_d0 ;
wire IXenc_out_d0_d1 ;
wire Iiny1_d_d0 ;
output Iout_d_d0_d0 ;
wire IYenc_out_d1_d0 ;
wire IYenc_out_d0_d1 ;
output Ito_pd_x4_d_d0 ;
wire Ito_pd_x2_a ;
wire Iinx12_d_d0 ;
wire Ito_pd_x4_a ;
wire Ipd_x14_reset_B ;
output Ito_pd_y4_d_d0 ;
wire Ito_pd_x6_a ;
output Ito_pd_x5_d_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbtree_315_4 IXarb (.Iin0_d_d0 (Iinx0_d_d0 ), .Iin0_a (Iinx0_a ), .Iin1_d_d0 (Iinx1_d_d0 ), .Iin1_a (Iinx1_a ), .Iin2_d_d0 (Iinx2_d_d0 ), .Iin2_a (Iinx2_a ), .Iin3_d_d0 (Iinx3_d_d0 ), .Iin3_a (Iinx3_a ), .Iin4_d_d0 (Iinx4_d_d0 ), .Iin4_a (Iinx4_a ), .Iin5_d_d0 (Iinx5_d_d0 ), .Iin5_a (Iinx5_a ), .Iin6_d_d0 (Iinx6_d_d0 ), .Iin6_a (Iinx6_a ), .Iin7_d_d0 (Iinx7_d_d0 ), .Iin7_a (Iinx7_a ), .Iin8_d_d0 (Iinx8_d_d0 ), .Iin8_a (Iinx8_a ), .Iin9_d_d0 (Iinx9_d_d0 ), .Iin9_a (Iinx9_a ), .Iin10_d_d0 (Iinx10_d_d0 ), .Iin10_a (Iinx10_a ), .Iin11_d_d0 (Iinx11_d_d0 ), .Iin11_a (Iinx11_a ), .Iin12_d_d0 (Iinx12_d_d0 ), .Iin12_a (Iinx12_a ), .Iin13_d_d0 (Iinx13_d_d0 ), .Iin13_a (Iinx13_a ), .Iin14_d_d0 (Iinx14_d_d0 ), .Iin14_a (Iinx14_a ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));
INV_X2 Iinv_buf (.y(Ia_x_Cel_c1 ), .a(Iinv_buf_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_pd_x (.in(reset_B), .Iout0 (Ipd_x14_reset_B ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_y_Cel (.y(_a_y), .c1(Ia_x_Cel_c1 ), .c2(_r_y), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4 IXenc (.Iin0 (Iinx0_a ), .Iin1 (Iinx1_a ), .Iin2 (Iinx2_a ), .Iin3 (Iinx3_a ), .Iin4 (Iinx4_a ), .Iin5 (Iinx5_a ), .Iin6 (Iinx6_a ), .Iin7 (Iinx7_a ), .Iin8 (Iinx8_a ), .Iin9 (Iinx9_a ), .Iin10 (Iinx10_a ), .Iin11 (Iinx11_a ), .Iin12 (Iinx12_a ), .Iin13 (Iinx13_a ), .Iin14 (Iinx14_a ), .Iout_d0_d0 (IXenc_out_d0_d0 ), .Iout_d0_d1 (IXenc_out_d0_d1 ), .Iout_d1_d0 (IXenc_out_d1_d0 ), .Iout_d1_d1 (IXenc_out_d1_d1 ), .Iout_d2_d0 (IXenc_out_d2_d0 ), .Iout_d2_d1 (IXenc_out_d2_d1 ), .Iout_d3_d0 (IXenc_out_d3_d0 ), .Iout_d3_d1 (IXenc_out_d3_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x0 (.in(Ito_pd_x0_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x1 (.in(Ito_pd_x1_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x2 (.in(Ito_pd_x2_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x3 (.in(Ito_pd_x3_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x4 (.in(Ito_pd_x4_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x5 (.in(Ito_pd_x5_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x6 (.in(Ito_pd_x6_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x7 (.in(Ito_pd_x7_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x8 (.in(Ito_pd_x8_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x9 (.in(Ito_pd_x9_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x10 (.in(Ito_pd_x10_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x11 (.in(Ito_pd_x11_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x12 (.in(Ito_pd_x12_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x13 (.in(Ito_pd_x13_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x14 (.in(Ito_pd_x14_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y0 (.in(Ito_pd_y0_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y1 (.in(Ito_pd_y1_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y2 (.in(Ito_pd_y2_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y3 (.in(Ito_pd_y3_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y4 (.in(Ito_pd_y4_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y5 (.in(Ito_pd_y5_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ibuf (.Iin_d_d0_d0 (IXenc_out_d0_d0 ), .Iin_d_d0_d1 (IXenc_out_d0_d1 ), .Iin_d_d1_d0 (IXenc_out_d1_d0 ), .Iin_d_d1_d1 (IXenc_out_d1_d1 ), .Iin_d_d2_d0 (IXenc_out_d2_d0 ), .Iin_d_d2_d1 (IXenc_out_d2_d1 ), .Iin_d_d3_d0 (IXenc_out_d3_d0 ), .Iin_d_d3_d1 (IXenc_out_d3_d1 ), .Iin_d_d4_d0 (IYenc_out_d0_d0 ), .Iin_d_d4_d1 (IYenc_out_d0_d1 ), .Iin_d_d5_d0 (IYenc_out_d1_d0 ), .Iin_d_d5_d1 (IYenc_out_d1_d1 ), .Iin_d_d6_d0 (IYenc_out_d2_d0 ), .Iin_d_d6_d1 (IYenc_out_d2_d1 ), .Iin_a (Iinv_buf_a ), .Iin_v (Ibuf_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbtree_36_4 IYarb (.Iin0_d_d0 (Iiny0_d_d0 ), .Iin0_a (Iiny0_a ), .Iin1_d_d0 (Iiny1_d_d0 ), .Iin1_a (Iiny1_a ), .Iin2_d_d0 (Iiny2_d_d0 ), .Iin2_a (Iiny2_a ), .Iin3_d_d0 (Iiny3_d_d0 ), .Iin3_a (Iiny3_a ), .Iin4_d_d0 (Iiny4_d_d0 ), .Iin4_a (Iiny4_a ), .Iin5_d_d0 (Iiny5_d_d0 ), .Iin5_a (Iiny5_a ), .Iout_d_d0 (_r_y), .Iout_a (_a_y), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4 IYenc (.Iin0 (Iiny0_a ), .Iin1 (Iiny1_a ), .Iin2 (Iiny2_a ), .Iin3 (Iiny3_a ), .Iin4 (Iiny4_a ), .Iin5 (Iiny5_a ), .Iout_d0_d0 (IYenc_out_d0_d0 ), .Iout_d0_d1 (IYenc_out_d0_d1 ), .Iout_d1_d0 (IYenc_out_d1_d0 ), .Iout_d1_d1 (IYenc_out_d1_d1 ), .Iout_d2_d0 (IYenc_out_d2_d0 ), .Iout_d2_d1 (IYenc_out_d2_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_x_Cel (.y(_a_x), .c1(Ia_x_Cel_c1 ), .c2(_r_x), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Irsb_pd_y (.in(reset_B), .Iout0 (Ipd_y5_reset_B ), .vdd(vdd), .vss(vss));
endmodule

385
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4/netlist/verilog.v

@ -1,4 +1,4 @@
module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4(Iinx0_d_d0 , Iinx0_a , Iinx1_d_d0 , Iinx1_a , Iinx2_d_d0 , Iinx2_a , Iinx3_d_d0 , Iinx3_a , Iinx4_d_d0 , Iinx4_a , Iinx5_d_d0 , Iinx5_a , Iinx6_d_d0 , Iinx6_a , Iinx7_d_d0 , Iinx7_a , Iinx8_d_d0 , Iinx8_a , Iinx9_d_d0 , Iinx9_a , Iinx10_d_d0 , Iinx10_a , Iinx11_d_d0 , Iinx11_a , Iinx12_d_d0 , Iinx12_a , Iinx13_d_d0 , Iinx13_a , Iinx14_d_d0 , Iinx14_a , Iiny0_d_d0 , Iiny0_a , Iiny1_d_d0 , Iiny1_a , Iiny2_d_d0 , Iiny2_a , Iiny3_d_d0 , Iiny3_a , Iiny4_d_d0 , Iiny4_a , Iiny5_d_d0 , Iiny5_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , Ito_pd_x0_d_d0 , Ito_pd_x0_a , Ito_pd_x1_d_d0 , Ito_pd_x1_a , Ito_pd_x2_d_d0 , Ito_pd_x2_a , Ito_pd_x3_d_d0 , Ito_pd_x3_a , Ito_pd_x4_d_d0 , Ito_pd_x4_a , Ito_pd_x5_d_d0 , Ito_pd_x5_a , Ito_pd_x6_d_d0 , Ito_pd_x6_a , Ito_pd_x7_d_d0 , Ito_pd_x7_a , Ito_pd_x8_d_d0 , Ito_pd_x8_a , Ito_pd_x9_d_d0 , Ito_pd_x9_a , Ito_pd_x10_d_d0 , Ito_pd_x10_a , Ito_pd_x11_d_d0 , Ito_pd_x11_a , Ito_pd_x12_d_d0 , Ito_pd_x12_a , Ito_pd_x13_d_d0 , Ito_pd_x13_a , Ito_pd_x14_d_d0 , Ito_pd_x14_a , Ito_pd_y0_d_d0 , Ito_pd_y0_a , Ito_pd_y1_d_d0 , Ito_pd_y1_a , Ito_pd_y2_d_d0 , Ito_pd_y2_a , Ito_pd_y3_d_d0 , Ito_pd_y3_a , Ito_pd_y4_d_d0 , Ito_pd_y4_a , Ito_pd_y5_d_d0 , Ito_pd_y5_a , Isupply_vss , reset_B, vdd, vss);
module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4(Iinx0_d_d0 , Iinx0_a , Iinx1_d_d0 , Iinx1_a , Iinx2_d_d0 , Iinx2_a , Iinx3_d_d0 , Iinx3_a , Iinx4_d_d0 , Iinx4_a , Iinx5_d_d0 , Iinx5_a , Iinx6_d_d0 , Iinx6_a , Iinx7_d_d0 , Iinx7_a , Iinx8_d_d0 , Iinx8_a , Iinx9_d_d0 , Iinx9_a , Iinx10_d_d0 , Iinx10_a , Iinx11_d_d0 , Iinx11_a , Iinx12_d_d0 , Iinx12_a , Iinx13_d_d0 , Iinx13_a , Iinx14_d_d0 , Iinx14_a , Iiny0_d_d0 , Iiny0_a , Iiny1_d_d0 , Iiny1_a , Iiny2_d_d0 , Iiny2_a , Iiny3_d_d0 , Iiny3_a , Iiny4_d_d0 , Iiny4_a , Iiny5_d_d0 , Iiny5_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , Ito_pd_x0_d_d0 , Ito_pd_x0_a , Ito_pd_x1_d_d0 , Ito_pd_x1_a , Ito_pd_x2_d_d0 , Ito_pd_x2_a , Ito_pd_x3_d_d0 , Ito_pd_x3_a , Ito_pd_x4_d_d0 , Ito_pd_x4_a , Ito_pd_x5_d_d0 , Ito_pd_x5_a , Ito_pd_x6_d_d0 , Ito_pd_x6_a , Ito_pd_x7_d_d0 , Ito_pd_x7_a , Ito_pd_x8_d_d0 , Ito_pd_x8_a , Ito_pd_x9_d_d0 , Ito_pd_x9_a , Ito_pd_x10_d_d0 , Ito_pd_x10_a , Ito_pd_x11_d_d0 , Ito_pd_x11_a , Ito_pd_x12_d_d0 , Ito_pd_x12_a , Ito_pd_x13_d_d0 , Ito_pd_x13_a , Ito_pd_x14_d_d0 , Ito_pd_x14_a , Ito_pd_y0_d_d0 , Ito_pd_y0_a , Ito_pd_y1_d_d0 , Ito_pd_y1_a , Ito_pd_y2_d_d0 , Ito_pd_y2_a , Ito_pd_y3_d_d0 , Ito_pd_y3_a , Ito_pd_y4_d_d0 , Ito_pd_y4_a , Ito_pd_y5_d_d0 , Ito_pd_y5_a , Isupply_vdd , Isupply_vss , reset_B, vdd, vss);
input vdd;
input vss;
input Iinx0_d_d0 ;
@ -101,177 +101,179 @@ module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4(Iinx0_d_d0
input Ito_pd_y4_a ;
input Ito_pd_y5_a ;
input Isupply_vdd ;
input Isupply_vss ;
input reset_B;
// -- signals ---
output Iiny0_a ;
wire Iinv_buf_a ;
wire Idly_x13_out ;
wire Iout_v ;
output Iout_d_d3_d1 ;
output Iout_d_d1_d0 ;
wire Ito_pd_x0_a ;
output Ito_pd_x9_d_d0 ;
wire Idly_x8_in ;
wire Idly_x0_out ;
output Ito_pd_y4_d_d0 ;
wire IXenc_out_d3_d1 ;
wire IYenc_out_d1_d0 ;
wire Iinx0_d_d0 ;
wire _a_x ;
output Iinx8_a ;
output Iinx13_a ;
output Ito_pd_x14_d_d0 ;
output Ito_pd_y2_d_d0 ;
wire IYenc_out_d1_d1 ;
wire Idly_x1_in ;
wire Ipd_x14_reset_B ;
wire Iiny2_d_d0 ;
wire Idly_x2_out ;
output Ito_pd_x5_d_d0 ;
wire Ito_pd_x12_a ;
wire Idly_x14_in ;
output Iinx6_a ;
output Ito_pd_x8_d_d0 ;
wire Iinx6_d_d0 ;
wire Ito_pd_x4_a ;
output Ito_pd_y5_d_d0 ;
wire Iinx11_d_d0 ;
wire Iinx12_d_d0 ;
wire Idly_y1_out ;
output Ito_pd_x6_d_d0 ;
wire Idly_x2_in ;
wire Idly_y3_out ;
wire Iout_a ;
output Iout_d_d0_d1 ;
wire IXenc_out_d0_d1 ;
wire Idly_x5_out ;
wire Ito_pd_x7_a ;
output Iout_d_d5_d0 ;
output Ito_pd_x13_d_d0 ;
wire IYenc_out_d0_d1 ;
wire Idly_x5_in ;
wire Idly_x11_in ;
wire Idly_y2_in ;
output Ito_pd_y0_d_d0 ;
output Iout_d_d4_d0 ;
wire Idly_y4_in ;
wire Ito_pd_x14_a ;
wire Iiny0_d_d0 ;
output Iinx9_a ;
output Ito_pd_x10_d_d0 ;
wire Iiny3_d_d0 ;
wire Idly_x9_out ;
wire Ito_pd_y5_a ;
output Iout_d_d2_d1 ;
output Ito_pd_x7_d_d0 ;
wire Ito_pd_x5_a ;
wire Iinx2_d_d0 ;
output Ito_pd_x2_d_d0 ;
wire Ito_pd_x2_a ;
output Iinx13_a ;
wire IXenc_out_d0_d1 ;
wire Ito_pd_y1_a ;
wire Iinx1_d_d0 ;
output Iout_d_d2_d0 ;
output Ito_pd_x13_d_d0 ;
wire Idly_y3_in ;
wire IYenc_out_d1_d1 ;
wire Idly_x11_in ;
wire Ito_pd_x12_a ;
wire Iiny1_d_d0 ;
output Iout_d_d6_d1 ;
wire Iinx14_d_d0 ;
wire Idly_x12_in ;
wire Idly_y4_in ;
wire Idly_x7_out ;
wire Iinx10_d_d0 ;
wire Isupply_vss ;
wire Idly_y0_out ;
wire Ito_pd_x10_a ;
wire Ito_pd_x14_a ;
wire Iout_a ;
output Ito_pd_x1_d_d0 ;
wire Ito_pd_x1_a ;
output Iinx5_a ;
output Iinx7_a ;
output Ito_pd_x9_d_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d5_d0 ;
wire Ito_pd_y0_a ;
output Iout_d_d6_d0 ;
wire Iinx7_d_d0 ;
wire Ia_x_Cel_c1 ;
output Iinx2_a ;
output Iinx4_a ;
wire IXenc_out_d1_d1 ;
output Ito_pd_x10_d_d0 ;
wire Idly_x1_out ;
wire Ito_pd_y2_a ;
wire Iinx0_d_d0 ;
wire _a_y ;
output Ito_pd_x12_d_d0 ;
wire Idly_x5_in ;
wire Idly_x6_in ;
wire IXenc_out_d3_d1 ;
wire Idly_y4_out ;
output Iout_d_d0_d1 ;
output Ito_pd_x8_d_d0 ;
output Ito_pd_x14_d_d0 ;
wire IYenc_out_d1_d0 ;
wire Iinv_buf_a ;
wire Idly_x0_out ;
wire Idly_x14_out ;
output Iinx9_a ;
output Ito_pd_y4_d_d0 ;
wire Idly_x4_in ;
wire IXenc_out_d2_d0 ;
wire Iiny0_d_d0 ;
output Iout_d_d3_d0 ;
wire IXenc_out_d3_d0 ;
wire IYenc_out_d2_d1 ;
wire Idly_x9_in ;
output Iinx11_a ;
wire Iout_v ;
wire Ito_pd_y4_a ;
wire Idly_x10_out ;
output Iiny5_a ;
output Iout_d_d1_d0 ;
wire Idly_x9_out ;
wire Ito_pd_x0_a ;
output Ito_pd_y5_d_d0 ;
wire Iinx3_d_d0 ;
wire Iinx13_d_d0 ;
output Ito_pd_x5_d_d0 ;
wire Idly_x6_out ;
output Iout_d_d1_d1 ;
wire Iinx8_d_d0 ;
wire _a_x ;
wire Idly_y2_in ;
wire Ito_pd_x4_a ;
output Iiny0_a ;
output Iinx12_a ;
output Iiny1_a ;
wire Idly_x0_in ;
wire Idly_x10_in ;
output Iinx6_a ;
wire Ito_pd_y5_a ;
output Iinx3_a ;
wire Idly_y1_out ;
wire IYenc_out_d0_d0 ;
wire Iinx9_d_d0 ;
wire _r_x ;
wire Ito_pd_x11_a ;
wire IYenc_out_d0_d1 ;
wire Iinx12_d_d0 ;
output Ito_pd_y1_d_d0 ;
output Iiny3_a ;
wire Iinx6_d_d0 ;
wire Ito_pd_x7_a ;
wire Ito_pd_x6_a ;
wire Iinx5_d_d0 ;
wire IXenc_out_d2_d1 ;
wire Iinx4_d_d0 ;
wire IXenc_out_d1_d0 ;
output Ito_pd_y2_d_d0 ;
wire Iiny4_d_d0 ;
output Iinx14_a ;
wire Idly_y5_out ;
wire Idly_x2_out ;
wire Idly_x13_out ;
output Ito_pd_y3_d_d0 ;
wire Idly_x7_in ;
output Ito_pd_x4_d_d0 ;
wire Isupply_vdd ;
output Ito_pd_x0_d_d0 ;
wire Idly_y5_in ;
output Iout_d_d4_d0 ;
wire Idly_x3_in ;
wire Ito_pd_x9_a ;
output Iout_d_d0_d0 ;
output Iinx8_a ;
wire Idly_y1_in ;
wire reset_B;
output Iinx10_a ;
wire IXenc_out_d0_d0 ;
wire Idly_x9_in ;
wire IXenc_out_d2_d1 ;
output Ito_pd_x7_d_d0 ;
wire Ibuf_in_v ;
wire _r_x ;
wire Idly_y1_in ;
wire Idly_x8_out ;
output Ito_pd_x4_d_d0 ;
output Ito_pd_y3_d_d0 ;
output Iout_d_d0_d0 ;
wire Idly_x1_out ;
wire Iinx4_d_d0 ;
output Iinx12_a ;
output Iout_d_d4_d1 ;
output Iout_d_d5_d1 ;
wire Idly_x7_in ;
output Iinx5_a ;
wire Ito_pd_x8_a ;
wire Ito_pd_x2_a ;
wire Iinx13_d_d0 ;
output Iiny2_a ;
output Iout_d_d6_d0 ;
wire Iinx10_d_d0 ;
wire _r_y ;
wire Idly_y0_out ;
wire Ito_pd_y1_a ;
output Iinx14_a ;
output Iout_d_d2_d0 ;
wire Iinx1_d_d0 ;
wire Iinx5_d_d0 ;
wire IXenc_out_d1_d0 ;
wire Idly_x6_out ;
output Ito_pd_x1_d_d0 ;
output Iout_d_d1_d1 ;
output Iinx2_a ;
wire Iinx7_d_d0 ;
wire Idly_x12_in ;
wire Idly_x3_out ;
wire Idly_x4_out ;
output Ito_pd_x3_d_d0 ;
wire Iiny5_d_d0 ;
wire Idly_y3_in ;
output Iiny4_a ;
output Iinx1_a ;
wire Ito_pd_x5_a ;
output Iiny1_a ;
output Iinx11_a ;
wire Idly_x11_out ;
output Iout_d_d6_d1 ;
output Iout_d_d3_d0 ;
wire Idly_x3_in ;
output Iiny3_a ;
wire Ito_pd_x9_a ;
wire IYenc_out_d2_d1 ;
wire Idly_y4_out ;
wire IYenc_out_d2_d0 ;
wire Idly_x6_in ;
wire Iinx9_d_d0 ;
wire Idly_y5_in ;
output Ito_pd_x0_d_d0 ;
wire Ipd_y5_reset_B ;
wire Idly_x10_out ;
wire Ito_pd_x11_a ;
output Iout_d_d2_d1 ;
wire Idly_y5_out ;
wire Ito_pd_x6_a ;
output Iiny5_a ;
wire Idly_x4_in ;
wire Ito_pd_x1_a ;
wire Ito_pd_x3_a ;
wire Idly_x10_in ;
output Iinx0_a ;
wire IXenc_out_d1_d1 ;
output Ito_pd_x2_d_d0 ;
output Ito_pd_y0_d_d0 ;
wire Idly_y2_out ;
output Ito_pd_x11_d_d0 ;
wire Ito_pd_y0_a ;
wire Iiny4_d_d0 ;
wire Iiny1_d_d0 ;
output Iinx7_a ;
output Ito_pd_x12_d_d0 ;
wire Idly_y0_in ;
wire Idly_x7_out ;
wire Ito_pd_y2_a ;
wire _a_y ;
output Iinx4_a ;
wire IXenc_out_d2_d0 ;
wire Idly_x14_out ;
wire Ito_pd_x13_a ;
output Iiny4_a ;
wire Iiny5_d_d0 ;
wire Iiny3_d_d0 ;
wire Ito_pd_y3_a ;
wire IYenc_out_d0_d0 ;
wire Isupply_vss ;
wire Ito_pd_x10_a ;
wire Iinx8_d_d0 ;
wire IXenc_out_d3_d0 ;
wire Iinx3_d_d0 ;
wire Idly_x2_in ;
wire Idly_x12_out ;
output Ito_pd_y1_d_d0 ;
wire Idly_x0_in ;
output Iiny2_a ;
wire Iiny2_d_d0 ;
wire Idly_x8_in ;
wire _r_y ;
wire IXenc_out_d0_d0 ;
output Iinx1_a ;
output Ito_pd_x3_d_d0 ;
output Ito_pd_x6_d_d0 ;
wire Idly_x3_out ;
output Iout_d_d3_d1 ;
output Ito_pd_x11_d_d0 ;
wire Idly_y3_out ;
wire Idly_x4_out ;
wire Ito_pd_x13_a ;
wire Ipd_y5_reset_B ;
wire Idly_x14_in ;
wire Idly_x5_out ;
wire Idly_x8_out ;
wire IYenc_out_d2_d0 ;
wire Ipd_x14_reset_B ;
output Iinx0_a ;
wire Ito_pd_x3_a ;
output Iout_d_d4_d1 ;
wire Idly_x13_in ;
wire Ia_x_Cel_c1 ;
output Iinx3_a ;
wire Ito_pd_y4_a ;
wire Ito_pd_x8_a ;
wire Idly_x1_in ;
wire Idly_x11_out ;
wire Ibuf_in_v ;
wire Iinx11_d_d0 ;
wire Idly_y0_in ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbtree_315_4 IXarb (.Iin0_d_d0 (Iinx0_d_d0 ), .Iin0_a (Idly_x0_in ), .Iin1_d_d0 (Iinx1_d_d0 ), .Iin1_a (Idly_x1_in ), .Iin2_d_d0 (Iinx2_d_d0 ), .Iin2_a (Idly_x2_in ), .Iin3_d_d0 (Iinx3_d_d0 ), .Iin3_a (Idly_x3_in ), .Iin4_d_d0 (Iinx4_d_d0 ), .Iin4_a (Idly_x4_in ), .Iin5_d_d0 (Iinx5_d_d0 ), .Iin5_a (Idly_x5_in ), .Iin6_d_d0 (Iinx6_d_d0 ), .Iin6_a (Idly_x6_in ), .Iin7_d_d0 (Iinx7_d_d0 ), .Iin7_a (Idly_x7_in ), .Iin8_d_d0 (Iinx8_d_d0 ), .Iin8_a (Idly_x8_in ), .Iin9_d_d0 (Iinx9_d_d0 ), .Iin9_a (Idly_x9_in ), .Iin10_d_d0 (Iinx10_d_d0 ), .Iin10_a (Idly_x10_in ), .Iin11_d_d0 (Iinx11_d_d0 ), .Iin11_a (Idly_x11_in ), .Iin12_d_d0 (Iinx12_d_d0 ), .Iin12_a (Idly_x12_in ), .Iin13_d_d0 (Iinx13_d_d0 ), .Iin13_a (Idly_x13_in ), .Iin14_d_d0 (Iinx14_d_d0 ), .Iin14_a (Idly_x14_in ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));
@ -279,6 +281,21 @@ INV_X2 Iinv_buf (.y(Ia_x_Cel_c1 ), .a(Iinv_buf_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_pd_x (.in(reset_B), .Iout0 (Ipd_x14_reset_B ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_y_Cel (.y(_a_y), .c1(Ia_x_Cel_c1 ), .c2(_r_y), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4 IXenc (.Iin0 (Iinx0_a ), .Iin1 (Iinx1_a ), .Iin2 (Iinx2_a ), .Iin3 (Iinx3_a ), .Iin4 (Iinx4_a ), .Iin5 (Iinx5_a ), .Iin6 (Iinx6_a ), .Iin7 (Iinx7_a ), .Iin8 (Iinx8_a ), .Iin9 (Iinx9_a ), .Iin10 (Iinx10_a ), .Iin11 (Iinx11_a ), .Iin12 (Iinx12_a ), .Iin13 (Iinx13_a ), .Iin14 (Iinx14_a ), .Iout_d0_d0 (IXenc_out_d0_d0 ), .Iout_d0_d1 (IXenc_out_d0_d1 ), .Iout_d1_d0 (IXenc_out_d1_d0 ), .Iout_d1_d1 (IXenc_out_d1_d1 ), .Iout_d2_d0 (IXenc_out_d2_d0 ), .Iout_d2_d1 (IXenc_out_d2_d1 ), .Iout_d3_d0 (IXenc_out_d3_d0 ), .Iout_d3_d1 (IXenc_out_d3_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x0 (.y(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x1 (.y(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x2 (.y(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x3 (.y(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x4 (.y(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x5 (.y(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x6 (.y(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x7 (.y(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x8 (.y(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x9 (.y(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x10 (.y(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x11 (.y(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x12 (.y(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x13 (.y(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x14 (.y(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y0 (.out(Idly_y0_out ), .in(Idly_y0_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y1 (.out(Idly_y1_out ), .in(Idly_y1_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y2 (.out(Idly_y2_out ), .in(Idly_y2_in ), .vdd(vdd), .vss(vss));
@ -300,27 +317,27 @@ BUF_X12 Isb_inx_a11 (.y(Iinx11_a ), .a(Idly_x11_out ), .vdd(vdd), .vss(vss));
BUF_X12 Isb_inx_a12 (.y(Iinx12_a ), .a(Idly_x12_out ), .vdd(vdd), .vss(vss));
BUF_X12 Isb_inx_a13 (.y(Iinx13_a ), .a(Idly_x13_out ), .vdd(vdd), .vss(vss));
BUF_X12 Isb_inx_a14 (.y(Iinx14_a ), .a(Idly_x14_out ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x0 (.in(Ito_pd_x0_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x1 (.in(Ito_pd_x1_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x2 (.in(Ito_pd_x2_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x3 (.in(Ito_pd_x3_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x4 (.in(Ito_pd_x4_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x5 (.in(Ito_pd_x5_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x6 (.in(Ito_pd_x6_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x7 (.in(Ito_pd_x7_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x8 (.in(Ito_pd_x8_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x9 (.in(Ito_pd_x9_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x10 (.in(Ito_pd_x10_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x11 (.in(Ito_pd_x11_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x12 (.in(Ito_pd_x12_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x13 (.in(Ito_pd_x13_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x14 (.in(Ito_pd_x14_a ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y0 (.in(Ito_pd_y0_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y1 (.in(Ito_pd_y1_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y2 (.in(Ito_pd_y2_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y3 (.in(Ito_pd_y3_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y4 (.in(Ito_pd_y4_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y5 (.in(Ito_pd_y5_a ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x0 (.in(Ito_pd_x0_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x1 (.in(Ito_pd_x1_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x2 (.in(Ito_pd_x2_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x3 (.in(Ito_pd_x3_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x4 (.in(Ito_pd_x4_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x5 (.in(Ito_pd_x5_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x6 (.in(Ito_pd_x6_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x7 (.in(Ito_pd_x7_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x8 (.in(Ito_pd_x8_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x9 (.in(Ito_pd_x9_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x10 (.in(Ito_pd_x10_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x11 (.in(Ito_pd_x11_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x12 (.in(Ito_pd_x12_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x13 (.in(Ito_pd_x13_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x14 (.in(Ito_pd_x14_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y0 (.in(Ito_pd_y0_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y1 (.in(Ito_pd_y1_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y2 (.in(Ito_pd_y2_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y3 (.in(Ito_pd_y3_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y4 (.in(Ito_pd_y4_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y5 (.in(Ito_pd_y5_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ibuf (.Iin_d_d0_d0 (IXenc_out_d0_d0 ), .Iin_d_d0_d1 (IXenc_out_d0_d1 ), .Iin_d_d1_d0 (IXenc_out_d1_d0 ), .Iin_d_d1_d1 (IXenc_out_d1_d1 ), .Iin_d_d2_d0 (IXenc_out_d2_d0 ), .Iin_d_d2_d1 (IXenc_out_d2_d1 ), .Iin_d_d3_d0 (IXenc_out_d3_d0 ), .Iin_d_d3_d1 (IXenc_out_d3_d1 ), .Iin_d_d4_d0 (IYenc_out_d0_d0 ), .Iin_d_d4_d1 (IYenc_out_d0_d1 ), .Iin_d_d5_d0 (IYenc_out_d1_d0 ), .Iin_d_d5_d1 (IYenc_out_d1_d1 ), .Iin_d_d6_d0 (IYenc_out_d2_d0 ), .Iin_d_d6_d1 (IYenc_out_d2_d1 ), .Iin_a (Iinv_buf_a ), .Iin_v (Ibuf_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x0 (.out(Idly_x0_out ), .in(Idly_x0_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x1 (.out(Idly_x1_out ), .in(Idly_x1_in ), .vdd(vdd), .vss(vss));
@ -337,6 +354,12 @@ tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x11 (.out(Idly_x11_out ), .in
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x12 (.out(Idly_x12_out ), .in(Idly_x12_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x13 (.out(Idly_x13_out ), .in(Idly_x13_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x14 (.out(Idly_x14_out ), .in(Idly_x14_in ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y0 (.y(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y1 (.y(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y2 (.y(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y3 (.y(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y4 (.y(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y5 (.y(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbtree_36_4 IYarb (.Iin0_d_d0 (Iiny0_d_d0 ), .Iin0_a (Idly_y0_in ), .Iin1_d_d0 (Iiny1_d_d0 ), .Iin1_a (Idly_y1_in ), .Iin2_d_d0 (Iiny2_d_d0 ), .Iin2_a (Idly_y2_in ), .Iin3_d_d0 (Iiny3_d_d0 ), .Iin3_a (Idly_y3_in ), .Iin4_d_d0 (Iiny4_d_d0 ), .Iin4_a (Idly_y4_in ), .Iin5_d_d0 (Iiny5_d_d0 ), .Iin5_a (Idly_y5_in ), .Iout_d_d0 (_r_y), .Iout_a (_a_y), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4 IYenc (.Iin0 (Iiny0_a ), .Iin1 (Iiny1_a ), .Iin2 (Iiny2_a ), .Iin3 (Iiny3_a ), .Iin4 (Iiny4_a ), .Iin5 (Iiny5_a ), .Iout_d0_d0 (IYenc_out_d0_d0 ), .Iout_d0_d1 (IYenc_out_d0_d1 ), .Iout_d1_d0 (IYenc_out_d1_d0 ), .Iout_d1_d1 (IYenc_out_d1_d1 ), .Iout_d2_d0 (IYenc_out_d2_d0 ), .Iout_d2_d1 (IYenc_out_d2_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
BUF_X12 Isb_iny_a0 (.y(Iiny0_a ), .a(Idly_y0_out ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_73_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

329
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_73_4/netlist/verilog.v

@ -1,329 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_73_4(Iinx0_d_d0 , Iinx0_a , Iinx1_d_d0 , Iinx1_a , Iinx2_d_d0 , Iinx2_a , Iinx3_d_d0 , Iinx3_a , Iinx4_d_d0 , Iinx4_a , Iinx5_d_d0 , Iinx5_a , Iinx6_d_d0 , Iinx6_a , Iinx7_d_d0 , Iinx7_a , Iinx8_d_d0 , Iinx8_a , Iinx9_d_d0 , Iinx9_a , Iinx10_d_d0 , Iinx10_a , Iinx11_d_d0 , Iinx11_a , Iinx12_d_d0 , Iinx12_a , Iinx13_d_d0 , Iinx13_a , Iinx14_d_d0 , Iinx14_a , Iiny0_d_d0 , Iiny0_a , Iiny1_d_d0 , Iiny1_a , Iiny2_d_d0 , Iiny2_a , Iiny3_d_d0 , Iiny3_a , Iiny4_d_d0 , Iiny4_a , Iiny5_d_d0 , Iiny5_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , Ito_pd_x0_d_d0 , Ito_pd_x0_a , Ito_pd_x1_d_d0 , Ito_pd_x1_a , Ito_pd_x2_d_d0 , Ito_pd_x2_a , Ito_pd_x3_d_d0 , Ito_pd_x3_a , Ito_pd_x4_d_d0 , Ito_pd_x4_a , Ito_pd_x5_d_d0 , Ito_pd_x5_a , Ito_pd_x6_d_d0 , Ito_pd_x6_a , Ito_pd_x7_d_d0 , Ito_pd_x7_a , Ito_pd_x8_d_d0 , Ito_pd_x8_a , Ito_pd_x9_d_d0 , Ito_pd_x9_a , Ito_pd_x10_d_d0 , Ito_pd_x10_a , Ito_pd_x11_d_d0 , Ito_pd_x11_a , Ito_pd_x12_d_d0 , Ito_pd_x12_a , Ito_pd_x13_d_d0 , Ito_pd_x13_a , Ito_pd_x14_d_d0 , Ito_pd_x14_a , Ito_pd_y0_d_d0 , Ito_pd_y0_a , Ito_pd_y1_d_d0 , Ito_pd_y1_a , Ito_pd_y2_d_d0 , Ito_pd_y2_a , Ito_pd_y3_d_d0 , Ito_pd_y3_a , Ito_pd_y4_d_d0 , Ito_pd_y4_a , Ito_pd_y5_d_d0 , Ito_pd_y5_a , Isupply_vss , reset_B, vdd, vss);
input vdd;
input vss;
input Iinx0_d_d0 ;
input Iinx1_d_d0 ;
input Iinx2_d_d0 ;
input Iinx3_d_d0 ;
input Iinx4_d_d0 ;
input Iinx5_d_d0 ;
input Iinx6_d_d0 ;
input Iinx7_d_d0 ;
input Iinx8_d_d0 ;
input Iinx9_d_d0 ;
input Iinx10_d_d0 ;
input Iinx11_d_d0 ;
input Iinx12_d_d0 ;
input Iinx13_d_d0 ;
input Iinx14_d_d0 ;
input Iiny0_d_d0 ;
input Iiny1_d_d0 ;
input Iiny2_d_d0 ;
input Iiny3_d_d0 ;
input Iiny4_d_d0 ;
input Iiny5_d_d0 ;
input Iout_a ;
input Iout_v ;
input Ito_pd_x0_a ;
input Ito_pd_x1_a ;
input Ito_pd_x2_a ;
input Ito_pd_x3_a ;
input Ito_pd_x4_a ;
input Ito_pd_x5_a ;
input Ito_pd_x6_a ;
input Ito_pd_x7_a ;
input Ito_pd_x8_a ;
input Ito_pd_x9_a ;
input Ito_pd_x10_a ;
input Ito_pd_x11_a ;
input Ito_pd_x12_a ;
input Ito_pd_x13_a ;
input Ito_pd_x14_a ;
input Ito_pd_y0_a ;
input Ito_pd_y1_a ;
input Ito_pd_y2_a ;
input Ito_pd_y3_a ;
input Ito_pd_y4_a ;
input Ito_pd_y5_a ;
input Isupply_vss ;
input reset_B;
// -- signals ---
wire Ipd_x14_in ;
wire Iinx9_d_d0 ;
wire Ia_x_Cel_c1 ;
output Ito_pd_x4_d_d0 ;
wire _a_y ;
output Iinx6_a ;
wire Ito_pd_x7_a ;
output Iinx5_a ;
output Iinx9_a ;
output Ito_pd_x9_d_d0 ;
wire IYenc_out_d0_d1 ;
wire IYenc_out_d2_d1 ;
output Iout_d_d1_d0 ;
wire Iinx6_d_d0 ;
wire Ito_pd_y4_a ;
wire Iiny3_d_d0 ;
output Iinx2_a ;
wire Iinx13_d_d0 ;
wire Iinx4_d_d0 ;
wire Iinx10_d_d0 ;
output Ito_pd_x8_d_d0 ;
output Iout_d_d0_d0 ;
output Iiny1_a ;
output Iout_d_d0_d1 ;
wire Ito_pd_x1_a ;
output Ito_pd_x11_d_d0 ;
output Ito_pd_x0_d_d0 ;
output Iiny3_a ;
wire Ipd_x2_in ;
wire Ito_pd_x13_a ;
wire Ipd_y3_in ;
wire Ito_pd_y5_a ;
output Iout_d_d2_d1 ;
wire Ipd_x11_in ;
output Ito_pd_y1_d_d0 ;
wire Iinx5_d_d0 ;
output Ito_pd_x12_d_d0 ;
output Iout_d_d5_d0 ;
output Iinx13_a ;
output Iinx1_a ;
output Iinx11_a ;
output Ito_pd_x3_d_d0 ;
wire IYenc_out_d1_d0 ;
wire Ipd_x14_reset_B ;
wire IXenc_out_d2_d1 ;
output Iout_d_d3_d1 ;
wire IXenc_out_d0_d1 ;
output Ito_pd_y2_d_d0 ;
wire Ito_pd_x0_a ;
wire Ito_pd_x2_a ;
output Iiny0_a ;
output Iinx10_a ;
wire IXenc_out_d3_d1 ;
wire Ipd_x3_in ;
output Iout_d_d3_d0 ;
wire Ito_pd_x11_a ;
wire Ito_pd_x9_a ;
wire Iinx3_d_d0 ;
wire Ipd_y5_in ;
wire Iiny2_d_d0 ;
wire Iinx0_d_d0 ;
wire Iinx12_d_d0 ;
wire Ipd_y0_in ;
wire Iinx7_d_d0 ;
output Ito_pd_x14_d_d0 ;
wire Ito_pd_x6_a ;
wire Iiny5_d_d0 ;
wire Ito_pd_y3_a ;
output Ito_pd_x2_d_d0 ;
output Iiny5_a ;
wire Iiny0_d_d0 ;
wire Ito_pd_y2_a ;
output Ito_pd_x6_d_d0 ;
output Iinx7_a ;
wire Ipd_x1_in ;
wire Ibuf_in_v ;
wire Isupply_vss ;
wire Iinx8_d_d0 ;
wire Ipd_x8_in ;
wire IXenc_out_d1_d1 ;
wire IXenc_out_d2_d0 ;
wire IYenc_out_d0_d0 ;
output Ito_pd_y0_d_d0 ;
wire Ito_pd_x12_a ;
wire Ipd_x6_in ;
output Iout_d_d6_d0 ;
wire Ito_pd_x10_a ;
wire Ipd_x10_in ;
wire Iout_a ;
wire Ito_pd_x4_a ;
output Iiny4_a ;
output Iinx14_a ;
wire _a_x ;
wire Ipd_x12_in ;
output Ito_pd_y3_d_d0 ;
output Ito_pd_x1_d_d0 ;
output Iinx3_a ;
wire Ito_pd_x5_a ;
wire Ito_pd_x14_a ;
output Iinx0_a ;
output Iinx12_a ;
wire _r_y ;
wire Ipd_y4_in ;
wire Ipd_x4_in ;
wire Iinx2_d_d0 ;
wire IYenc_out_d1_d1 ;
wire _r_x ;
output Iiny2_a ;
wire Iinx14_d_d0 ;
wire IYenc_out_d2_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d4_d0 ;
output Iinx8_a ;
wire IXenc_out_d1_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d5_d1 ;
wire Iinx11_d_d0 ;
wire Iiny1_d_d0 ;
wire Ito_pd_x8_a ;
output Ito_pd_x13_d_d0 ;
wire Ipd_x5_in ;
wire Iiny4_d_d0 ;
wire Ipd_x7_in ;
output Iout_d_d6_d1 ;
wire Iinx1_d_d0 ;
wire IXenc_out_d3_d0 ;
output Ito_pd_x5_d_d0 ;
output Ito_pd_x10_d_d0 ;
wire Ito_pd_y0_a ;
output Iinx4_a ;
wire Iinv_buf_a ;
wire Ipd_x13_in ;
wire reset_B;
wire Ito_pd_y1_a ;
output Iout_d_d2_d0 ;
wire Ito_pd_x3_a ;
wire IXenc_out_d0_d0 ;
wire Ipd_y1_in ;
wire Ipd_y2_in ;
output Ito_pd_y5_d_d0 ;
wire Ipd_x0_in ;
wire Ipd_x9_in ;
output Ito_pd_y4_d_d0 ;
wire Iout_v ;
output Ito_pd_x7_d_d0 ;
wire Ipd_y5_reset_B ;
// --- instances
tmpl_0_0dataflow__neuro_0_0arbtree_315_4 IXarb (.Iin0_d_d0 (Iinx0_d_d0 ), .Iin0_a (Iinx0_a ), .Iin1_d_d0 (Iinx1_d_d0 ), .Iin1_a (Iinx1_a ), .Iin2_d_d0 (Iinx2_d_d0 ), .Iin2_a (Iinx2_a ), .Iin3_d_d0 (Iinx3_d_d0 ), .Iin3_a (Iinx3_a ), .Iin4_d_d0 (Iinx4_d_d0 ), .Iin4_a (Iinx4_a ), .Iin5_d_d0 (Iinx5_d_d0 ), .Iin5_a (Iinx5_a ), .Iin6_d_d0 (Iinx6_d_d0 ), .Iin6_a (Iinx6_a ), .Iin7_d_d0 (Iinx7_d_d0 ), .Iin7_a (Iinx7_a ), .Iin8_d_d0 (Iinx8_d_d0 ), .Iin8_a (Iinx8_a ), .Iin9_d_d0 (Iinx9_d_d0 ), .Iin9_a (Iinx9_a ), .Iin10_d_d0 (Iinx10_d_d0 ), .Iin10_a (Iinx10_a ), .Iin11_d_d0 (Iinx11_d_d0 ), .Iin11_a (Iinx11_a ), .Iin12_d_d0 (Iinx12_d_d0 ), .Iin12_a (Iinx12_a ), .Iin13_d_d0 (Iinx13_d_d0 ), .Iin13_a (Iinx13_a ), .Iin14_d_d0 (Iinx14_d_d0 ), .Iin14_a (Iinx14_a ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));
INV_X2 Iinv_buf (.y(Ia_x_Cel_c1 ), .a(Iinv_buf_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_pd_x (.in(reset_B), .Iout0 (Ipd_x14_reset_B ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_y_Cel (.y(_a_y), .c1(Ia_x_Cel_c1 ), .c2(_r_y), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4 IXenc (.Iin0 (Iinx0_a ), .Iin1 (Iinx1_a ), .Iin2 (Iinx2_a ), .Iin3 (Iinx3_a ), .Iin4 (Iinx4_a ), .Iin5 (Iinx5_a ), .Iin6 (Iinx6_a ), .Iin7 (Iinx7_a ), .Iin8 (Iinx8_a ), .Iin9 (Iinx9_a ), .Iin10 (Iinx10_a ), .Iin11 (Iinx11_a ), .Iin12 (Iinx12_a ), .Iin13 (Iinx13_a ), .Iin14 (Iinx14_a ), .Iout_d0_d0 (IXenc_out_d0_d0 ), .Iout_d0_d1 (IXenc_out_d0_d1 ), .Iout_d1_d0 (IXenc_out_d1_d0 ), .Iout_d1_d1 (IXenc_out_d1_d1 ), .Iout_d2_d0 (IXenc_out_d2_d0 ), .Iout_d2_d1 (IXenc_out_d2_d1 ), .Iout_d3_d0 (IXenc_out_d3_d0 ), .Iout_d3_d1 (IXenc_out_d3_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_y0 (.out(Ipd_y0_in ), .in(Ito_pd_y0_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_y1 (.out(Ipd_y1_in ), .in(Ito_pd_y1_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_y2 (.out(Ipd_y2_in ), .in(Ito_pd_y2_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_y3 (.out(Ipd_y3_in ), .in(Ito_pd_y3_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_y4 (.out(Ipd_y4_in ), .in(Ito_pd_y4_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_y5 (.out(Ipd_y5_in ), .in(Ito_pd_y5_a ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x0 (.y(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x1 (.y(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x2 (.y(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x3 (.y(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x4 (.y(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x5 (.y(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x6 (.y(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x7 (.y(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x8 (.y(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x9 (.y(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x10 (.y(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x11 (.y(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x12 (.y(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x13 (.y(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_x14 (.y(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x0 (.in(Ipd_x0_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x1 (.in(Ipd_x1_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x2 (.in(Ipd_x2_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x3 (.in(Ipd_x3_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x4 (.in(Ipd_x4_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x5 (.in(Ipd_x5_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x6 (.in(Ipd_x6_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x7 (.in(Ipd_x7_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x8 (.in(Ipd_x8_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x9 (.in(Ipd_x9_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x10 (.in(Ipd_x10_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x11 (.in(Ipd_x11_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x12 (.in(Ipd_x12_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x13 (.in(Ipd_x13_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x14 (.in(Ipd_x14_in ), .reset_B(Ipd_x14_reset_B ), .out(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y0 (.in(Ipd_y0_in ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y1 (.in(Ipd_y1_in ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y2 (.in(Ipd_y2_in ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y3 (.in(Ipd_y3_in ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y4 (.in(Ipd_y4_in ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y5 (.in(Ipd_y5_in ), .reset_B(Ipd_y5_reset_B ), .out(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ibuf (.Iin_d_d0_d0 (IXenc_out_d0_d0 ), .Iin_d_d0_d1 (IXenc_out_d0_d1 ), .Iin_d_d1_d0 (IXenc_out_d1_d0 ), .Iin_d_d1_d1 (IXenc_out_d1_d1 ), .Iin_d_d2_d0 (IXenc_out_d2_d0 ), .Iin_d_d2_d1 (IXenc_out_d2_d1 ), .Iin_d_d3_d0 (IXenc_out_d3_d0 ), .Iin_d_d3_d1 (IXenc_out_d3_d1 ), .Iin_d_d4_d0 (IYenc_out_d0_d0 ), .Iin_d_d4_d1 (IYenc_out_d0_d1 ), .Iin_d_d5_d0 (IYenc_out_d1_d0 ), .Iin_d_d5_d1 (IYenc_out_d1_d1 ), .Iin_d_d6_d0 (IYenc_out_d2_d0 ), .Iin_d_d6_d1 (IYenc_out_d2_d1 ), .Iin_a (Iinv_buf_a ), .Iin_v (Ibuf_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x0 (.out(Ipd_x0_in ), .in(Ito_pd_x0_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x1 (.out(Ipd_x1_in ), .in(Ito_pd_x1_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x2 (.out(Ipd_x2_in ), .in(Ito_pd_x2_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x3 (.out(Ipd_x3_in ), .in(Ito_pd_x3_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x4 (.out(Ipd_x4_in ), .in(Ito_pd_x4_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x5 (.out(Ipd_x5_in ), .in(Ito_pd_x5_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x6 (.out(Ipd_x6_in ), .in(Ito_pd_x6_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x7 (.out(Ipd_x7_in ), .in(Ito_pd_x7_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x8 (.out(Ipd_x8_in ), .in(Ito_pd_x8_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x9 (.out(Ipd_x9_in ), .in(Ito_pd_x9_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x10 (.out(Ipd_x10_in ), .in(Ito_pd_x10_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x11 (.out(Ipd_x11_in ), .in(Ito_pd_x11_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x12 (.out(Ipd_x12_in ), .in(Ito_pd_x12_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x13 (.out(Ipd_x13_in ), .in(Ito_pd_x13_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0delay__chain_33_4 Idly_x14 (.out(Ipd_x14_in ), .in(Ito_pd_x14_a ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y0 (.y(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y1 (.y(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y2 (.y(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y3 (.y(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y4 (.y(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
KEEP Ikeep_y5 (.y(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0arbtree_36_4 IYarb (.Iin0_d_d0 (Iiny0_d_d0 ), .Iin0_a (Iiny0_a ), .Iin1_d_d0 (Iiny1_d_d0 ), .Iin1_a (Iiny1_a ), .Iin2_d_d0 (Iiny2_d_d0 ), .Iin2_a (Iiny2_a ), .Iin3_d_d0 (Iiny3_d_d0 ), .Iin3_a (Iiny3_a ), .Iin4_d_d0 (Iiny4_d_d0 ), .Iin4_a (Iiny4_a ), .Iin5_d_d0 (Iiny5_d_d0 ), .Iin5_a (Iiny5_a ), .Iout_d_d0 (_r_y), .Iout_a (_a_y), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4 IYenc (.Iin0 (Iiny0_a ), .Iin1 (Iiny1_a ), .Iin2 (Iiny2_a ), .Iin3 (Iiny3_a ), .Iin4 (Iiny4_a ), .Iin5 (Iiny5_a ), .Iout_d0_d0 (IYenc_out_d0_d0 ), .Iout_d0_d1 (IYenc_out_d0_d1 ), .Iout_d1_d0 (IYenc_out_d1_d0 ), .Iout_d1_d1 (IYenc_out_d1_d1 ), .Iout_d2_d0 (IYenc_out_d2_d0 ), .Iout_d2_d1 (IYenc_out_d2_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
A_2C_RB_X1 Ia_x_Cel (.y(_a_x), .c1(Ia_x_Cel_c1 ), .c2(_r_x), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Irsb_pd_y (.in(reset_B), .Iout0 (Ipd_y5_reset_B ), .vdd(vdd), .vss(vss));
endmodule

212
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_313_73_4/netlist/verilog.v

@ -60,121 +60,121 @@ module tmpl_0_0dataflow__neuro_0_0fifo_313_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
input reset_B;
// -- signals ---
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element1_in_d_d2_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d0_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element2_in_v ;
wire Ififo_element1_in_d_d12_d1 ;
output Iout_d_d5_d1 ;
wire Ififo_element1_in_d_d11_d1 ;
output Iin_a ;
wire _reset_BX ;
output Iout_d_d3_d1 ;
wire Iin_d_d11_d1 ;
output Iout_d_d3_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
output Iout_d_d10_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Iin_d_d0_d1 ;
output Iout_d_d11_d0 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element2_in_d_d7_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d0_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Iin_d_d3_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d9_d0 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Iin_d_d9_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Iin_d_d12_d0 ;
output Iout_d_d7_d0 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Iin_d_d5_d1 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
output Iout_d_d2_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Iin_d_d5_d0 ;
wire Iout_v ;
wire Iin_d_d9_d0 ;
wire Iin_d_d8_d1 ;
wire Iout_a ;
wire Ififo_element1_in_v ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Iin_d_d1_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d7_d1 ;
wire Ififo_element2_in_d_d2_d1 ;
output Iout_d_d1_d1 ;
wire Ififo_element1_in_a ;
output Iout_d_d4_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
output Iout_d_d9_d1 ;
output Iout_d_d8_d0 ;
wire Ififo_element2_in_a ;
wire Ififo_element2_in_d_d11_d0 ;
output Iin_v ;
wire Iin_d_d6_d0 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d3_d1 ;
output Iout_d_d6_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Iin_d_d2_d0 ;
wire reset_B;
output Iout_d_d7_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d9_d1 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_d_d1_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire I_reset_BXX2 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element1_in_d_d5_d1 ;
output Iout_d_d12_d0 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Iin_d_d4_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Iin_d_d7_d0 ;
output Iout_d_d11_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d5_d0 ;
wire I_reset_BXX2 ;
output Iout_d_d7_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Iin_d_d1_d1 ;
output Iout_d_d5_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element1_in_d_d8_d0 ;
output Iout_d_d1_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element2_in_a ;
wire Iin_d_d12_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Iin_d_d8_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d3_d1 ;
wire Ififo_element1_in_d_d2_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d3_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
output Iout_d_d7_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Iin_d_d0_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Iin_d_d6_d1 ;
wire Iout_v ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_v ;
wire Iin_d_d11_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Ififo_element2_in_d_d7_d1 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d3_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d4_d1 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element2_in_d_d3_d1 ;
output Iout_d_d11_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d2_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d8_d1 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
output Iin_v ;
output Iin_a ;
output Iout_d_d11_d1 ;
output Iout_d_d6_d0 ;
wire Iin_d_d4_d0 ;
wire _reset_BX ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d12_d0 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d7_d0 ;
output Iout_d_d10_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element1_in_a ;
wire Ififo_element1_in_d_d6_d1 ;
wire Iout_a ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d4_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_313_75_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

243
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_313_75_4/netlist/verilog.v

@ -1,243 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0fifo_313_75_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
output Iout_d_d9_d1 ;
wire Iin_d_d2_d1 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Ififo_element4_in_d_d1_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element4_in_d_d8_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d5_d0 ;
wire Ififo_element4_in_d_d6_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element4_in_d_d1_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Iin_d_d4_d1 ;
output Iin_a ;
wire Ififo_element4_in_d_d5_d1 ;
wire Iin_d_d6_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Ififo_element3_in_d_d1_d1 ;
wire Ififo_element3_in_d_d9_d0 ;
wire Iin_d_d12_d1 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
output Iout_d_d7_d1 ;
wire Ififo_element1_in_a ;
wire Ififo_element2_in_d_d2_d1 ;
output Iout_d_d5_d1 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element4_in_d_d0_d1 ;
wire Ififo_element4_in_d_d11_d1 ;
wire Iin_d_d11_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
output Iout_d_d3_d0 ;
output Iin_v ;
wire Ififo_element4_in_d_d7_d1 ;
output Iout_d_d0_d0 ;
wire Ififo_element3_in_d_d10_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d1_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element3_in_d_d2_d1 ;
wire Ififo_element3_in_d_d8_d0 ;
wire Iout_a ;
wire Ififo_element1_in_d_d8_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Iin_d_d11_d1 ;
wire Ififo_element4_in_d_d2_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element3_in_a ;
wire Iin_d_d0_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
wire I_reset_BXX4 ;
wire Iin_d_d7_d0 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Iin_d_d12_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
output Iout_d_d11_d0 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element3_in_d_d6_d1 ;
output Iout_d_d4_d1 ;
wire Iin_d_d9_d0 ;
wire Ififo_element2_in_a ;
wire Iout_v ;
wire Ififo_element3_in_d_d8_d1 ;
wire Ififo_element3_in_d_d4_d1 ;
wire Ififo_element3_in_d_d5_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
output Iout_d_d10_d0 ;
wire Ififo_element4_in_d_d12_d0 ;
wire Iin_d_d8_d0 ;
wire Ififo_element3_in_d_d3_d1 ;
wire Iin_d_d5_d1 ;
wire Ififo_element3_in_d_d11_d0 ;
wire Ififo_element4_in_d_d5_d0 ;
wire Ififo_element4_in_d_d10_d1 ;
wire Iin_d_d8_d1 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element3_in_d_d12_d1 ;
wire Ififo_element4_in_d_d9_d0 ;
wire Ififo_element4_in_d_d8_d1 ;
wire Iin_d_d4_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element3_in_v ;
wire Ififo_element4_in_d_d6_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d1_d0 ;
wire Ififo_element4_in_d_d12_d1 ;
wire Ififo_element2_in_d_d7_d1 ;
output Iout_d_d12_d1 ;
wire Ififo_element4_in_v ;
wire Ififo_element3_in_d_d2_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d6_d1 ;
wire Iin_d_d10_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element4_in_d_d2_d0 ;
wire Ififo_element3_in_d_d11_d1 ;
wire Ififo_element4_in_a ;
wire Iin_d_d6_d0 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element2_in_v ;
wire Ififo_element3_in_d_d5_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element3_in_d_d4_d0 ;
wire Ififo_element3_in_d_d0_d0 ;
wire Ififo_element3_in_d_d10_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Ififo_element3_in_d_d7_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d2_d1 ;
wire _reset_BX ;
wire Iin_d_d9_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_v ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
output Iout_d_d7_d0 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element3_in_d_d6_d0 ;
wire Ififo_element3_in_d_d7_d0 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element4_in_d_d3_d0 ;
output Iout_d_d10_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element4_in_d_d10_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element3_in_d_d12_d0 ;
wire Ififo_element4_in_d_d9_d1 ;
wire reset_B;
wire Iin_d_d2_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
output Iout_d_d12_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Iin_d_d10_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
output Iout_d_d3_d1 ;
wire Ififo_element4_in_d_d4_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d7_d1 ;
wire Ififo_element4_in_d_d0_d0 ;
wire Ififo_element4_in_d_d11_d0 ;
wire Ififo_element3_in_d_d1_d0 ;
wire Ififo_element3_in_d_d9_d1 ;
output Iout_d_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Ififo_element2_in_d_d4_d0 ;
output Iout_d_d1_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element3_in_d_d0_d1 ;
wire Ififo_element4_in_d_d7_d0 ;
wire Ififo_element3_in_d_d3_d0 ;
wire Ififo_element4_in_d_d3_d1 ;
wire Ififo_element4_in_d_d4_d1 ;
output Iout_d_d8_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX4 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element0 (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_d_d7_d0 (Iin_d_d7_d0 ), .Iin_d_d7_d1 (Iin_d_d7_d1 ), .Iin_d_d8_d0 (Iin_d_d8_d0 ), .Iin_d_d8_d1 (Iin_d_d8_d1 ), .Iin_d_d9_d0 (Iin_d_d9_d0 ), .Iin_d_d9_d1 (Iin_d_d9_d1 ), .Iin_d_d10_d0 (Iin_d_d10_d0 ), .Iin_d_d10_d1 (Iin_d_d10_d1 ), .Iin_d_d11_d0 (Iin_d_d11_d0 ), .Iin_d_d11_d1 (Iin_d_d11_d1 ), .Iin_d_d12_d0 (Iin_d_d12_d0 ), .Iin_d_d12_d1 (Iin_d_d12_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element1_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element1_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element1_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element1_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element1_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element1_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element1_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element1_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element1_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element1_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element1_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element1_in_d_d12_d1 ), .Iout_a (Ififo_element1_in_a ), .Iout_v (Ififo_element1_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element1 (.Iin_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element1_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element1_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element1_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element1_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element1_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element1_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element1_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element1_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element1_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element1_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element1_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element1_in_d_d12_d1 ), .Iin_a (Ififo_element1_in_a ), .Iin_v (Ififo_element1_in_v ), .Iout_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element2_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element2_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element2_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element2_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element2_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element2_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element2_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element2_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element2_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element2_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element2_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element2_in_d_d12_d1 ), .Iout_a (Ififo_element2_in_a ), .Iout_v (Ififo_element2_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element2 (.Iin_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element2_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element2_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element2_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element2_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element2_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element2_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element2_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element2_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element2_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element2_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element2_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element2_in_d_d12_d1 ), .Iin_a (Ififo_element2_in_a ), .Iin_v (Ififo_element2_in_v ), .Iout_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element3_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element3_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element3_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element3_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element3_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element3_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element3_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element3_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element3_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element3_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element3_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element3_in_d_d12_d1 ), .Iout_a (Ififo_element3_in_a ), .Iout_v (Ififo_element3_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element3 (.Iin_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element3_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element3_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element3_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element3_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element3_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element3_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element3_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element3_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element3_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element3_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element3_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element3_in_d_d12_d1 ), .Iin_a (Ififo_element3_in_a ), .Iin_v (Ififo_element3_in_v ), .Iout_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iout_d_d7_d0 (Ififo_element4_in_d_d7_d0 ), .Iout_d_d7_d1 (Ififo_element4_in_d_d7_d1 ), .Iout_d_d8_d0 (Ififo_element4_in_d_d8_d0 ), .Iout_d_d8_d1 (Ififo_element4_in_d_d8_d1 ), .Iout_d_d9_d0 (Ififo_element4_in_d_d9_d0 ), .Iout_d_d9_d1 (Ififo_element4_in_d_d9_d1 ), .Iout_d_d10_d0 (Ififo_element4_in_d_d10_d0 ), .Iout_d_d10_d1 (Ififo_element4_in_d_d10_d1 ), .Iout_d_d11_d0 (Ififo_element4_in_d_d11_d0 ), .Iout_d_d11_d1 (Ififo_element4_in_d_d11_d1 ), .Iout_d_d12_d0 (Ififo_element4_in_d_d12_d0 ), .Iout_d_d12_d1 (Ififo_element4_in_d_d12_d1 ), .Iout_a (Ififo_element4_in_a ), .Iout_v (Ififo_element4_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Ififo_element4 (.Iin_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iin_d_d7_d0 (Ififo_element4_in_d_d7_d0 ), .Iin_d_d7_d1 (Ififo_element4_in_d_d7_d1 ), .Iin_d_d8_d0 (Ififo_element4_in_d_d8_d0 ), .Iin_d_d8_d1 (Ififo_element4_in_d_d8_d1 ), .Iin_d_d9_d0 (Ififo_element4_in_d_d9_d0 ), .Iin_d_d9_d1 (Ififo_element4_in_d_d9_d1 ), .Iin_d_d10_d0 (Ififo_element4_in_d_d10_d0 ), .Iin_d_d10_d1 (Ififo_element4_in_d_d10_d1 ), .Iin_d_d11_d0 (Ififo_element4_in_d_d11_d0 ), .Iin_d_d11_d1 (Ififo_element4_in_d_d11_d1 ), .Iin_d_d12_d0 (Ififo_element4_in_d_d12_d0 ), .Iin_d_d12_d1 (Ififo_element4_in_d_d12_d1 ), .Iin_a (Ififo_element4_in_a ), .Iin_v (Ififo_element4_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_d_d7_d0 (Iout_d_d7_d0 ), .Iout_d_d7_d1 (Iout_d_d7_d1 ), .Iout_d_d8_d0 (Iout_d_d8_d0 ), .Iout_d_d8_d1 (Iout_d_d8_d1 ), .Iout_d_d9_d0 (Iout_d_d9_d0 ), .Iout_d_d9_d1 (Iout_d_d9_d1 ), .Iout_d_d10_d0 (Iout_d_d10_d0 ), .Iout_d_d10_d1 (Iout_d_d10_d1 ), .Iout_d_d11_d0 (Iout_d_d11_d0 ), .Iout_d_d11_d1 (Iout_d_d11_d1 ), .Iout_d_d12_d0 (Iout_d_d12_d0 ), .Iout_d_d12_d1 (Iout_d_d12_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
endmodule

480
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_329_73_4/netlist/verilog.v

@ -124,249 +124,249 @@ module tmpl_0_0dataflow__neuro_0_0fifo_329_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
input reset_B;
// -- signals ---
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element1_in_d_d22_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d_d10_d0 ;
wire Ififo_element1_in_d_d27_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d2_d1 ;
wire Ififo_element2_in_d_d19_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
output Iin_v ;
wire Ififo_element1_in_d_d24_d0 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element1_in_d_d25_d1 ;
wire Ififo_element2_in_a ;
wire Iin_d_d4_d1 ;
wire Iin_d_d12_d1 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Ififo_element1_in_d_d19_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d3_d0 ;
wire Ififo_element2_in_d_d14_d1 ;
wire Iin_d_d1_d0 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d23_d0 ;
output Iout_d_d17_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element1_in_d_d27_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d12_d0 ;
wire Ififo_element2_in_d_d24_d1 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Iin_d_d1_d1 ;
wire Ififo_element1_in_v ;
wire Ififo_element2_in_d_d12_d1 ;
wire Iin_d_d9_d0 ;
output Iout_d_d21_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d18_d1 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element2_in_d_d0_d0 ;
output Iout_d_d6_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Iin_d_d27_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_d_d15_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d0_d0 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d8_d1 ;
output Iout_d_d21_d1 ;
output Iout_d_d7_d0 ;
wire Iin_d_d11_d1 ;
wire Ififo_element1_in_d_d21_d0 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d25_d0 ;
wire Iin_d_d0_d1 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
wire _reset_BX ;
wire Iin_d_d0_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d15_d0 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Ififo_element1_in_d_d28_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d3_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d17_d1 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Iin_d_d4_d0 ;
wire Ififo_element1_in_d_d22_d1 ;
output Iout_d_d4_d1 ;
wire Ififo_element2_in_d_d7_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d26_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Ififo_element1_in_d_d26_d1 ;
wire Ififo_element2_in_d_d21_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d23_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Ififo_element2_in_d_d26_d1 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d5_d1 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Iin_d_d24_d1 ;
output Iin_a ;
wire Ififo_element1_in_d_d24_d1 ;
output Iout_d_d9_d0 ;
wire I_reset_BXX2 ;
wire Iin_d_d7_d0 ;
wire Ififo_element1_in_d_d14_d0 ;
wire Iout_v ;
wire Ififo_element1_in_d_d15_d1 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d20_d0 ;
wire Ififo_element1_in_d_d13_d1 ;
output Iout_d_d12_d1 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d26_d1 ;
wire Ififo_element1_in_d_d20_d1 ;
output Iout_d_d22_d1 ;
wire Ififo_element2_in_d_d13_d0 ;
wire Iin_d_d17_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_d_d18_d1 ;
output Iout_d_d26_d1 ;
wire Ififo_element2_in_d_d20_d1 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element1_in_d_d23_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d20_d0 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d18_d0 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element1_in_d_d16_d0 ;
wire Ififo_element1_in_a ;
output Iout_d_d27_d1 ;
wire Ififo_element2_in_d_d16_d0 ;
wire Ififo_element1_in_d_d17_d0 ;
output Iout_d_d13_d0 ;
output Iout_d_d2_d0 ;
wire Ififo_element2_in_d_d25_d1 ;
wire Ififo_element2_in_d_d24_d0 ;
output Iout_d_d10_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d23_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Iin_d_d20_d1 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Iin_d_d23_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element1_in_d_d13_d0 ;
wire Ififo_element1_in_d_d25_d0 ;
output Iout_d_d16_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d25_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
output Iout_d_d16_d0 ;
output Iout_d_d3_d1 ;
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d15_d1 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
output Iout_d_d13_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element1_in_d_d14_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d19_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
output Iout_d_d26_d0 ;
wire Ififo_element2_in_d_d18_d0 ;
wire Iin_d_d2_d0 ;
wire Ififo_element1_in_d_d16_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d6_d1 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element2_in_d_d22_d1 ;
wire reset_B;
wire Iin_d_d21_d1 ;
wire Iin_d_d28_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
output Iout_d_d22_d0 ;
wire Ififo_element1_in_d_d28_d1 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Ififo_element1_in_d_d18_d0 ;
wire Ififo_element2_in_d_d17_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d15_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
output Iout_d_d7_d1 ;
wire Ififo_element2_in_d_d17_d1 ;
wire Ififo_element2_in_d_d15_d0 ;
wire Iin_d_d28_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Ififo_element2_in_d_d26_d0 ;
wire Iin_d_d13_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
output Iout_d_d8_d0 ;
wire Ififo_element2_in_d_d15_d1 ;
output Iout_d_d8_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Iin_d_d27_d1 ;
wire Iout_a ;
output Iout_d_d19_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d1_d1 ;
wire Ififo_element2_in_d_d22_d0 ;
output Iout_d_d25_d1 ;
output Iout_d_d11_d1 ;
wire Iin_d_d21_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
output Iout_d_d28_d0 ;
output Iout_d_d11_d0 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Ififo_element1_in_d_d21_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d19_d1 ;
wire Ififo_element2_in_d_d27_d0 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Ififo_element2_in_d_d16_d1 ;
wire Ififo_element2_in_d_d14_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d14_d1 ;
wire Iin_d_d14_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d20_d0 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Iin_d_d8_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d13_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d24_d1 ;
wire Ififo_element1_in_d_d17_d0 ;
output Iout_d_d24_d1 ;
wire Ififo_element1_in_d_d15_d1 ;
output Iout_d_d26_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d0_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element1_in_d_d14_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d9_d1 ;
wire Ififo_element2_in_d_d18_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element1_in_d_d15_d0 ;
wire Ififo_element1_in_d_d24_d1 ;
wire Ififo_element1_in_d_d25_d0 ;
output Iout_d_d20_d1 ;
wire Iin_d_d0_d0 ;
wire Ififo_element1_in_d_d23_d0 ;
output Iout_d_d23_d1 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Iin_d_d16_d1 ;
output Iin_a ;
wire Ififo_element2_in_d_d25_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d16_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d8_d1 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Iin_d_d25_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element1_in_d_d28_d1 ;
output Iout_d_d28_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d15_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d5_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element1_in_d_d26_d1 ;
wire Ififo_element1_in_v ;
wire Iin_d_d10_d0 ;
wire Ififo_element2_in_d_d14_d0 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Iin_d_d27_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d14_d1 ;
output Iout_d_d20_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d26_d1 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d20_d1 ;
output Iin_v ;
output Iout_d_d2_d1 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element1_in_d_d13_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d3_d0 ;
wire Ififo_element2_in_d_d25_d0 ;
wire Ififo_element2_in_d_d15_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d28_d1 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Iin_d_d10_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d22_d1 ;
wire Ififo_element2_in_d_d24_d1 ;
wire _reset_BX ;
wire Iin_d_d17_d1 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element2_in_d_d14_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Iin_d_d20_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element1_in_d_d25_d1 ;
wire Ififo_element2_in_d_d27_d0 ;
wire Ififo_element2_in_d_d26_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d22_d0 ;
wire Ififo_element1_in_d_d18_d1 ;
wire Ififo_element2_in_d_d22_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d_d26_d1 ;
wire Ififo_element2_in_d_d7_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
wire I_reset_BXX2 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Ififo_element1_in_d_d18_d0 ;
output Iout_d_d8_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Iin_d_d25_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
output Iout_d_d27_d1 ;
wire Iin_d_d20_d1 ;
wire Ififo_element1_in_d_d21_d1 ;
output Iout_d_d27_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d11_d0 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Iin_d_d3_d0 ;
wire Ififo_element1_in_d_d16_d0 ;
output Iout_d_d22_d0 ;
wire Ififo_element2_in_d_d22_d1 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Ififo_element2_in_d_d13_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
wire Ififo_element1_in_d_d20_d0 ;
wire Ififo_element1_in_d_d24_d0 ;
wire Ififo_element1_in_d_d28_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d1_d1 ;
wire Ififo_element2_in_d_d24_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d18_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element2_in_d_d19_d0 ;
wire Ififo_element2_in_d_d18_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Iin_d_d12_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Iin_d_d21_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
output Iout_d_d12_d1 ;
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d9_d0 ;
wire Iout_v ;
output Iout_d_d17_d0 ;
output Iout_d_d16_d0 ;
wire Ififo_element2_in_d_d17_d0 ;
wire Ififo_element2_in_d_d16_d1 ;
wire Ififo_element1_in_d_d22_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d2_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d15_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d13_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
output Iout_d_d7_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d4_d1 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Ififo_element2_in_d_d15_d1 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d19_d1 ;
wire Ififo_element1_in_d_d14_d1 ;
output Iout_d_d12_d0 ;
wire Ififo_element2_in_d_d17_d1 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Ififo_element1_in_d_d9_d1 ;
output Iout_d_d17_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Iin_d_d24_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element1_in_d_d21_d0 ;
output Iout_d_d11_d0 ;
wire Iin_d_d14_d0 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Iout_a ;
output Iout_d_d19_d1 ;
output Iout_d_d5_d1 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element1_in_d_d26_d0 ;
output Iout_d_d7_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_a ;
output Iout_d_d13_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d28_d1 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Iin_d_d7_d0 ;
wire Ififo_element1_in_d_d27_d0 ;
output Iout_d_d21_d0 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d23_d0 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
wire reset_B;
wire Iin_d_d12_d0 ;
wire Ififo_element1_in_d_d19_d1 ;
wire Ififo_element1_in_d_d20_d1 ;
wire Ififo_element1_in_d_d22_d0 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element2_in_d_d26_d1 ;
wire Ififo_element2_in_d_d10_d1 ;
output Iout_d_d14_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element2_in_a ;
wire Ififo_element2_in_d_d21_d0 ;
wire Iin_d_d6_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_329_75_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

499
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_329_75_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

486
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_330_73_4/netlist/verilog.v

@ -128,257 +128,257 @@ module tmpl_0_0dataflow__neuro_0_0fifo_330_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
input reset_B;
// -- signals ---
wire Iin_d_d18_d1 ;
output Iout_d_d28_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element2_in_d_d26_d1 ;
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element1_in_d_d20_d1 ;
output Iout_d_d11_d0 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d10_d1 ;
wire Ififo_element2_in_d_d25_d1 ;
wire Ififo_element2_in_d_d19_d1 ;
output Iout_d_d12_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Ififo_element2_in_d_d13_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d22_d1 ;
wire Ififo_element1_in_d_d8_d0 ;
output Iout_d_d21_d0 ;
wire Ififo_element2_in_d_d15_d1 ;
wire Ififo_element1_in_d_d9_d1 ;
output Iout_d_d22_d1 ;
wire Ififo_element1_in_d_d14_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d12_d1 ;
wire Ififo_element2_in_d_d29_d1 ;
wire Iin_d_d2_d0 ;
wire Iout_a ;
output Iout_d_d8_d1 ;
output Iout_d_d4_d1 ;
wire Ififo_element2_in_d_d25_d0 ;
output Iin_v ;
output Iout_d_d24_d1 ;
output Iout_d_d20_d1 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Ififo_element2_in_d_d14_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d19_d1 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element1_in_d_d13_d0 ;
output Iout_d_d13_d0 ;
wire Ififo_element2_in_d_d24_d0 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d17_d1 ;
wire Ififo_element1_in_d_d25_d1 ;
output Iout_d_d13_d1 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Ififo_element2_in_d_d20_d1 ;
wire Ififo_element1_in_d_d17_d0 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element2_in_d_d16_d1 ;
wire Iin_d_d14_d1 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Iin_d_d29_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
output Iout_d_d29_d1 ;
wire Ififo_element2_in_d_d24_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d28_d0 ;
wire Ififo_element1_in_d_d21_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d17_d0 ;
wire Iin_d_d12_d1 ;
wire Ififo_element1_in_a ;
output Iout_d_d9_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
output Iout_d_d22_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d17_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element1_in_d_d19_d0 ;
output Iout_d_d3_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Iin_d_d7_d0 ;
wire Ififo_element1_in_d_d24_d1 ;
output Iout_d_d20_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d11_d1 ;
wire Ififo_element2_in_d_d29_d0 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Iin_d_d24_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Ififo_element1_in_d_d11_d1 ;
output Iout_d_d16_d0 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element1_in_d_d3_d1 ;
output Iout_d_d8_d0 ;
wire Iin_d_d20_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_d_d16_d0 ;
wire Ififo_element2_in_d_d18_d0 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element2_in_d_d26_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d6_d0 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Ififo_element2_in_d_d16_d0 ;
wire Ififo_element1_in_d_d12_d1 ;
wire Ififo_element2_in_d_d15_d0 ;
wire Iin_d_d24_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
output Iout_d_d9_d0 ;
wire Ififo_element1_in_d_d7_d1 ;
output Iout_d_d26_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d7_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element1_in_d_d14_d1 ;
wire Ififo_element1_in_d_d18_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d14_d1 ;
output Iout_d_d6_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d17_d0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d15_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d5_d0 ;
wire Ififo_element2_in_d_d22_d0 ;
wire Iin_d_d8_d1 ;
wire Ififo_element1_in_d_d28_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d12_d0 ;
wire Ififo_element1_in_d_d25_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d11_d0 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element1_in_d_d21_d1 ;
wire Ififo_element1_in_d_d22_d1 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d20_d1 ;
wire Ififo_element1_in_d_d21_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d9_d0 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Ififo_element2_in_d_d18_d0 ;
wire I_reset_BXX2 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d_d19_d0 ;
output Iout_d_d1_d1 ;
wire _reset_BX ;
wire Iin_d_d0_d0 ;
wire Iin_d_d25_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element1_in_d_d27_d0 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d15_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Ififo_element1_in_d_d13_d1 ;
wire Ififo_element2_in_d_d21_d0 ;
wire Ififo_element1_in_d_d12_d0 ;
output Iout_d_d2_d0 ;
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element2_in_d_d18_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element1_in_d_d23_d0 ;
wire Ififo_element2_in_a ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element1_in_d_d22_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d16_d1 ;
output Iout_d_d21_d1 ;
wire Iin_d_d25_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element1_in_d_d22_d1 ;
output Iout_d_d29_d0 ;
wire Ififo_element2_in_d_d19_d0 ;
wire reset_B;
wire Iin_d_d13_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d1_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Iin_d_d26_d0 ;
wire Ififo_element1_in_d_d20_d0 ;
output Iout_d_d2_d1 ;
wire Ififo_element2_in_d_d27_d0 ;
wire Iin_d_d26_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element1_in_d_d28_d1 ;
wire Iout_v ;
wire Iin_d_d23_d0 ;
wire Iin_d_d27_d1 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Ififo_element2_in_d_d22_d1 ;
wire I_reset_BXX2 ;
wire Iin_d_d29_d0 ;
wire Ififo_element1_in_d_d29_d1 ;
output Iout_d_d17_d1 ;
wire Ififo_element1_in_d_d24_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d5_d1 ;
wire Ififo_element2_in_d_d14_d0 ;
wire Iin_d_d2_d1 ;
output Iin_a ;
wire Ififo_element1_in_d_d26_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d21_d1 ;
wire Ififo_element1_in_d_d15_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d15_d1 ;
wire Iin_d_d27_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d15_d1 ;
wire Iin_d_d5_d0 ;
wire Ififo_element1_in_d_d25_d0 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Ififo_element2_in_d_d17_d1 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d16_d0 ;
output Iout_d_d23_d1 ;
wire Ififo_element1_in_d_d29_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d28_d1 ;
wire Ififo_element1_in_d_d18_d1 ;
wire Ififo_element1_in_v ;
output Iout_d_d10_d0 ;
output Iout_d_d22_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d9_d1 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d19_d1 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Ififo_element1_in_d_d19_d1 ;
output Iout_d_d23_d0 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Iin_d_d18_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element1_in_d_d21_d1 ;
output Iout_d_d0_d0 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
output Iout_d_d26_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d5_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d25_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Ififo_element2_in_d_d27_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element1_in_d_d24_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d16_d0 ;
wire Ififo_element2_in_d_d19_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
wire reset_B;
wire Iin_d_d8_d1 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Ififo_element1_in_d_d23_d0 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
output Iout_d_d15_d1 ;
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d6_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element1_in_d_d28_d1 ;
output Iout_d_d12_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d12_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element1_in_d_d17_d0 ;
wire Ififo_element1_in_a ;
output Iout_d_d28_d1 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d23_d1 ;
wire Ififo_element1_in_d_d14_d0 ;
wire Ififo_element1_in_d_d15_d0 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Iin_d_d2_d1 ;
wire Ififo_element1_in_v ;
output Iout_d_d26_d0 ;
output Iout_d_d11_d1 ;
wire Ififo_element2_in_d_d18_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d15_d1 ;
output Iin_v ;
wire Ififo_element1_in_d_d18_d1 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Iin_d_d27_d1 ;
wire Ififo_element2_in_a ;
wire Iin_d_d7_d0 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element1_in_d_d20_d0 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Ififo_element2_in_d_d17_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d28_d0 ;
wire Ififo_element1_in_d_d17_d1 ;
output Iout_d_d13_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element1_in_d_d25_d0 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Ififo_element2_in_d_d26_d0 ;
wire _reset_BX ;
output Iout_d_d7_d0 ;
wire Iin_d_d20_d0 ;
output Iin_a ;
output Iout_d_d25_d0 ;
output Iout_d_d24_d0 ;
wire Iin_d_d10_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d4_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d7_d1 ;
wire Ififo_element2_in_d_d16_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d19_d1 ;
wire Ififo_element2_in_d_d7_d1 ;
wire Iin_d_d4_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element1_in_d_d13_d1 ;
wire Ififo_element1_in_d_d14_d1 ;
wire Ififo_element1_in_d_d29_d0 ;
wire Ififo_element2_in_d_d14_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d25_d0 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d5_d0 ;
wire Iout_v ;
output Iout_d_d20_d0 ;
output Iout_d_d13_d0 ;
wire Ififo_element2_in_d_d29_d1 ;
wire Ififo_element2_in_d_d24_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d17_d1 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Iout_a ;
wire Ififo_element2_in_d_d15_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d16_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element1_in_d_d22_d0 ;
output Iout_d_d23_d1 ;
wire Iin_d_d14_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d8_d0 ;
wire Ififo_element2_in_d_d16_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
output Iout_d_d4_d0 ;
wire Iin_d_d24_d0 ;
output Iout_d_d21_d0 ;
output Iout_d_d17_d1 ;
wire Ififo_element2_in_d_d26_d1 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Ififo_element1_in_d_d7_d1 ;
output Iout_d_d28_d0 ;
output Iout_d_d11_d0 ;
wire Ififo_element2_in_d_d22_d0 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d_d17_d0 ;
wire Ififo_element2_in_d_d24_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d16_d0 ;
wire Ififo_element1_in_d_d15_d1 ;
wire Ififo_element2_in_d_d21_d0 ;
wire Iin_d_d9_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Iin_d_d18_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d23_d0 ;
output Iout_d_d19_d0 ;
wire Ififo_element2_in_d_d15_d1 ;
wire Iin_d_d19_d0 ;
wire Ififo_element1_in_d_d18_d0 ;
wire Ififo_element1_in_d_d19_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Iin_d_d9_d1 ;
wire Ififo_element1_in_d_d24_d0 ;
output Iout_d_d22_d0 ;
wire Ififo_element2_in_d_d25_d1 ;
wire Ififo_element2_in_d_d13_d0 ;
wire Iin_d_d10_d1 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
output Iout_d_d2_d0 ;
wire Ififo_element2_in_d_d20_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element1_in_d_d28_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d0_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d_d27_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d14_d1 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Iin_d_d7_d1 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Ififo_element1_in_d_d26_d1 ;
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element2_in_d_d25_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d29_d1 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Iin_d_d17_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Ififo_element2_in_d_d17_d0 ;
wire Ififo_element2_in_d_d14_d1 ;
wire Iin_d_d21_d0 ;
output Iout_d_d3_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d21_d1 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Ififo_element2_in_d_d22_d1 ;
wire Ififo_element1_in_d_d29_d1 ;
output Iout_d_d14_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d1_d1 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d29_d0 ;
wire Iin_d_d0_d0 ;
wire Ififo_element1_in_d_d20_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d3_d0 ;
wire Ififo_element1_in_d_d16_d0 ;
output Iout_d_d21_d1 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Iin_d_d29_d0 ;
wire Ififo_element1_in_d_d12_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d22_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_330_75_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

515
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_330_75_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

492
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_331_73_4/netlist/verilog.v

@ -132,265 +132,265 @@ module tmpl_0_0dataflow__neuro_0_0fifo_331_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
input reset_B;
// -- signals ---
wire Iin_d_d13_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d17_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Iin_d_d19_d1 ;
wire Ififo_element1_in_v ;
wire Ififo_element1_in_d_d18_d1 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d9_d0 ;
wire Ififo_element2_in_d_d18_d1 ;
output Iout_d_d28_d1 ;
wire Iout_a ;
output Iout_d_d6_d0 ;
output Iout_d_d22_d0 ;
wire Ififo_element1_in_d_d23_d0 ;
wire Ififo_element1_in_d_d17_d0 ;
wire Ififo_element2_in_d_d14_d0 ;
wire Ififo_element1_in_d_d27_d0 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d24_d1 ;
wire Ififo_element1_in_d_d21_d1 ;
wire Ififo_element1_in_d_d20_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element2_in_d_d6_d0 ;
output Iout_d_d8_d1 ;
wire Ififo_element1_in_d_d13_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d23_d1 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d1_d0 ;
wire Ififo_element2_in_d_d26_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Ififo_element1_in_d_d21_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d5_d0 ;
wire Iin_d_d25_d0 ;
wire Ififo_element1_in_d_d1_d0 ;
output Iout_d_d4_d0 ;
output Iout_d_d15_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d4_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d13_d0 ;
output Iout_d_d16_d0 ;
wire Ififo_element1_in_d_d24_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d0_d0 ;
wire Iout_v ;
wire Iin_d_d15_d1 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Ififo_element1_in_v ;
wire Ififo_element2_in_d_d23_d0 ;
wire Ififo_element2_in_d_d24_d0 ;
wire Ififo_element1_in_d_d28_d1 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element2_in_d_d21_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d26_d1 ;
wire Ififo_element1_in_d_d26_d1 ;
output Iout_d_d6_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d8_d1 ;
wire Iin_d_d10_d0 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d17_d1 ;
output Iout_d_d13_d1 ;
wire Ififo_element2_in_d_d20_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element2_in_d_d1_d1 ;
output Iin_a ;
output Iout_d_d30_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Iin_d_d21_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d16_d1 ;
wire Ififo_element2_in_d_d14_d1 ;
output Iout_d_d3_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d29_d1 ;
wire Ififo_element1_in_d_d27_d0 ;
wire Iin_d_d6_d0 ;
wire reset_B;
wire Ififo_element2_in_d_d18_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d10_d0 ;
wire Ififo_element1_in_d_d25_d1 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Ififo_element2_in_d_d25_d0 ;
output Iout_d_d27_d0 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Iin_d_d2_d0 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d29_d0 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Iin_d_d21_d1 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element1_in_d_d8_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d14_d1 ;
wire Ififo_element2_in_d_d29_d1 ;
wire Ififo_element1_in_d_d13_d1 ;
output Iin_v ;
wire Ififo_element2_in_d_d27_d0 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Iin_d_d13_d0 ;
wire Ififo_element2_in_d_d22_d0 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Iin_d_d25_d0 ;
wire Ififo_element2_in_d_d19_d0 ;
output Iout_d_d2_d0 ;
wire Iin_d_d12_d1 ;
wire Ififo_element1_in_d_d15_d1 ;
output Iout_d_d0_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element2_in_v ;
wire Iout_a ;
wire Ififo_element2_in_d_d17_d1 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Ififo_element2_in_d_d22_d1 ;
output Iout_d_d26_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d11_d0 ;
wire Ififo_element1_in_d_d29_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d28_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d5_d1 ;
wire I_reset_BXX2 ;
wire Ififo_element2_in_d_d15_d0 ;
wire Ififo_element2_in_d_d16_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d22_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d18_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
output Iout_d_d9_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d23_d1 ;
wire Ififo_element1_in_d_d24_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d16_d0 ;
wire _reset_BX ;
output Iout_d_d27_d1 ;
wire Iin_d_d25_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d19_d0 ;
wire Iin_d_d19_d0 ;
output Iout_d_d7_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Iin_d_d20_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element2_in_d_d7_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d27_d0 ;
wire Iout_v ;
wire Ififo_element1_in_d_d20_d1 ;
wire Iin_d_d3_d1 ;
wire Ififo_element1_in_d_d22_d1 ;
wire Ififo_element1_in_d_d18_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element2_in_d_d30_d0 ;
output Iout_d_d28_d1 ;
wire Iin_d_d22_d0 ;
wire Ififo_element2_in_d_d9_d1 ;
output Iout_d_d9_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d30_d1 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Ififo_element2_in_d_d24_d1 ;
wire Ififo_element2_in_d_d25_d1 ;
wire Ififo_element1_in_d_d19_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Ififo_element1_in_d_d22_d0 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Ififo_element2_in_d_d14_d0 ;
output Iout_d_d17_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
output Iout_d_d20_d0 ;
wire Ififo_element1_in_d_d25_d0 ;
wire Iin_d_d8_d0 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Iin_d_d9_d1 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element1_in_d_d18_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Ififo_element2_in_d_d12_d1 ;
wire Ififo_element1_in_d_d29_d0 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Iin_d_d20_d1 ;
wire Ififo_element2_in_d_d18_d0 ;
wire Ififo_element1_in_d_d17_d0 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Ififo_element1_in_d_d16_d0 ;
wire Iin_d_d18_d1 ;
wire Ififo_element2_in_d_d15_d1 ;
output Iout_d_d21_d0 ;
wire Ififo_element1_in_d_d23_d0 ;
wire Ififo_element2_in_d_d26_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
output Iout_d_d24_d1 ;
wire Iin_d_d18_d0 ;
wire Ififo_element2_in_a ;
output Iout_d_d22_d1 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Ififo_element1_in_d_d7_d1 ;
output Iout_d_d1_d0 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d29_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Iin_d_d11_d1 ;
output Iout_d_d17_d0 ;
output Iout_d_d18_d0 ;
wire Ififo_element1_in_d_d14_d1 ;
wire Ififo_element2_in_d_d16_d1 ;
wire Iin_d_d1_d0 ;
wire Ififo_element1_in_a ;
wire Ififo_element2_in_d_d26_d1 ;
wire Ififo_element1_in_d_d13_d0 ;
wire Ififo_element2_in_d_d30_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d25_d1 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Iin_d_d7_d1 ;
wire Ififo_element1_in_d_d14_d0 ;
wire Iin_d_d14_d0 ;
wire Ififo_element1_in_d_d15_d0 ;
wire Ififo_element1_in_d_d21_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d26_d1 ;
wire Iin_d_d17_d0 ;
output Iout_d_d4_d1 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d7_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d0_d1 ;
wire Ififo_element2_in_d_d17_d0 ;
wire Iin_d_d11_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element1_in_d_d7_d1 ;
output Iout_d_d25_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Iin_d_d29_d1 ;
wire Iin_d_d29_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d11_d1 ;
wire Ififo_element1_in_d_d12_d1 ;
wire Iin_d_d7_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire I_reset_BXX2 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d2_d1 ;
wire Ififo_element2_in_d_d10_d0 ;
output Iout_d_d28_d0 ;
wire Ififo_element1_in_d_d25_d0 ;
wire Ififo_element2_in_d_d0_d0 ;
output Iout_d_d21_d1 ;
wire Ififo_element1_in_d_d20_d0 ;
wire Iin_d_d13_d0 ;
output Iout_d_d7_d0 ;
output Iin_v ;
wire Iin_d_d30_d0 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Ififo_element2_in_d_d27_d1 ;
output Iout_d_d24_d1 ;
wire Iin_d_d21_d0 ;
wire Ififo_element2_in_d_d22_d0 ;
output Iout_d_d27_d1 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
output Iout_d_d6_d1 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Iin_d_d27_d1 ;
output Iout_d_d22_d1 ;
wire Ififo_element2_in_a ;
output Iout_d_d12_d0 ;
output Iout_d_d26_d0 ;
wire Ififo_element1_in_d_d14_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Iin_d_d22_d1 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Iin_d_d27_d0 ;
wire reset_B;
wire Ififo_element2_in_d_d2_d1 ;
output Iout_d_d7_d1 ;
wire Ififo_element1_in_d_d29_d1 ;
wire Iin_d_d30_d1 ;
output Iout_d_d15_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Ififo_element2_in_d_d24_d0 ;
wire Iin_d_d12_d1 ;
wire Iin_d_d8_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
output Iout_d_d13_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d19_d1 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Iin_d_d8_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d20_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d2_d0 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d9_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Iin_d_d1_d1 ;
output Iin_a ;
output Iout_d_d3_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d30_d0 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Iin_d_d11_d1 ;
wire _reset_BX ;
output Iout_d_d17_d1 ;
output Iout_d_d18_d0 ;
wire Iin_d_d20_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
wire Ififo_element2_in_d_d29_d0 ;
output Iout_d_d26_d1 ;
wire Ififo_element1_in_d_d20_d1 ;
wire Iin_d_d19_d0 ;
wire Ififo_element2_in_d_d16_d1 ;
output Iout_d_d0_d1 ;
output Iout_d_d11_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d3_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d15_d0 ;
wire Ififo_element2_in_d_d30_d0 ;
output Iout_d_d9_d1 ;
wire Ififo_element1_in_d_d15_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d16_d1 ;
output Iout_d_d27_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Ififo_element1_in_d_d16_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Ififo_element1_in_d_d22_d0 ;
wire Ififo_element2_in_d_d1_d0 ;
output Iout_d_d23_d0 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Iin_d_d28_d0 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Ififo_element1_in_d_d15_d1 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_a ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element2_in_d_d16_d0 ;
output Iout_d_d25_d1 ;
wire Iin_d_d25_d1 ;
wire Ififo_element2_in_d_d9_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d8_d0 ;
wire Iin_d_d28_d1 ;
output Iout_d_d24_d0 ;
wire Ififo_element1_in_d_d13_d0 ;
wire Iin_d_d17_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element2_in_d_d13_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d11_d1 ;
output Iout_d_d29_d0 ;
wire Iin_d_d8_d1 ;
output Iout_d_d1_d1 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Ififo_element1_in_d_d30_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Iin_d_d16_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d15_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element2_in_d_d26_d0 ;
wire Ififo_element1_in_d_d25_d1 ;
wire Ififo_element2_in_d_d27_d0 ;
wire Ififo_element1_in_d_d18_d0 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Ififo_element2_in_d_d21_d0 ;
wire Iin_d_d7_d1 ;
wire Ififo_element2_in_d_d4_d0 ;
output Iout_d_d21_d0 ;
wire Ififo_element1_in_d_d14_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d18_d0 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Iin_d_d16_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
output Iout_d_d16_d0 ;
wire Ififo_element2_in_d_d9_d0 ;
wire Iin_d_d24_d1 ;
wire Ififo_element2_in_d_d7_d1 ;
wire Ififo_element1_in_d_d29_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d14_d0 ;
wire Ififo_element2_in_d_d19_d0 ;
output Iout_d_d13_d0 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Ififo_element2_in_d_d22_d1 ;
wire Ififo_element2_in_d_d14_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d_d14_d1 ;
output Iout_d_d17_d0 ;
wire Ififo_element1_in_d_d30_d1 ;
wire Ififo_element1_in_d_d22_d1 ;
wire Ififo_element2_in_d_d25_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d12_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d19_d1 ;
wire Ififo_element1_in_d_d28_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Iin_d_d26_d1 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Iin_d_d6_d1 ;
wire Ififo_element2_in_d_d17_d1 ;
output Iout_d_d29_d1 ;
wire Ififo_element1_in_d_d26_d1 ;
wire Ififo_element1_in_d_d24_d1 ;
wire Iin_d_d3_d1 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element1_in_d_d24_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d30_d1 ;
wire Ififo_element1_in_d_d19_d1 ;
wire Ififo_element2_in_d_d15_d1 ;
wire Ififo_element1_in_d_d21_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d20_d1 ;
wire Ififo_element2_in_d_d20_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d12_d1 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element2_in_d_d25_d1 ;
wire Ififo_element2_in_d_d24_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d9_d0 ;
wire Iin_d_d14_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d28_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Iin_d_d5_d0 ;
output Iout_d_d8_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_331_75_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

531
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_331_75_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

522
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_332_73_4/netlist/verilog.v

@ -136,273 +136,273 @@ module tmpl_0_0dataflow__neuro_0_0fifo_332_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
input reset_B;
// -- signals ---
wire Ififo_element1_in_d_d28_d0 ;
wire Ififo_element1_in_d_d15_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
output Iout_d_d8_d1 ;
wire Ififo_element1_in_d_d13_d0 ;
output Iout_d_d16_d0 ;
wire Ififo_element1_in_d_d18_d1 ;
wire Iin_d_d26_d0 ;
wire Ififo_element2_in_d_d20_d0 ;
wire Iin_d_d10_d1 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
output Iout_d_d25_d0 ;
wire Iin_d_d24_d0 ;
output Iout_d_d22_d0 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d20_d1 ;
wire Ififo_element1_in_d_d30_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d8_d1 ;
wire Ififo_element2_in_d_d21_d0 ;
output Iout_d_d20_d1 ;
wire Ififo_element1_in_d_d21_d1 ;
wire Ififo_element1_in_d_d16_d0 ;
wire Ififo_element2_in_d_d30_d1 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d18_d1 ;
wire Ififo_element2_in_d_d26_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d1_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d31_d1 ;
wire Ififo_element1_in_d_d14_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Iin_d_d26_d1 ;
output Iout_d_d3_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element2_in_d_d15_d1 ;
wire Iin_d_d31_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element2_in_d_d17_d1 ;
wire Ififo_element2_in_d_d7_d0 ;
wire Ififo_element2_in_d_d22_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d10_d1 ;
wire Iin_d_d8_d0 ;
wire Ififo_element2_in_d_d14_d0 ;
output Iout_d_d28_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d28_d1 ;
output Iout_d_d14_d1 ;
wire Ififo_element1_in_d_d24_d1 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Iin_d_d28_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element1_in_d_d19_d1 ;
wire Ififo_element2_in_d_d18_d1 ;
wire Ififo_element2_in_d_d19_d0 ;
output Iout_d_d7_d1 ;
output Iout_d_d27_d0 ;
wire Iin_d_d27_d1 ;
wire Ififo_element2_in_a ;
output Iout_d_d30_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d5_d1 ;
wire Ififo_element2_in_d_d2_d1 ;
output Iout_d_d15_d1 ;
wire Ififo_element2_in_d_d27_d0 ;
output Iout_d_d22_d1 ;
wire reset_B;
wire Ififo_element1_in_d_d20_d0 ;
wire Ififo_element1_in_d_d31_d0 ;
wire Ififo_element2_in_d_d9_d0 ;
output Iout_d_d4_d1 ;
wire Ififo_element1_in_d_d22_d0 ;
wire Ififo_element1_in_d_d9_d1 ;
output Iout_d_d17_d0 ;
wire Ififo_element1_in_d_d26_d1 ;
wire Iin_d_d15_d1 ;
output Iout_d_d20_d0 ;
wire Ififo_element2_in_d_d25_d0 ;
wire Iin_d_d29_d1 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d26_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d31_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d28_d1 ;
output Iout_d_d12_d1 ;
wire Ififo_element1_in_d_d13_d1 ;
wire Ififo_element2_in_d_d29_d0 ;
wire Ififo_element1_in_d_d21_d0 ;
wire Ififo_element1_in_d_d18_d0 ;
wire Ififo_element1_in_d_d31_d1 ;
wire Ififo_element2_in_d_d20_d1 ;
output Iout_d_d29_d0 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Iin_d_d13_d1 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Iin_d_d6_d0 ;
wire Ififo_element2_in_d_d17_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d_d9_d0 ;
wire Ififo_element1_in_d_d15_d0 ;
output Iout_d_d11_d0 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Ififo_element2_in_d_d15_d0 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d3_d1 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Iin_d_d0_d0 ;
wire Ififo_element2_in_d_d8_d0 ;
output Iout_d_d5_d0 ;
output Iout_d_d11_d1 ;
output Iout_d_d26_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
output Iout_d_d13_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Iin_d_d9_d1 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element1_in_d_d8_d1 ;
wire Iin_d_d19_d1 ;
wire Ififo_element2_in_d_d9_d1 ;
output Iout_d_d23_d1 ;
wire Iin_d_d14_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
output Iout_d_d21_d0 ;
wire Iout_v ;
wire Ififo_element1_in_d_d22_d1 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Iin_d_d21_d1 ;
wire Ififo_element2_in_d_d5_d1 ;
output Iout_d_d14_d0 ;
wire Ififo_element1_in_d_d11_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element1_in_d_d28_d1 ;
wire Iin_d_d0_d1 ;
output Iout_d_d17_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d2_d0 ;
wire Ififo_element2_in_d_d31_d0 ;
wire Ififo_element1_in_d_d17_d0 ;
wire Ififo_element2_in_d_d21_d1 ;
wire Ififo_element2_in_d_d25_d1 ;
wire Ififo_element2_in_d_d30_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d13_d1 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d12_d1 ;
wire Ififo_element1_in_d_d27_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d18_d0 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Ififo_element1_in_v ;
wire Ififo_element1_in_d_d3_d1 ;
wire Iin_d_d18_d1 ;
output Iout_d_d7_d0 ;
wire Ififo_element1_in_d_d25_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d18_d0 ;
output Iout_d_d0_d0 ;
output Iout_d_d24_d1 ;
wire Ififo_element1_in_d_d14_d0 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_d_d24_d0 ;
wire Ififo_element1_in_d_d12_d1 ;
wire Iin_d_d27_d0 ;
wire Ififo_element1_in_d_d17_d0 ;
wire Iin_d_d5_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Iin_d_d0_d0 ;
output Iout_d_d10_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d_d3_d0 ;
wire Ififo_element1_in_d_d21_d1 ;
wire Ififo_element1_in_d_d8_d0 ;
wire Iin_d_d3_d1 ;
wire Ififo_element1_in_d_d16_d0 ;
wire Iin_d_d25_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
output Iout_d_d19_d1 ;
wire Iin_d_d4_d1 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Iin_d_d18_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element1_in_d_d23_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Iin_d_d14_d0 ;
wire Ififo_element2_in_d_d14_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d21_d1 ;
wire Ififo_element1_in_d_d29_d1 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d_d6_d0 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Iin_d_d17_d1 ;
wire _reset_BX ;
output Iout_d_d2_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d9_d0 ;
wire Ififo_element2_in_d_d29_d1 ;
wire Ififo_element1_in_d_d20_d1 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d12_d0 ;
wire Ififo_element2_in_d_d31_d1 ;
wire Iin_d_d29_d0 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Iin_d_d17_d0 ;
wire Ififo_element2_in_d_d24_d1 ;
wire Ififo_element1_in_d_d29_d0 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
output Iout_d_d19_d0 ;
output Iout_d_d28_d0 ;
wire Ififo_element2_in_d_d16_d1 ;
output Iout_d_d10_d0 ;
wire Ififo_element2_in_d_d13_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
output Iout_d_d27_d1 ;
wire Ififo_element1_in_d_d30_d0 ;
wire Ififo_element2_in_d_d23_d1 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Iin_d_d16_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
output Iout_d_d26_d1 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Iin_d_d7_d0 ;
wire I_reset_BXX2 ;
wire Iin_d_d25_d1 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Ififo_element1_in_a ;
wire Ififo_element2_in_d_d7_d1 ;
output Iout_d_d29_d1 ;
wire Ififo_element1_in_d_d25_d1 ;
wire Ififo_element2_in_d_d12_d0 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element2_in_d_d11_d0 ;
output Iout_d_d25_d1 ;
wire Ififo_element2_in_d_d22_d0 ;
output Iout_d_d9_d1 ;
wire Iout_a ;
wire Ififo_element2_in_d_d12_d1 ;
output Iout_d_d15_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d16_d1 ;
wire Iin_d_d3_d0 ;
output Iout_d_d24_d0 ;
output Iout_d_d31_d0 ;
output Iin_v ;
output Iin_a ;
wire Ififo_element2_in_d_d24_d0 ;
wire Iin_d_d13_d0 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element1_in_d_d29_d1 ;
wire Iin_d_d31_d0 ;
wire Ififo_element1_in_d_d30_d1 ;
wire Ififo_element1_in_d_d11_d1 ;
wire Iin_d_d6_d0 ;
wire Ififo_element2_in_d_d16_d0 ;
wire Ififo_element1_in_d_d24_d1 ;
wire Ififo_element1_in_d_d22_d1 ;
output Iout_d_d26_d1 ;
wire Ififo_element1_in_d_d27_d1 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element2_in_d_d11_d1 ;
wire Ififo_element2_in_d_d12_d1 ;
output Iout_d_d11_d0 ;
output Iout_d_d21_d1 ;
wire Ififo_element2_in_d_d10_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element2_in_d_d22_d0 ;
wire Iin_d_d30_d1 ;
wire Ififo_element2_in_d_d9_d0 ;
output Iout_d_d14_d0 ;
wire Iin_d_d29_d0 ;
wire reset_B;
wire Ififo_element2_in_d_d14_d0 ;
wire Ififo_element2_in_d_d31_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d_d20_d0 ;
wire Ififo_element2_in_d_d23_d0 ;
wire Ififo_element2_in_a ;
wire Ififo_element1_in_d_d13_d1 ;
wire Ififo_element2_in_d_d21_d0 ;
wire Ififo_element2_in_d_d15_d0 ;
output Iout_d_d10_d0 ;
wire Ififo_element1_in_d_d8_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d16_d1 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Iin_d_d31_d1 ;
output Iin_a ;
wire Ififo_element2_in_d_d18_d1 ;
wire Ififo_element1_in_d_d29_d0 ;
wire Ififo_element2_in_d_d7_d1 ;
output Iout_d_d23_d0 ;
output Iout_d_d7_d1 ;
wire Ififo_element1_in_d_d18_d1 ;
wire _reset_BX ;
wire Iin_d_d2_d0 ;
output Iout_d_d14_d1 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d20_d0 ;
wire Ififo_element2_in_d_d19_d0 ;
output Iout_d_d8_d0 ;
wire Iin_d_d15_d0 ;
wire Ififo_element1_in_v ;
wire Iin_d_d7_d0 ;
wire Iin_d_d2_d1 ;
wire Ififo_element2_in_d_d17_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d4_d1 ;
wire Ififo_element1_in_a ;
wire Ififo_element2_in_d_d25_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d25_d0 ;
wire Ififo_element1_in_d_d17_d1 ;
wire Ififo_element2_in_v ;
output Iout_d_d15_d1 ;
wire Ififo_element1_in_d_d10_d1 ;
wire Ififo_element1_in_d_d9_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d10_d1 ;
wire Ififo_element2_in_d_d28_d1 ;
wire Ififo_element1_in_d_d14_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element2_in_d_d6_d0 ;
output Iout_d_d1_d0 ;
wire Iin_d_d18_d1 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element2_in_d_d29_d0 ;
output Iout_d_d7_d0 ;
wire Ififo_element1_in_d_d23_d0 ;
wire Ififo_element1_in_d_d9_d0 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_d_d16_d1 ;
wire Ififo_element2_in_d_d13_d1 ;
wire Ififo_element2_in_d_d30_d1 ;
output Iout_d_d28_d0 ;
wire Ififo_element2_in_d_d17_d1 ;
wire Ififo_element2_in_d_d27_d1 ;
wire Iin_d_d8_d0 ;
wire Ififo_element2_in_d_d21_d1 ;
output Iout_d_d6_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d12_d0 ;
wire Ififo_element2_in_d_d27_d0 ;
output Iout_d_d26_d0 ;
output Iout_d_d27_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element2_in_d_d20_d0 ;
output Iout_d_d1_d1 ;
output Iout_d_d4_d1 ;
wire Ififo_element2_in_d_d24_d0 ;
output Iout_d_d29_d1 ;
wire Ififo_element1_in_d_d19_d0 ;
wire Ififo_element1_in_d_d23_d1 ;
wire Iin_d_d1_d1 ;
wire Ififo_element2_in_d_d14_d1 ;
wire Ififo_element2_in_d_d29_d1 ;
output Iout_d_d15_d0 ;
wire Ififo_element1_in_d_d10_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d5_d0 ;
wire Ififo_element2_in_d_d31_d0 ;
wire Ififo_element2_in_d_d9_d1 ;
output Iout_d_d18_d1 ;
wire Ififo_element1_in_d_d12_d0 ;
wire Ififo_element2_in_d_d12_d0 ;
output Iout_d_d21_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Iin_d_d22_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
output Iout_d_d22_d1 ;
wire Ififo_element1_in_d_d25_d0 ;
wire Ififo_element1_in_d_d24_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Iin_d_d12_d1 ;
wire Ififo_element2_in_d_d18_d0 ;
wire Ififo_element2_in_d_d25_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d4_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d29_d0 ;
output Iout_d_d25_d1 ;
wire Ififo_element1_in_d_d20_d1 ;
output Iout_d_d8_d1 ;
output Iout_d_d30_d0 ;
wire Ififo_element1_in_d_d26_d0 ;
wire Ififo_element1_in_d_d15_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Ififo_element2_in_d_d10_d0 ;
wire Ififo_element2_in_d_d11_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d_d12_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d29_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Iout_a ;
wire Iin_d_d14_d0 ;
output Iout_d_d22_d0 ;
output Iout_d_d23_d1 ;
wire Ififo_element1_in_d_d21_d0 ;
wire Iin_d_d26_d1 ;
wire Ififo_element1_in_d_d11_d0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d27_d1 ;
wire I_reset_BXX2 ;
output Iout_d_d5_d1 ;
wire Iin_d_d30_d0 ;
wire Ififo_element1_in_d_d28_d0 ;
output Iout_d_d28_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d27_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d26_d0 ;
wire Iin_d_d0_d1 ;
wire Ififo_element2_in_d_d15_d1 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Iin_d_d7_d1 ;
wire Ififo_element2_in_d_d8_d0 ;
wire Iin_d_d6_d1 ;
wire Ififo_element2_in_d_d19_d1 ;
wire Ififo_element2_in_d_d20_d1 ;
output Iout_d_d11_d1 ;
wire Ififo_element2_in_d_d16_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element1_in_d_d22_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d17_d0 ;
output Iout_d_d19_d1 ;
wire Ififo_element1_in_d_d28_d1 ;
output Iout_d_d31_d0 ;
wire Ififo_element2_in_d_d8_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d20_d1 ;
output Iout_d_d6_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
output Iout_d_d12_d1 ;
wire Iin_d_d8_d1 ;
wire Ififo_element1_in_d_d31_d1 ;
wire Ififo_element1_in_d_d25_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element1_in_d_d27_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d10_d0 ;
output Iout_d_d24_d1 ;
output Iout_d_d31_d1 ;
wire Ififo_element1_in_d_d13_d0 ;
wire Ififo_element2_in_d_d22_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element2_in_d_d7_d0 ;
output Iout_d_d30_d1 ;
wire Ififo_element2_in_d_d23_d1 ;
output Iout_d_d24_d0 ;
wire Ififo_element1_in_d_d7_d1 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_d_d18_d0 ;
wire Ififo_element1_in_d_d7_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d13_d0 ;
wire Ififo_element1_in_d_d31_d0 ;
output Iout_d_d3_d1 ;
wire Ififo_element1_in_d_d15_d0 ;
wire Ififo_element1_in_d_d14_d1 ;
wire Ififo_element2_in_d_d24_d1 ;
output Iout_d_d9_d0 ;
wire Iout_v ;
wire Ififo_element1_in_d_d12_d1 ;
wire Ififo_element2_in_d_d26_d0 ;
output Iout_d_d9_d1 ;
wire Iin_d_d17_d1 ;
wire Ififo_element1_in_d_d30_d0 ;
output Iout_d_d0_d1 ;
output Iout_d_d13_d0 ;
output Iin_v ;
wire Iin_d_d23_d0 ;
wire Ififo_element2_in_d_d28_d0 ;
wire Iin_d_d9_d0 ;
wire Ififo_element2_in_d_d26_d1 ;
wire Ififo_element2_in_d_d30_d0 ;
wire Ififo_element1_in_d_d26_d1 ;
wire Ififo_element1_in_d_d19_d1 ;
wire Iin_d_d1_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_332_75_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

547
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_332_75_4/netlist/verilog.v

File diff suppressed because one or more lines are too long

112
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_37_73_4/netlist/verilog.v

@ -36,73 +36,73 @@ module tmpl_0_0dataflow__neuro_0_0fifo_37_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
input reset_B;
// -- signals ---
wire Ififo_element1_in_a ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
output Iout_d_d4_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d2_d1 ;
wire Iout_a ;
output Iout_d_d3_d0 ;
output Iout_d_d2_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
wire Ififo_element1_in_d_d5_d0 ;
output Iin_a ;
wire Iin_d_d0_d0 ;
wire reset_B;
output Iout_d_d4_d1 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Iin_d_d3_d1 ;
wire Ififo_element2_in_a ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d5_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d1_d0 ;
output Iout_d_d2_d0 ;
output Iout_d_d1_d1 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d3_d0 ;
wire Ififo_element1_in_v ;
output Iout_d_d6_d0 ;
output Iin_v ;
wire Iin_d_d1_d1 ;
output Iout_d_d3_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Iin_d_d4_d1 ;
output Iout_d_d1_d0 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
output Iout_d_d0_d1 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d6_d0 ;
wire I_reset_BXX2 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
output Iout_d_d5_d1 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
output Iout_d_d0_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element1_in_a ;
wire Ififo_element2_in_a ;
wire Ififo_element2_in_d_d1_d0 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d0_d1 ;
wire Iout_v ;
output Iout_d_d3_d0 ;
output Iin_a ;
output Iout_d_d6_d0 ;
output Iout_d_d2_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d1_d0 ;
wire I_reset_BXX2 ;
wire Iin_d_d4_d0 ;
wire Iout_a ;
wire Ififo_element2_in_d_d3_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
output Iin_v ;
wire _reset_BX ;
wire Ififo_element1_in_v ;
wire Ififo_element1_in_d_d4_d0 ;
wire Iin_d_d0_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d5_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Ififo_element1_in_d_d2_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d2_d1 ;
wire Iin_d_d3_d1 ;
wire Ififo_element2_in_d_d1_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d6_d1 ;
output Iout_d_d5_d1 ;
wire Iin_d_d1_d1 ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element1_in_d_d0_d0 ;
wire Iin_d_d6_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d4_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Iout_v ;
wire Ififo_element2_in_d_d5_d0 ;
wire Iin_d_d4_d1 ;
wire Ififo_element1_in_d_d3_d0 ;
wire reset_B;
wire Ififo_element1_in_d_d1_d0 ;
wire Iin_d_d5_d0 ;
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element1_in_d_d0_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_37_75_4/netlist/master.tag

@ -1,2 +0,0 @@
-- Master.tag File, Rev:1.0
verilog.v

147
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_37_75_4/netlist/verilog.v

@ -1,147 +0,0 @@
module tmpl_0_0dataflow__neuro_0_0fifo_37_75_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iout_a ;
input Iout_v ;
input reset_B;
// -- signals ---
output Iout_d_d1_d0 ;
wire Ififo_element2_in_d_d5_d1 ;
wire Ififo_element1_in_d_d3_d1 ;
wire Iin_d_d6_d1 ;
output Iout_d_d4_d0 ;
wire Ififo_element4_in_d_d1_d1 ;
wire Ififo_element3_in_d_d3_d1 ;
wire Ififo_element1_in_v ;
output Iout_d_d2_d1 ;
output Iout_d_d2_d0 ;
wire Iin_d_d5_d1 ;
wire _reset_BX ;
wire Iout_v ;
wire Ififo_element4_in_v ;
wire Ififo_element3_in_d_d2_d0 ;
wire Ififo_element2_in_d_d2_d1 ;
wire Ififo_element1_in_d_d6_d1 ;
wire Ififo_element1_in_d_d5_d0 ;
output Iout_d_d6_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d1_d1 ;
output Iout_d_d1_d1 ;
wire Iin_d_d2_d0 ;
wire Ififo_element4_in_d_d2_d1 ;
wire Ififo_element3_in_d_d4_d0 ;
wire Ififo_element2_in_d_d6_d1 ;
wire Ififo_element2_in_d_d2_d0 ;
wire Ififo_element1_in_d_d4_d1 ;
wire Iin_d_d5_d0 ;
wire Ififo_element4_in_d_d4_d1 ;
wire Ififo_element4_in_d_d3_d1 ;
wire Ififo_element3_in_d_d0_d0 ;
wire Ififo_element1_in_d_d1_d1 ;
wire Ififo_element1_in_d_d0_d0 ;
output Iout_d_d5_d1 ;
wire Ififo_element4_in_d_d2_d0 ;
wire Ififo_element3_in_d_d6_d1 ;
wire Ififo_element2_in_d_d3_d1 ;
wire Iout_a ;
output Iout_d_d3_d1 ;
wire Iin_d_d3_d1 ;
wire Ififo_element4_in_d_d3_d0 ;
wire Ififo_element2_in_d_d0_d1 ;
output Iin_a ;
wire Iin_d_d1_d0 ;
output Iout_d_d6_d1 ;
wire Ififo_element4_in_d_d4_d0 ;
wire Ififo_element1_in_d_d2_d1 ;
wire I_reset_BXX4 ;
output Iout_d_d3_d0 ;
wire Ififo_element2_in_v ;
wire Ififo_element2_in_d_d0_d0 ;
wire Ififo_element1_in_d_d4_d0 ;
wire Ififo_element3_in_d_d5_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d3_d0 ;
wire Ififo_element3_in_a ;
wire Ififo_element2_in_d_d4_d0 ;
wire Ififo_element3_in_d_d4_d1 ;
wire Ififo_element3_in_d_d1_d1 ;
wire Ififo_element1_in_d_d1_d0 ;
wire reset_B;
output Iout_d_d0_d0 ;
wire Ififo_element3_in_d_d3_d0 ;
wire Ififo_element2_in_d_d4_d1 ;
wire Ififo_element1_in_d_d0_d1 ;
wire Ififo_element3_in_d_d5_d0 ;
wire Ififo_element2_in_d_d6_d0 ;
wire Ififo_element2_in_d_d5_d0 ;
wire Ififo_element3_in_d_d2_d1 ;
wire Ififo_element1_in_a ;
wire Ififo_element1_in_d_d3_d0 ;
wire Iin_d_d4_d0 ;
wire Ififo_element4_in_d_d6_d1 ;
wire Ififo_element2_in_d_d3_d0 ;
wire Iin_d_d0_d1 ;
wire Ififo_element3_in_v ;
wire Ififo_element3_in_d_d0_d1 ;
wire Ififo_element2_in_a ;
wire Iin_d_d0_d0 ;
output Iout_d_d0_d1 ;
wire Ififo_element4_in_d_d5_d1 ;
wire Ififo_element3_in_d_d6_d0 ;
wire Ififo_element3_in_d_d1_d0 ;
wire Iin_d_d2_d1 ;
output Iout_d_d4_d1 ;
wire Ififo_element4_in_a ;
wire Ififo_element4_in_d_d0_d0 ;
wire Ififo_element1_in_d_d2_d0 ;
wire Ififo_element4_in_d_d6_d0 ;
wire Ififo_element4_in_d_d1_d0 ;
wire Ififo_element2_in_d_d1_d1 ;
wire Ififo_element1_in_d_d6_d0 ;
output Iin_v ;
output Iout_d_d5_d0 ;
wire Ififo_element4_in_d_d5_d0 ;
wire Ififo_element4_in_d_d0_d1 ;
wire Ififo_element2_in_d_d1_d0 ;
wire Ififo_element1_in_d_d5_d1 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX4 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element0 (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iout_a (Ififo_element1_in_a ), .Iout_v (Ififo_element1_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element1 (.Iin_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element1_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element1_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element1_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element1_in_d_d6_d1 ), .Iin_a (Ififo_element1_in_a ), .Iin_v (Ififo_element1_in_v ), .Iout_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iout_a (Ififo_element2_in_a ), .Iout_v (Ififo_element2_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element2 (.Iin_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element2_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element2_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element2_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element2_in_d_d6_d1 ), .Iin_a (Ififo_element2_in_a ), .Iin_v (Ififo_element2_in_v ), .Iout_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iout_a (Ififo_element3_in_a ), .Iout_v (Ififo_element3_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element3 (.Iin_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element3_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element3_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element3_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element3_in_d_d6_d1 ), .Iin_a (Ififo_element3_in_a ), .Iin_v (Ififo_element3_in_v ), .Iout_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iout_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iout_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iout_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iout_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iout_a (Ififo_element4_in_a ), .Iout_v (Ififo_element4_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ififo_element4 (.Iin_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iin_d_d5_d0 (Ififo_element4_in_d_d5_d0 ), .Iin_d_d5_d1 (Ififo_element4_in_d_d5_d1 ), .Iin_d_d6_d0 (Ififo_element4_in_d_d6_d0 ), .Iin_d_d6_d1 (Ififo_element4_in_d_d6_d1 ), .Iin_a (Ififo_element4_in_a ), .Iin_v (Ififo_element4_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
endmodule

414
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0fork_332_4/netlist/verilog.v

@ -202,215 +202,215 @@ module tmpl_0_0dataflow__neuro_0_0fork_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d
input reset_B;
// -- signals ---
output Iout2_d_d26_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d27_d0 ;
output Iout1_d_d13_d0 ;
output Iout1_d_d26_d0 ;
output Iout1_d_d16_d1 ;
output Iout2_d_d28_d0 ;
output Iout2_d_d22_d1 ;
output Iout2_d_d1_d1 ;
wire Iin_d_d2_d1 ;
output Iout2_d_d18_d1 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d28_d1 ;
output Iout2_d_d19_d0 ;
output Iout2_d_d19_d1 ;
output Iout2_d_d5_d1 ;
wire Iout1_a_B_buf_out0 ;
output Iout2_d_d21_d0 ;
output Iout2_d_d29_d1 ;
output Iout1_d_d27_d1 ;
output Iout2_d_d29_d0 ;
output Iout2_d_d21_d1 ;
output Iout2_d_d8_d1 ;
output Iout1_d_d28_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d19_d1 ;
output Iout1_d_d27_d0 ;
output Iout2_d_d0_d0 ;
output Iout1_d_d31_d1 ;
output Iout1_d_d24_d1 ;
wire Iout2_a_B_buf_out0 ;
wire Iin_d_d8_d1 ;
output Iout1_d_d2_d0 ;
output Iout1_d_d0_d1 ;
output Iout2_d_d31_d1 ;
wire Iin_d_d16_d0 ;
output Iout1_d_d6_d1 ;
output Iout1_d_d21_d1 ;
output Iout2_d_d13_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d14_d1 ;
output Iout2_d_d15_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d23_d1 ;
output Iout1_d_d25_d0 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d13_d0 ;
output Iout1_d_d11_d1 ;
output Iout2_d_d10_d0 ;
output Iout2_d_d28_d1 ;
output Iout1_d_d3_d0 ;
output Iout1_d_d5_d1 ;
wire reset_B;
output Iout2_d_d0_d1 ;
output Iin_a ;
wire Iin_d_d10_d0 ;
wire _reset_BX ;
output Iout1_d_d0_d0 ;
output Iout1_d_d12_d0 ;
output Iout2_d_d17_d1 ;
output Iout2_d_d7_d1 ;
wire _en ;
output Iout1_d_d12_d1 ;
wire Iin_d_d4_d0 ;
output Iout2_d_d23_d1 ;
wire Iin_d_d7_d0 ;
output Iout1_d_d5_d0 ;
output Iout1_d_d4_d1 ;
wire Iin_d_d26_d1 ;
output Iout1_d_d3_d1 ;
output Iout1_d_d14_d1 ;
output Iout2_d_d2_d0 ;
output Iout2_d_d2_d1 ;
wire Iin_d_d19_d0 ;
output Iout1_d_d7_d0 ;
output Iout2_d_d20_d0 ;
output Iout2_d_d8_d0 ;
output Iout2_d_d30_d1 ;
output Iout2_d_d20_d1 ;
output Iout2_d_d10_d1 ;
output Iout1_d_d11_d0 ;
output Iout2_d_d11_d1 ;
output Iout1_d_d10_d1 ;
output Iout1_d_d26_d1 ;
wire Iout2_v ;
output Iout1_d_d15_d0 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d9_d1 ;
output Iout1_d_d25_d1 ;
wire Iin_d_d12_d1 ;
wire Iout1_en_buf_out0 ;
output Iout2_d_d12_d1 ;
wire _out1_a_B ;
wire Iin_d_d28_d0 ;
output Iout2_d_d4_d1 ;
wire Iout2_a ;
output Iout2_d_d13_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d26_d0 ;
output Iout1_d_d6_d0 ;
output Iout1_d_d19_d0 ;
wire Iin_d_d18_d1 ;
output Iout1_d_d24_d0 ;
output Iout2_d_d23_d0 ;
output Iout1_d_d17_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d17_d1 ;
output Iout1_d_d20_d0 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d24_d1 ;
output Iout2_d_d14_d1 ;
wire Iin_d_d29_d1 ;
wire _out2_a_B ;
output Iout2_d_d4_d0 ;
wire Iin_d_d21_d0 ;
output Iout2_d_d27_d1 ;
wire Iin_d_d25_d1 ;
output Iout1_d_d23_d0 ;
output Iout1_d_d18_d1 ;
wire Iin_d_d9_d1 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d3_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d12_d0 ;
output Iout1_d_d1_d0 ;
output Iout2_d_d25_d1 ;
output Iout1_d_d22_d0 ;
output Iout2_d_d22_d0 ;
output Iin_v ;
wire Iin_d_d18_d0 ;
output Iout1_d_d28_d0 ;
output Iout2_d_d16_d0 ;
output Iout2_d_d9_d0 ;
output Iout1_d_d19_d1 ;
wire Iin_d_d8_d0 ;
output Iout2_d_d24_d0 ;
output Iout2_d_d6_d1 ;
output Iout1_d_d23_d1 ;
output Iout1_d_d22_d1 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d15_d0 ;
output Iout2_d_d15_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d29_d0 ;
output Iout2_d_d30_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d8_d1 ;
output Iout1_d_d9_d1 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d31_d0 ;
output Iout1_d_d17_d0 ;
output Iout1_d_d18_d0 ;
output Iout2_d_d27_d0 ;
output Iout2_d_d26_d0 ;
wire Iin_d_d30_d0 ;
output Iout1_d_d21_d0 ;
output Iout2_d_d6_d0 ;
output Iout2_d_d1_d0 ;
output Iout1_d_d30_d1 ;
output Iout1_d_d20_d1 ;
wire Iout1_a ;
wire Iin_d_d1_d1 ;
wire Iin_d_d15_d1 ;
output Iout2_d_d12_d0 ;
output Iout1_d_d29_d0 ;
output Iout2_d_d18_d0 ;
output Iout2_d_d11_d0 ;
wire Iin_d_d27_d1 ;
wire Iout2_en_buf_out0 ;
output Iout1_d_d2_d1 ;
output Iout1_d_d29_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d20_d0 ;
output Iout1_d_d30_d0 ;
output Iout1_d_d9_d0 ;
output Iout1_d_d10_d0 ;
output Iout2_d_d25_d0 ;
output Iout2_d_d17_d0 ;
output Iout2_d_d14_d0 ;
output Iout2_d_d24_d1 ;
wire _in_v ;
wire Iin_d_d10_d1 ;
output Iout2_d_d31_d0 ;
output Iout2_d_d7_d0 ;
wire Iin_d_d14_d0 ;
output Iout2_d_d16_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d25_d0 ;
wire Iin_d_d31_d1 ;
output Iout1_d_d8_d0 ;
output Iout1_d_d7_d1 ;
output Iout2_d_d5_d0 ;
wire Iin_d_d11_d1 ;
output Iout1_d_d16_d0 ;
wire Iout1_v ;
wire Iin_d_d22_d1 ;
output Iout1_d_d14_d0 ;
output Iout1_d_d13_d1 ;
output Iout1_d_d31_d0 ;
output Iout2_d_d5_d1 ;
output Iout2_d_d4_d1 ;
wire Iin_d_d5_d1 ;
output Iout2_d_d6_d0 ;
wire Iin_d_d14_d1 ;
output Iout1_d_d18_d0 ;
output Iout1_d_d15_d1 ;
output Iout1_d_d25_d1 ;
wire Iin_d_d30_d1 ;
output Iout1_d_d29_d0 ;
wire Iout2_a ;
output Iout1_d_d5_d1 ;
output Iout2_d_d24_d0 ;
output Iout2_d_d17_d0 ;
output Iout2_d_d9_d0 ;
output Iout2_d_d5_d0 ;
wire Iin_d_d28_d0 ;
wire Iin_d_d30_d0 ;
wire Iout1_a_B_buf_out0 ;
output Iout1_d_d17_d0 ;
output Iout2_d_d10_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d22_d1 ;
output Iout1_d_d6_d0 ;
output Iout1_d_d13_d0 ;
output Iout2_d_d11_d0 ;
wire Iin_d_d6_d1 ;
output Iout1_d_d10_d0 ;
output Iout1_d_d22_d0 ;
output Iout2_d_d13_d1 ;
output Iout2_d_d12_d1 ;
wire Iin_d_d26_d0 ;
output Iout1_d_d0_d0 ;
output Iout2_d_d8_d1 ;
wire Iin_d_d9_d0 ;
output Iout1_d_d16_d1 ;
output Iout2_d_d1_d0 ;
output Iout2_d_d15_d1 ;
output Iout1_d_d21_d1 ;
wire Iout1_en_buf_out0 ;
output Iout2_d_d31_d0 ;
wire Iin_d_d29_d1 ;
output Iout1_d_d12_d1 ;
output Iout2_d_d22_d0 ;
wire Iout2_v ;
wire Iin_d_d4_d0 ;
wire Iin_d_d19_d1 ;
output Iout1_d_d26_d1 ;
output Iout1_d_d12_d0 ;
output Iout1_d_d28_d0 ;
output Iout1_d_d0_d1 ;
output Iout1_d_d23_d1 ;
wire Iin_d_d2_d1 ;
output Iin_a ;
wire Iout1_v ;
wire Iin_d_d10_d1 ;
wire Iin_d_d11_d0 ;
output Iout1_d_d3_d1 ;
output Iout2_d_d20_d0 ;
wire Iin_d_d4_d1 ;
wire _out2_a_B ;
output Iout1_d_d2_d1 ;
output Iout2_d_d29_d0 ;
output Iout2_d_d30_d1 ;
output Iout2_d_d10_d1 ;
output Iout1_d_d10_d1 ;
wire Iin_d_d18_d0 ;
output Iout1_d_d14_d1 ;
output Iout2_d_d18_d0 ;
wire Iin_d_d3_d0 ;
output Iout1_d_d11_d0 ;
output Iout1_d_d19_d0 ;
wire Iin_d_d23_d0 ;
output Iout1_d_d24_d0 ;
output Iout1_d_d26_d0 ;
output Iout2_d_d23_d0 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d25_d0 ;
output Iout2_d_d25_d1 ;
wire Iin_d_d23_d1 ;
output Iout1_d_d6_d1 ;
output Iout1_d_d9_d1 ;
output Iout2_d_d9_d1 ;
output Iout2_d_d27_d0 ;
output Iout2_d_d23_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d21_d0 ;
output Iout2_d_d29_d1 ;
output Iout2_d_d20_d1 ;
wire Iin_d_d12_d1 ;
output Iout1_d_d9_d0 ;
output Iout2_d_d4_d0 ;
output Iout2_d_d3_d0 ;
output Iout1_d_d14_d0 ;
output Iout1_d_d31_d1 ;
output Iout2_d_d30_d0 ;
output Iout2_d_d13_d0 ;
wire Iin_d_d3_d1 ;
output Iout1_d_d4_d0 ;
output Iout2_d_d3_d1 ;
wire Iin_d_d7_d1 ;
output Iout1_d_d8_d1 ;
output Iout2_d_d22_d1 ;
output Iout1_d_d20_d1 ;
wire Iin_d_d26_d1 ;
output Iout1_d_d7_d1 ;
output Iout1_d_d24_d1 ;
output Iout1_d_d13_d1 ;
output Iout2_d_d1_d1 ;
wire Iout2_a_B_buf_out0 ;
output Iout1_d_d17_d1 ;
output Iout2_d_d19_d0 ;
output Iout1_d_d30_d1 ;
output Iout1_d_d31_d0 ;
output Iout2_d_d21_d1 ;
wire Iin_d_d17_d0 ;
output Iout2_d_d15_d0 ;
output Iout2_d_d8_d0 ;
output Iout2_d_d27_d1 ;
output Iout1_d_d16_d0 ;
output Iout1_d_d23_d0 ;
output Iout2_d_d12_d0 ;
wire _reset_BX ;
output Iout1_d_d5_d0 ;
output Iout1_d_d30_d0 ;
output Iout2_d_d7_d0 ;
output Iout1_d_d19_d1 ;
wire _out1_a_B ;
wire Iin_d_d24_d1 ;
wire Iin_d_d29_d0 ;
output Iout1_d_d2_d0 ;
output Iout1_d_d21_d0 ;
output Iout2_d_d31_d1 ;
output Iout2_d_d26_d1 ;
output Iout2_d_d11_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d13_d0 ;
output Iout1_d_d8_d0 ;
output Iout2_d_d26_d0 ;
output Iout2_d_d6_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d10_d0 ;
output Iout1_d_d27_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d31_d1 ;
wire Iout2_en_buf_out0 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d13_d1 ;
output Iout1_d_d27_d0 ;
wire reset_B;
output Iout2_d_d28_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d1_d0 ;
output Iout2_d_d0_d1 ;
output Iout1_d_d28_d1 ;
output Iin_v ;
wire Iin_d_d8_d1 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d27_d0 ;
output Iout2_d_d19_d1 ;
output Iout1_d_d20_d0 ;
output Iout2_d_d25_d0 ;
output Iout2_d_d21_d0 ;
output Iout2_d_d2_d0 ;
output Iout2_d_d24_d1 ;
output Iout1_d_d18_d1 ;
output Iout1_d_d25_d0 ;
output Iout1_d_d11_d1 ;
output Iout2_d_d28_d0 ;
wire Iin_d_d14_d0 ;
output Iout1_d_d7_d0 ;
output Iout1_d_d1_d0 ;
output Iout1_d_d3_d0 ;
output Iout2_d_d16_d1 ;
output Iout2_d_d2_d1 ;
wire Iin_d_d16_d0 ;
output Iout2_d_d17_d1 ;
wire Iout1_a ;
wire Iin_d_d19_d0 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d7_d0 ;
output Iout2_d_d7_d1 ;
wire _in_v ;
wire Iin_d_d11_d1 ;
wire _en ;
wire Iin_d_d16_d1 ;
output Iout2_d_d0_d0 ;
output Iout1_d_d22_d1 ;
output Iout1_d_d4_d1 ;
wire Iin_d_d15_d1 ;
output Iout1_d_d15_d0 ;
output Iout2_d_d18_d1 ;
wire I_reset_BXX0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d25_d1 ;
output Iout1_d_d1_d1 ;
output Iout2_d_d16_d0 ;
output Iout2_d_d14_d1 ;
output Iout1_d_d29_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d31_d0 ;
// --- instances
A_4C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout1_v ), .c4(Iout2_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));

394
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0merge_331_4/netlist/verilog.v

@ -196,214 +196,214 @@ module tmpl_0_0dataflow__neuro_0_0merge_331_4(Iin1_d_d0_d0 , Iin1_d_d0_d1 , Iin1
input reset_B;
// -- signals ---
wire Iin2_d_d13_d1 ;
output Iout_d_d11_d1 ;
output Iin2_v ;
output Iout_d_d14_d1 ;
wire Iin2_d_d10_d0 ;
wire Iin2_d_d14_d0 ;
output Iout_d_d21_d0 ;
wire Iin1_d_d27_d0 ;
output Iout_d_d9_d1 ;
wire Iin2_d_d5_d1 ;
wire Iin1_d_d20_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d25_d0 ;
output Iout_d_d29_d0 ;
wire Iin2_d_d30_d0 ;
wire Iin1_d_d30_d1 ;
wire Iin2_d_d7_d0 ;
wire Iin2_d_d28_d1 ;
wire Iin2_d_d18_d1 ;
output Iout_d_d12_d1 ;
wire Iin2_d_d10_d1 ;
output Iin1_v ;
wire Iin1_d_d10_d0 ;
wire Iin2_d_d11_d0 ;
wire Iin2_d_d20_d1 ;
output Iout_d_d16_d1 ;
wire Iin1_d_d23_d1 ;
output Iout_d_d9_d0 ;
wire Iin1_d_d9_d0 ;
wire Iin2_d_d28_d0 ;
wire Iin2_d_d19_d1 ;
wire Iin2_d_d12_d0 ;
wire Iin2_d_d18_d0 ;
wire I_out_a_BX0 ;
wire Iin1_d_d17_d0 ;
wire Iin1_d_d20_d0 ;
output Iout_d_d24_d1 ;
wire Iin2_d_d2_d0 ;
wire Iin2_d_d24_d0 ;
output Iout_d_d5_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d8_d0 ;
output Iin2_a ;
output Iout_d_d0_d1 ;
wire Iin1_d_d27_d1 ;
output Iout_d_d1_d0 ;
wire Iin2_d_d20_d0 ;
output Iout_d_d26_d0 ;
wire Iin1_d_d2_d1 ;
wire Iin2_d_d19_d0 ;
wire Iin1_d_d14_d1 ;
wire Iin2_d_d30_d1 ;
wire Iin2_d_d5_d0 ;
output Iout_d_d13_d0 ;
wire _in2_arb_temp ;
output Iout_d_d1_d1 ;
wire Iin1_d_d25_d1 ;
wire Iin2_d_d3_d0 ;
wire Iin1_d_d12_d0 ;
output Iout_d_d23_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin1_d_d3_d1 ;
wire I_out_temp_d_d0 ;
wire _out_a_B ;
wire Iin2_d_d8_d0 ;
output Iout_d_d10_d0 ;
wire Iin1_d_d14_d0 ;
wire Iin2_d_d21_d0 ;
wire Iin1_d_d18_d1 ;
wire Iin2_d_d9_d1 ;
wire I_in2_arb_X0 ;
wire _in1_arb_temp ;
wire Iin1_d_d12_d1 ;
output Iout_d_d6_d0 ;
wire Iin2_d_d25_d0 ;
wire Iin2_d_d3_d1 ;
output Iout_d_d3_d1 ;
wire Iin1_d_d29_d1 ;
output Iout_d_d12_d0 ;
wire Iin2_d_d29_d0 ;
wire Iin1_d_d30_d0 ;
wire Iin1_d_d10_d1 ;
wire Iin2_d_d24_d1 ;
output Iout_d_d20_d0 ;
wire Iin2_d_d22_d0 ;
wire Iout_a ;
wire Iin1_d_d3_d0 ;
output Iout_d_d22_d1 ;
output Iin1_a ;
wire Iin2_d_d16_d0 ;
wire Iin1_d_d1_d1 ;
wire Iin1_d_d8_d1 ;
output Iout_d_d13_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d3_d0 ;
wire Iin2_d_d6_d0 ;
wire Iin1_d_d22_d0 ;
wire Iin2_d_d27_d0 ;
output Iout_d_d29_d1 ;
wire Iin2_d_d17_d1 ;
output Iout_d_d15_d1 ;
wire I_in1_arb_X0 ;
wire Iin2_d_d29_d1 ;
wire Iin2_d_d12_d1 ;
wire Iin1_d_d26_d1 ;
wire Iin2_d_d17_d0 ;
wire Iin1_d_d22_d1 ;
wire _in1_arb ;
output Iout_d_d30_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d7_d0 ;
wire Iin1_d_d11_d0 ;
wire Iin1_d_d0_d1 ;
output Iout_d_d25_d1 ;
wire Iin2_d_d13_d0 ;
output Iout_d_d22_d0 ;
output Iout_d_d17_d1 ;
wire Iin2_d_d9_d1 ;
wire Iin1_d_d13_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d26_d1 ;
wire Iin1_d_d9_d1 ;
wire Iin2_d_d15_d1 ;
output Iout_d_d10_d1 ;
output Iout_d_d20_d1 ;
wire Iin2_d_d1_d1 ;
wire I_en_X0 ;
wire Iin1_d_d26_d1 ;
wire Iin2_d_d12_d0 ;
output Iout_d_d6_d1 ;
wire Iin1_d_d4_d0 ;
wire Iin1_d_d14_d0 ;
wire Iin2_d_d3_d0 ;
wire _in1_arb_temp ;
wire Iin1_d_d15_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d27_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d13_d1 ;
output Iout_d_d5_d1 ;
wire Iin2_d_d0_d0 ;
wire Iin2_d_d2_d0 ;
wire Iin2_d_d9_d0 ;
wire Iin2_d_d24_d0 ;
wire Iin1_d_d27_d0 ;
wire Iin1_d_d18_d1 ;
wire Iin1_d_d0_d0 ;
wire Iin1_d_d2_d0 ;
wire Iin2_d_d6_d0 ;
wire Iin1_d_d7_d0 ;
output Iout_d_d16_d0 ;
wire Iin2_d_d26_d1 ;
output Iout_d_d7_d1 ;
wire Iin1_d_d19_d0 ;
wire _in1_arb ;
wire Iin1_d_d19_d1 ;
output Iout_d_d30_d1 ;
output Iout_d_d0_d1 ;
wire Iin1_d_d20_d0 ;
wire Iin2_d_d20_d0 ;
wire Iin1_d_d25_d0 ;
wire _reset_BX ;
output Iout_d_d23_d1 ;
wire Iin2_d_d16_d1 ;
wire Iin2_d_d8_d1 ;
output Iout_d_d20_d1 ;
wire Iin2_d_d15_d1 ;
wire _out_a_B ;
wire Iin2_d_d20_d1 ;
output Iout_d_d19_d1 ;
wire Iin2_d_d3_d1 ;
wire Iin2_d_d23_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d15_d0 ;
wire Iin1_d_d17_d0 ;
wire Iin2_d_d10_d1 ;
output Iout_d_d2_d1 ;
wire Iin1_d_d11_d0 ;
wire Iin2_d_d11_d0 ;
output Iout_d_d25_d0 ;
wire Iin1_d_d3_d1 ;
output Iout_d_d8_d1 ;
wire Iin2_d_d4_d1 ;
wire Iin2_d_d8_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d23_d0 ;
wire Iin1_d_d11_d1 ;
wire Iin2_d_d19_d1 ;
wire Iin1_d_d3_d0 ;
wire Iin2_d_d16_d0 ;
output Iout_d_d14_d1 ;
wire Iin2_d_d5_d1 ;
wire Iin1_d_d13_d0 ;
wire Iin1_d_d23_d0 ;
wire Iin1_d_d25_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d18_d0 ;
wire Iin1_d_d17_d1 ;
wire Iin1_d_d27_d1 ;
wire Iin1_d_d22_d1 ;
wire Iin1_d_d15_d0 ;
wire Iin2_d_d24_d1 ;
output Iout_d_d22_d1 ;
wire Iin1_d_d8_d0 ;
output Iout_d_d10_d0 ;
wire Iin1_d_d9_d1 ;
wire Iin2_d_d14_d1 ;
wire I_reset_BXX0 ;
wire _in1_a_B ;
wire Iin2_d_d23_d1 ;
wire Iin2_d_d29_d0 ;
wire Iout_v ;
wire Iin1_d_d29_d1 ;
wire I_in1_arb_X0 ;
wire Iin2_d_d7_d0 ;
wire Iin2_d_d28_d0 ;
wire Iin1_d_d10_d1 ;
wire Iin2_d_d28_d1 ;
wire I_en_X0 ;
wire I_out_a_BX0 ;
wire I_in2_arb_X0 ;
output Iout_d_d3_d0 ;
output Iout_d_d27_d1 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d6_d0 ;
wire Iin2_d_d1_d1 ;
wire Iin1_d_d30_d1 ;
wire Iin1_d_d24_d1 ;
wire _in2_arb ;
wire Iin2_d_d23_d1 ;
output Iout_d_d23_d1 ;
wire Iin1_d_d0_d0 ;
wire Iin2_d_d9_d0 ;
wire Iin1_d_d19_d0 ;
wire Iin2_d_d6_d1 ;
wire Iin2_d_d26_d0 ;
wire Iin2_d_d25_d1 ;
wire I_reset_BXX0 ;
wire Iin1_d_d4_d0 ;
wire Iin1_d_d22_d0 ;
wire Iin1_d_d19_d1 ;
output Iout_d_d6_d1 ;
wire _reset_BX ;
wire Iin2_d_d16_d1 ;
wire Iin1_d_d11_d1 ;
wire Iin2_d_d22_d1 ;
wire Iin1_d_d6_d0 ;
output Iout_d_d18_d0 ;
wire _in1_a_B ;
wire Iin1_d_d15_d1 ;
wire Iin2_d_d27_d1 ;
output Iout_d_d28_d0 ;
wire Iin1_d_d5_d1 ;
wire Iout_v ;
wire Iin1_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire reset_B;
wire Iin2_d_d15_d0 ;
output Iout_d_d24_d0 ;
wire _en ;
wire Iin1_d_d13_d1 ;
wire Iin1_d_d17_d1 ;
output Iout_d_d21_d1 ;
wire Iin2_d_d8_d1 ;
wire Iin2_d_d2_d1 ;
wire Iin2_d_d23_d0 ;
output Iout_d_d27_d0 ;
wire Iin2_d_d11_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d5_d0 ;
wire Iin1_d_d5_d0 ;
output Iout_d_d14_d0 ;
wire Iin1_d_d21_d1 ;
output Iout_d_d19_d1 ;
wire Iin2_d_d7_d1 ;
wire Iin2_d_d1_d0 ;
wire Iin2_d_d4_d1 ;
wire Iin1_d_d8_d0 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d15_d0 ;
wire Iin1_d_d15_d0 ;
wire Iin1_d_d25_d0 ;
wire _in2_a_B ;
wire Iin1_d_d6_d1 ;
wire Iin2_d_d14_d1 ;
wire Iin1_d_d28_d1 ;
wire Iin1_d_d16_d0 ;
output Iout_d_d30_d0 ;
output Iout_d_d17_d1 ;
wire Iin2_d_d4_d0 ;
wire Iin1_d_d13_d0 ;
wire Iin1_d_d21_d0 ;
wire Iin1_d_d26_d0 ;
wire Iin1_d_d7_d1 ;
output Iout_d_d28_d1 ;
wire Iin1_d_d2_d0 ;
wire Iin1_d_d23_d0 ;
wire Iin1_d_d29_d0 ;
wire Iin1_d_d4_d1 ;
wire Iin2_d_d0_d1 ;
output Iout_d_d27_d1 ;
output Iout_d_d4_d1 ;
wire Iin1_d_d28_d0 ;
wire Iin2_d_d0_d0 ;
wire Iin2_d_d21_d1 ;
output Iout_d_d8_d1 ;
output Iin2_a ;
output Iout_d_d17_d0 ;
wire Iin2_d_d13_d1 ;
output Iout_d_d14_d0 ;
wire Iin1_d_d2_d1 ;
output Iin2_v ;
wire Iin1_d_d6_d0 ;
output Iout_d_d20_d0 ;
wire Iin1_d_d26_d0 ;
wire Iin2_d_d30_d0 ;
wire Iin2_d_d1_d0 ;
wire Iin1_d_d16_d0 ;
output Iin1_a ;
wire Iin1_d_d1_d1 ;
wire Iin1_d_d6_d1 ;
output Iout_d_d10_d1 ;
wire Iin2_d_d6_d1 ;
wire Iin1_d_d5_d0 ;
output Iout_d_d7_d0 ;
wire Iin2_d_d17_d0 ;
wire Iin1_d_d18_d0 ;
wire _en ;
wire Iin1_d_d12_d0 ;
output Iout_d_d22_d0 ;
output Iout_d_d18_d1 ;
output Iout_d_d13_d0 ;
wire Iin1_d_d21_d0 ;
wire Iin2_d_d30_d1 ;
wire Iin2_d_d27_d1 ;
wire Iin2_d_d18_d0 ;
wire Iin1_d_d29_d0 ;
wire Iin1_d_d7_d1 ;
output Iout_d_d4_d1 ;
wire Iin2_d_d4_d0 ;
output Iout_d_d21_d0 ;
wire Iin2_d_d25_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d26_d0 ;
output Iout_d_d1_d1 ;
wire Iin1_d_d9_d0 ;
output Iout_d_d28_d0 ;
wire Iin1_d_d4_d1 ;
wire Iin1_d_d5_d1 ;
output Iout_d_d29_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d5_d0 ;
wire Iin1_d_d12_d1 ;
wire Iin2_d_d5_d0 ;
wire Iin2_d_d14_d0 ;
wire Iin1_d_d21_d1 ;
wire Iin2_d_d21_d1 ;
wire Iin2_d_d11_d1 ;
wire Iin2_d_d19_d0 ;
wire reset_B;
wire Iin1_d_d20_d1 ;
output Iout_d_d19_d0 ;
wire I_out_temp_d_d0 ;
wire Iout_a ;
wire Iin2_d_d18_d1 ;
output Iout_d_d15_d1 ;
wire Iin1_d_d23_d1 ;
output Iout_d_d8_d0 ;
wire _in2_a_B ;
wire Iin1_d_d14_d1 ;
wire Iin2_d_d2_d1 ;
wire Iin2_d_d22_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin1_d_d16_d1 ;
wire Iin2_d_d22_d1 ;
output Iout_d_d11_d1 ;
wire Iin2_d_d10_d0 ;
wire Iin2_d_d21_d0 ;
wire Iin1_d_d28_d0 ;
output Iout_d_d21_d1 ;
output Iin1_v ;
wire Iin2_d_d26_d0 ;
output Iout_d_d9_d1 ;
wire Iin1_d_d28_d1 ;
wire Iin1_d_d0_d1 ;
output Iout_d_d7_d1 ;
wire Iin2_d_d26_d1 ;
output Iout_d_d12_d1 ;
wire Iin1_d_d10_d0 ;
output Iout_d_d16_d0 ;
wire Iin2_d_d13_d0 ;
wire Iin2_d_d25_d0 ;
wire Iin2_d_d29_d1 ;
wire Iin2_d_d15_d0 ;
wire Iin1_d_d8_d1 ;
output Iout_d_d24_d1 ;
wire Iin2_d_d7_d1 ;
wire Iin1_d_d30_d0 ;
wire Iin2_d_d0_d1 ;
output Iout_d_d4_d0 ;
wire Iin2_d_d12_d1 ;
wire _in2_arb_temp ;
// --- instances
A_2C2N2N_RB_X1 Imerge_func_f0 (.y(Iout_d_d0_d0 ), .c1(I_en_X0 ), .c2(I_out_a_BX0 ), .na1(I_in1_arb_X0 ), .na2(Iin1_d_d0_d0 ), .nb1(I_in2_arb_X0 ), .nb2(Iin2_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));

406
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0merge_332_4/netlist/verilog.v

@ -202,220 +202,220 @@ module tmpl_0_0dataflow__neuro_0_0merge_332_4(Iin1_d_d0_d0 , Iin1_d_d0_d1 , Iin1
input reset_B;
// -- signals ---
output Iout_d_d27_d1 ;
wire Iin1_d_d31_d0 ;
wire Iin1_d_d6_d1 ;
wire Iin1_d_d17_d1 ;
wire Iin1_d_d7_d0 ;
wire _in2_arb_temp ;
wire Iin2_d_d24_d0 ;
output Iout_d_d8_d1 ;
wire Iin1_d_d30_d1 ;
wire Iin1_d_d18_d0 ;
output Iout_d_d26_d1 ;
wire Iin1_d_d9_d0 ;
wire Iin2_d_d18_d0 ;
wire Iin1_d_d30_d0 ;
wire _in1_a_B ;
wire _in1_arb ;
wire Iin2_d_d26_d1 ;
output Iout_d_d21_d1 ;
wire Iin2_d_d4_d1 ;
output Iout_d_d0_d1 ;
wire _in2_a_B ;
output Iout_d_d9_d0 ;
output Iout_d_d4_d0 ;
wire Iin1_d_d16_d0 ;
wire Iin1_d_d20_d0 ;
wire Iin1_d_d0_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d22_d1 ;
wire Iin1_d_d17_d0 ;
output Iout_d_d15_d0 ;
wire Iin2_d_d16_d1 ;
wire Iin2_d_d2_d1 ;
wire Iin1_d_d25_d1 ;
wire Iin1_d_d6_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d13_d0 ;
wire Iin1_d_d25_d0 ;
wire Iin2_d_d5_d1 ;
wire Iin1_d_d7_d1 ;
output Iout_d_d12_d0 ;
wire Iin2_d_d12_d0 ;
wire Iin2_d_d17_d0 ;
wire _in1_arb_temp ;
wire Iin1_d_d8_d1 ;
wire Iin2_d_d25_d1 ;
wire Iin1_d_d29_d1 ;
wire Iin1_d_d3_d1 ;
output Iout_d_d14_d1 ;
wire Iin1_d_d18_d1 ;
output Iin1_v ;
wire I_en_X0 ;
wire Iin1_d_d2_d0 ;
wire Iin1_d_d2_d1 ;
output Iout_d_d10_d1 ;
wire Iin1_d_d31_d1 ;
wire Iin1_d_d27_d1 ;
wire Iin2_d_d2_d0 ;
wire Iin2_d_d4_d0 ;
wire Iin1_d_d5_d0 ;
output Iout_d_d11_d0 ;
wire Iin2_d_d20_d0 ;
output Iin2_v ;
wire Iin1_d_d19_d1 ;
output Iout_d_d5_d1 ;
output Iout_d_d17_d1 ;
wire Iin1_d_d23_d1 ;
wire Iin1_d_d21_d1 ;
wire Iin2_d_d31_d1 ;
wire Iin2_d_d15_d1 ;
wire Iin2_d_d16_d0 ;
wire Iin2_d_d9_d1 ;
wire Iin1_d_d28_d1 ;
wire I_in2_arb_X0 ;
wire Iin2_d_d14_d0 ;
output Iout_d_d19_d0 ;
output Iout_d_d24_d0 ;
wire Iin2_d_d28_d0 ;
wire Iin2_d_d31_d0 ;
wire Iin2_d_d17_d1 ;
wire Iin1_d_d15_d1 ;
wire Iout_a ;
wire Iin2_d_d24_d1 ;
output Iout_d_d21_d0 ;
wire Iin2_d_d22_d0 ;
wire Iin1_d_d13_d1 ;
wire Iin2_d_d21_d1 ;
wire Iin2_d_d13_d1 ;
output Iout_d_d9_d1 ;
wire Iin1_d_d3_d0 ;
wire Iin2_d_d11_d0 ;
wire Iin1_d_d24_d0 ;
wire Iin1_d_d4_d0 ;
wire Iin1_d_d21_d0 ;
wire Iout_v ;
wire Iin2_d_d29_d1 ;
wire Iin1_d_d29_d0 ;
wire Iin1_d_d11_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d24_d1 ;
wire Iin1_d_d26_d0 ;
wire _in2_arb ;
wire Iin1_d_d12_d1 ;
wire Iin2_d_d19_d1 ;
wire Iin2_d_d0_d0 ;
wire Iin1_d_d1_d0 ;
output Iout_d_d5_d0 ;
wire Iin1_d_d15_d0 ;
wire Iin1_d_d4_d1 ;
output Iout_d_d4_d1 ;
wire I_out_a_BX0 ;
wire _reset_BX ;
wire Iin1_d_d14_d1 ;
wire I_out_temp_d_d0 ;
output Iout_d_d20_d1 ;
wire Iin2_d_d1_d0 ;
wire Iin2_d_d7_d0 ;
wire Iin2_d_d20_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d25_d0 ;
wire Iin1_d_d28_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d7_d1 ;
output Iout_d_d2_d1 ;
output Iout_d_d31_d1 ;
output Iout_d_d19_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d29_d0 ;
wire Iin1_d_d9_d1 ;
output Iout_d_d23_d1 ;
wire Iin2_d_d14_d1 ;
wire Iin2_d_d9_d0 ;
wire Iin1_d_d14_d0 ;
wire reset_B;
wire Iin2_d_d12_d1 ;
wire I_in1_arb_X0 ;
output Iout_d_d28_d0 ;
wire Iin1_d_d5_d1 ;
output Iout_d_d15_d1 ;
wire Iin2_d_d3_d0 ;
output Iout_d_d31_d0 ;
wire _en ;
wire Iin1_d_d1_d1 ;
output Iout_d_d1_d1 ;
output Iout_d_d18_d1 ;
wire Iin1_d_d26_d1 ;
wire Iin2_d_d6_d0 ;
wire Iin1_d_d23_d0 ;
output Iout_d_d30_d1 ;
output Iout_d_d6_d1 ;
wire Iin2_d_d15_d0 ;
output Iout_d_d20_d0 ;
wire Iin2_d_d25_d0 ;
wire Iin2_d_d26_d0 ;
wire Iin2_d_d6_d1 ;
wire Iin1_d_d11_d0 ;
wire Iin2_d_d13_d0 ;
output Iout_d_d22_d0 ;
wire Iin2_d_d28_d1 ;
wire Iin2_d_d11_d1 ;
wire Iin2_d_d10_d1 ;
wire Iin2_d_d27_d1 ;
output Iout_d_d12_d1 ;
output Iout_d_d11_d1 ;
wire Iin2_d_d3_d1 ;
wire Iin2_d_d22_d0 ;
output Iout_d_d30_d0 ;
output Iin2_v ;
wire Iin2_d_d12_d1 ;
wire Iin1_d_d10_d1 ;
output Iout_d_d16_d1 ;
wire Iin2_d_d14_d1 ;
wire Iin2_d_d8_d1 ;
output Iout_d_d13_d0 ;
wire Iin1_d_d18_d1 ;
wire _reset_BX ;
wire _in1_arb_temp ;
output Iout_d_d24_d1 ;
wire Iin2_d_d15_d1 ;
output Iout_d_d9_d1 ;
wire Iin2_d_d29_d1 ;
wire Iin1_d_d4_d0 ;
wire Iin1_d_d5_d0 ;
wire Iin2_d_d9_d0 ;
output Iout_d_d28_d0 ;
wire Iin1_d_d17_d1 ;
wire Iin2_d_d13_d1 ;
output Iin1_v ;
wire Iin1_d_d26_d0 ;
wire Iin2_d_d30_d0 ;
wire _in1_a_B ;
wire Iin1_d_d18_d0 ;
wire Iin2_d_d2_d0 ;
output Iout_d_d14_d0 ;
output Iout_d_d14_d1 ;
wire Iin2_d_d24_d0 ;
output Iout_d_d4_d1 ;
output Iout_d_d12_d0 ;
wire Iin1_d_d15_d0 ;
wire Iin1_d_d2_d1 ;
output Iout_d_d20_d1 ;
output Iout_d_d8_d1 ;
output Iout_d_d9_d0 ;
wire Iin1_d_d13_d1 ;
wire Iin2_d_d5_d0 ;
output Iout_d_d6_d0 ;
wire Iin1_d_d8_d0 ;
wire Iin2_d_d31_d1 ;
wire Iin1_d_d21_d1 ;
wire _in1_arb ;
output Iout_d_d2_d1 ;
output Iout_d_d0_d1 ;
wire Iin1_d_d19_d1 ;
output Iout_d_d18_d0 ;
output Iout_d_d19_d0 ;
wire Iin1_d_d20_d0 ;
wire _in2_arb ;
wire Iin2_d_d23_d1 ;
wire Iin1_d_d24_d1 ;
wire Iin1_d_d20_d1 ;
wire Iin2_d_d3_d0 ;
wire Iin2_d_d7_d0 ;
wire Iin2_d_d17_d0 ;
wire Iin2_d_d18_d0 ;
wire Iin1_d_d8_d1 ;
wire Iin2_d_d1_d0 ;
wire Iin1_d_d11_d0 ;
output Iout_d_d15_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d10_d0 ;
output Iout_d_d16_d0 ;
wire Iin1_d_d24_d0 ;
output Iout_d_d18_d1 ;
wire Iin1_d_d31_d0 ;
wire Iin2_d_d20_d1 ;
wire Iin2_d_d3_d1 ;
wire Iin1_d_d29_d1 ;
wire I_in2_arb_X0 ;
wire Iin2_d_d6_d0 ;
wire Iin2_d_d27_d1 ;
wire Iin2_d_d26_d1 ;
output Iout_d_d26_d1 ;
wire Iin2_d_d2_d1 ;
wire Iin1_d_d22_d1 ;
output Iout_d_d5_d0 ;
wire Iin1_d_d27_d0 ;
output Iout_d_d25_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d30_d0 ;
wire _out_a_B ;
wire Iin2_d_d23_d1 ;
wire Iin2_d_d30_d1 ;
output Iout_d_d28_d1 ;
output Iout_d_d27_d1 ;
wire Iout_v ;
output Iout_d_d6_d1 ;
wire Iin1_d_d26_d1 ;
wire Iin1_d_d6_d1 ;
wire Iin2_d_d21_d1 ;
wire Iin1_d_d0_d0 ;
wire Iin2_d_d25_d0 ;
wire Iin2_d_d26_d0 ;
wire Iin2_d_d29_d0 ;
output Iout_d_d31_d1 ;
wire Iin2_d_d11_d1 ;
output Iout_d_d4_d0 ;
output Iout_d_d29_d0 ;
wire Iin1_d_d5_d1 ;
wire Iin2_d_d10_d0 ;
wire Iin1_d_d13_d0 ;
wire Iin1_d_d19_d0 ;
output Iout_d_d12_d1 ;
wire Iin1_d_d31_d1 ;
output Iout_d_d10_d1 ;
wire Iin1_d_d4_d1 ;
wire Iin2_d_d6_d1 ;
wire Iin1_d_d28_d1 ;
output Iout_d_d8_d0 ;
output Iout_d_d17_d0 ;
wire Iin2_d_d20_d0 ;
wire Iin1_d_d21_d0 ;
wire Iin2_d_d22_d1 ;
wire Iin1_d_d1_d0 ;
wire Iin1_d_d22_d0 ;
wire Iin1_d_d0_d1 ;
output Iin2_a ;
output Iout_d_d23_d0 ;
wire Iin2_d_d31_d0 ;
wire Iin2_d_d17_d1 ;
wire Iin1_d_d3_d0 ;
wire Iin1_d_d29_d0 ;
wire reset_B;
wire Iout_a ;
output Iout_d_d11_d1 ;
wire Iin2_d_d9_d1 ;
output Iin1_a ;
wire Iin2_d_d4_d0 ;
output Iout_d_d26_d0 ;
output Iout_d_d27_d0 ;
wire Iin2_d_d0_d1 ;
wire Iin2_d_d10_d0 ;
output Iout_d_d18_d0 ;
wire Iin1_d_d16_d1 ;
output Iin2_a ;
wire Iin2_d_d18_d1 ;
output Iout_d_d13_d1 ;
wire Iin2_d_d1_d1 ;
output Iin1_a ;
wire Iin1_d_d24_d1 ;
output Iout_d_d23_d0 ;
wire Iin1_d_d20_d1 ;
output Iout_d_d0_d0 ;
output Iout_d_d1_d0 ;
wire Iin1_d_d10_d1 ;
wire Iin1_d_d0_d0 ;
wire Iin1_d_d19_d0 ;
wire Iin2_d_d21_d0 ;
wire Iin2_d_d8_d1 ;
output Iout_d_d3_d0 ;
output Iout_d_d16_d0 ;
wire Iin2_d_d19_d0 ;
wire Iin2_d_d30_d0 ;
output Iout_d_d16_d1 ;
wire Iin1_d_d22_d1 ;
wire Iin1_d_d10_d0 ;
output Iout_d_d17_d0 ;
wire Iin2_d_d23_d0 ;
wire Iin2_d_d30_d1 ;
wire Iin2_d_d8_d0 ;
wire Iin1_d_d12_d0 ;
wire Iin1_d_d13_d0 ;
output Iout_d_d14_d0 ;
wire Iin2_d_d29_d0 ;
wire _in2_a_B ;
output Iout_d_d19_d1 ;
wire Iin1_d_d6_d0 ;
wire Iin1_d_d1_d1 ;
wire Iin2_d_d19_d1 ;
wire Iin2_d_d7_d1 ;
output Iout_d_d8_d0 ;
wire Iin2_d_d0_d0 ;
wire Iin1_d_d2_d0 ;
output Iout_d_d6_d0 ;
wire Iin2_d_d8_d0 ;
wire Iin1_d_d10_d0 ;
wire _en ;
output Iout_d_d22_d0 ;
output Iout_d_d29_d1 ;
output Iout_d_d22_d1 ;
wire Iin2_d_d16_d1 ;
wire Iin1_d_d11_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d21_d1 ;
output Iout_d_d3_d1 ;
output Iout_d_d1_d0 ;
wire Iin2_d_d15_d0 ;
wire Iin1_d_d14_d1 ;
wire I_out_temp_d_d0 ;
wire Iin2_d_d25_d1 ;
output Iout_d_d13_d1 ;
output Iout_d_d7_d1 ;
wire Iin1_d_d16_d1 ;
wire Iin2_d_d19_d0 ;
wire Iin1_d_d23_d0 ;
wire Iin1_d_d30_d0 ;
output Iout_d_d31_d0 ;
output Iout_d_d5_d1 ;
wire Iin2_d_d11_d0 ;
output Iout_d_d23_d1 ;
wire Iin1_d_d25_d1 ;
wire I_reset_BXX0 ;
output Iout_d_d25_d0 ;
wire Iin1_d_d9_d0 ;
wire Iin2_d_d27_d0 ;
wire Iin1_d_d22_d0 ;
wire Iin1_d_d9_d1 ;
wire Iin2_d_d14_d0 ;
wire Iin2_d_d16_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d24_d0 ;
wire Iin2_d_d28_d0 ;
wire Iin1_d_d12_d1 ;
output Iout_d_d30_d1 ;
wire Iin1_d_d27_d1 ;
output Iout_d_d3_d0 ;
wire Iin1_d_d16_d0 ;
wire Iin1_d_d17_d0 ;
output Iout_d_d20_d0 ;
wire Iin2_d_d23_d0 ;
wire Iin1_d_d15_d1 ;
wire Iin1_d_d12_d0 ;
wire Iin2_d_d12_d0 ;
wire Iin2_d_d13_d0 ;
wire Iin1_d_d7_d1 ;
wire _out_a_B ;
wire Iin2_d_d4_d1 ;
wire Iin1_d_d30_d1 ;
wire I_out_a_BX0 ;
wire Iin1_d_d8_d0 ;
output Iout_d_d15_d0 ;
wire Iin1_d_d3_d1 ;
wire Iin1_d_d7_d0 ;
wire Iin2_d_d21_d0 ;
wire Iin1_d_d25_d0 ;
wire I_in1_arb_X0 ;
output Iout_d_d11_d0 ;
output Iout_d_d21_d0 ;
wire Iin1_d_d28_d0 ;
wire Iin2_d_d28_d1 ;
wire Iin2_d_d18_d1 ;
wire _in2_arb_temp ;
wire Iin2_d_d1_d1 ;
output Iout_d_d1_d1 ;
wire I_en_X0 ;
wire Iin2_d_d5_d1 ;
wire Iin2_d_d0_d1 ;
wire Iin1_d_d23_d1 ;
// --- instances
A_2C2N2N_RB_X1 Imerge_func_f0 (.y(Iout_d_d0_d0 ), .c1(I_en_X0 ), .c2(I_out_a_BX0 ), .na1(I_in1_arb_X0 ), .na2(Iin1_d_d0_d0 ), .nb1(I_in2_arb_X0 ), .nb2(Iin2_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));

18
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__hs__2d/netlist/verilog.v

@ -10,28 +10,28 @@ module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(Iin_d_d0 , Iin_a , Ioutx_d_d0 , Io
input reset_B;
// -- signals ---
output Iin_a ;
wire reset_B;
wire _en ;
output Ioutx_d_d0 ;
wire _y_a_B ;
wire _x_a_B ;
output Iouty_d_d0 ;
wire Iin_d_d0 ;
wire _req ;
wire Iin_d_d0 ;
wire _reqB ;
wire Iouty_a ;
wire _reset_BX ;
wire _en ;
output Iin_a ;
output Iouty_d_d0 ;
wire Ioutx_a ;
wire reset_B;
wire _y_a_B ;
wire _reset_BX ;
// --- instances
INV_X1 Ireq_inv (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu_y (.p1(_reqB), .p2(Iouty_a ), .y(Iouty_d_d0 ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu_y (.p1(Iouty_a ), .p2(_reqB), .y(Iouty_d_d0 ), .vdd(vdd), .vss(vss));
INV_X2 Iinv_x (.y(_x_a_B), .a(Ioutx_a ), .vdd(vdd), .vss(vss));
INV_X2 Iinv_y (.y(_y_a_B), .a(Iouty_a ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X1 IA_ack (.y(Iin_a ), .c1(_en), .c2(Iin_d_d0 ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
BUF_X2 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_1C1P_X1 IA_en (.y(_en), .c1(Iin_a ), .p1(_req), .vdd(vdd), .vss(vss));
A_2C1P1N_RB_X1 IA_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(Iin_d_d0 ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
A_3P_U_X4 Ipu_x (.p1(Ioutx_a ), .p2(_reqB), .p3(_y_a_B), .y(Ioutx_d_d0 ), .vdd(vdd), .vss(vss));
A_3P_U_X4 Ipu_x (.p1(Ioutx_a ), .p2(_y_a_B), .p3(_reqB), .y(Ioutx_d_d0 ), .vdd(vdd), .vss(vss));
endmodule

522
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4/netlist/verilog.v

@ -268,278 +268,278 @@ module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4(Iin0_d_d0 , Iin0_a
input reset_B;
// -- signals ---
wire Iin79_d_d0 ;
wire Iin85_d_d0 ;
output Ito_pd_y1_a ;
wire Iin12_d_d0 ;
output Ito_pd_y0_a ;
output Ito_pd_x0_d_d0 ;
output Iin25_a ;
wire Iin19_d_d0 ;
wire Iouty4_a ;
output Iin79_a ;
wire Iin32_d_d0 ;
wire Ineurons29_reset_B ;
output Iin0_a ;
output Ito_pd_x11_d_d0 ;
output Ioutx6_d_d0 ;
output Iin78_a ;
wire Ineurons59_reset_B ;
output Iin22_a ;
wire Iin8_d_d0 ;
output Ito_pd_y3_a ;
output Iouty0_d_d0 ;
wire Iin24_d_d0 ;
output Ioutx13_d_d0 ;
wire reset_B;
output Ito_pd_y2_a ;
wire Iin23_d_d0 ;
output Iin6_a ;
wire Iin4_d_d0 ;
wire Iin45_d_d0 ;
wire Ioutx12_a ;
output Iin32_a ;
wire Iin75_d_d0 ;
wire Iin16_d_d0 ;
output Iin9_a ;
wire Iin78_d_d0 ;
wire Ioutx2_a ;
output Iin59_a ;
wire Iin72_d_d0 ;
wire Ioutx6_a ;
wire Iin17_d_d0 ;
output Iin38_a ;
wire Iin50_d_d0 ;
output Iin66_a ;
wire Iouty2_a ;
wire Ioutx7_a ;
output Ito_pd_y1_d_d0 ;
output Iin34_a ;
output Iin69_a ;
wire Iin87_d_d0 ;
output Iin4_a ;
wire Iin46_d_d0 ;
output Iin65_a ;
output Iin76_a ;
wire Iin33_d_d0 ;
wire Iin49_d_d0 ;
output Iin33_a ;
output Iin35_a ;
output Iin52_a ;
wire Iin69_d_d0 ;
wire Iin77_d_d0 ;
output Iin14_a ;
output Iin7_a ;
output Ito_pd_x0_a ;
output Ioutx5_d_d0 ;
wire Iin0_d_d0 ;
output Ito_pd_y4_a ;
wire Iin42_d_d0 ;
wire Iouty5_a ;
output Iin70_a ;
output Iin80_a ;
wire Iin44_d_d0 ;
output Iin48_a ;
wire Iin89_d_d0 ;
output Iin5_a ;
output Iin19_a ;
wire Ineurons29_reset_B ;
output Ito_pd_y4_a ;
output Ioutx8_d_d0 ;
wire Iin53_d_d0 ;
output Ito_pd_y1_d_d0 ;
wire Ioutx0_a ;
output Iin29_a ;
output Iin58_a ;
output Iin74_a ;
output Iin77_a ;
output Ito_pd_x13_a ;
wire Iin58_d_d0 ;
output Ito_pd_y3_a ;
output Ioutx12_d_d0 ;
wire Iin48_d_d0 ;
output Iin49_a ;
wire Iin57_d_d0 ;
output Ioutx6_d_d0 ;
wire Ineurons59_reset_B ;
wire Iin51_d_d0 ;
output Iin53_a ;
wire Iin8_d_d0 ;
output Ito_pd_x4_a ;
output Iin14_a ;
wire Iin43_d_d0 ;
output Iin17_a ;
output Iin15_a ;
output Ioutx5_d_d0 ;
wire Iin64_d_d0 ;
wire reset_B;
output Ito_pd_x6_a ;
wire Iin46_d_d0 ;
output Iin81_a ;
wire Ioutx13_a ;
wire Iin65_d_d0 ;
output Iin78_a ;
wire Iin85_d_d0 ;
output Iouty2_d_d0 ;
wire Iin2_d_d0 ;
wire Iouty2_a ;
output Iin33_a ;
wire Iin67_d_d0 ;
wire Iin83_d_d0 ;
wire Iin32_d_d0 ;
output Iin12_a ;
wire Iin52_d_d0 ;
output Ito_pd_x10_d_d0 ;
wire Iin38_d_d0 ;
wire Iin22_d_d0 ;
output Ito_pd_x5_a ;
output Iin51_a ;
output Iin7_a ;
wire Iin6_d_d0 ;
output Iin1_a ;
output Iin27_a ;
wire Iin39_d_d0 ;
wire Ineurons14_reset_B ;
output Ito_pd_x0_a ;
output Ito_pd_x7_a ;
output Iin75_a ;
output Iin2_a ;
output Iin66_a ;
wire Iin71_d_d0 ;
output Iin38_a ;
wire Ioutx14_a ;
wire Iin18_d_d0 ;
output Ito_pd_x2_d_d0 ;
output Iin82_a ;
output Iin0_a ;
output Ito_pd_x0_d_d0 ;
wire Iin81_d_d0 ;
wire Ioutx3_a ;
output Iin26_a ;
output Iin11_a ;
output Ito_pd_x3_a ;
output Iin45_a ;
output Iin63_a ;
output Ioutx10_d_d0 ;
wire Iin55_d_d0 ;
output Iin25_a ;
output Ito_pd_y5_a ;
output Iin50_a ;
wire Iin63_d_d0 ;
output Iin20_a ;
wire Iin12_d_d0 ;
output Iin10_a ;
output Ito_pd_x13_d_d0 ;
output Iin36_a ;
wire Iin41_d_d0 ;
wire Iin3_d_d0 ;
output Ioutx11_d_d0 ;
output Ito_pd_x5_d_d0 ;
output Ito_pd_x3_d_d0 ;
wire Iin62_d_d0 ;
wire Iin88_d_d0 ;
output Iin22_a ;
output Ito_pd_x11_a ;
wire Iin13_d_d0 ;
wire Iin74_d_d0 ;
output Iin47_a ;
wire Iin20_d_d0 ;
output Iin43_a ;
wire Irsb5_in ;
wire Iin31_d_d0 ;
output Ito_pd_y2_a ;
output Ito_pd_x12_d_d0 ;
output Iin24_a ;
output Iin37_a ;
wire Iin36_d_d0 ;
output Iouty4_d_d0 ;
wire Iin11_d_d0 ;
output Iin40_a ;
output Iin42_a ;
wire Iin1_d_d0 ;
output Ito_pd_x14_d_d0 ;
wire Iin28_d_d0 ;
output Iin84_a ;
wire Ioutx10_a ;
wire Iin34_d_d0 ;
output Iin83_a ;
wire Ioutx5_a ;
wire Ioutx1_a ;
output Iin21_a ;
wire Iin14_d_d0 ;
output Ioutx4_d_d0 ;
output Iin44_a ;
wire Iin49_d_d0 ;
output Ito_pd_y4_d_d0 ;
wire Iin84_d_d0 ;
output Ioutx14_d_d0 ;
output Iin54_a ;
wire Iin59_d_d0 ;
wire Ineurons44_reset_B ;
wire Iin33_d_d0 ;
output Iin67_a ;
output Ito_pd_x6_d_d0 ;
output Ito_pd_x7_d_d0 ;
wire Ioutx4_a ;
output Ioutx0_d_d0 ;
wire Iin45_d_d0 ;
output Ito_pd_y3_d_d0 ;
wire Iin27_d_d0 ;
output Iin34_a ;
output Iin64_a ;
output Ioutx2_d_d0 ;
output Iin35_a ;
wire Iin47_d_d0 ;
wire Iin86_d_d0 ;
output Iin30_a ;
wire Iin54_d_d0 ;
output Iin57_a ;
wire Iin79_d_d0 ;
output Ito_pd_x8_d_d0 ;
output Iin55_a ;
wire Iin30_d_d0 ;
wire Ineurons74_reset_B ;
wire Iin73_d_d0 ;
output Iin23_a ;
output Iin52_a ;
output Iin87_a ;
wire Iin0_d_d0 ;
output Ito_pd_x12_a ;
wire Iin4_d_d0 ;
wire Iin19_d_d0 ;
output Iin41_a ;
output Iin86_a ;
output Iin28_a ;
wire Iin77_d_d0 ;
output Iin8_a ;
output Iin61_a ;
wire Iin9_d_d0 ;
output Ito_pd_x2_a ;
output Ito_pd_y2_d_d0 ;
output Iin65_a ;
wire Iin50_d_d0 ;
wire Iin69_d_d0 ;
output Iin73_a ;
output Ito_pd_y5_d_d0 ;
wire Iin82_d_d0 ;
output Iin31_a ;
output Ioutx9_d_d0 ;
wire Iin60_d_d0 ;
output Iin76_a ;
output Ito_pd_x1_d_d0 ;
output Iin60_a ;
wire Iin61_d_d0 ;
output Iin88_a ;
output Iin89_a ;
wire Iin37_d_d0 ;
output Ito_pd_x1_a ;
output Ioutx3_d_d0 ;
output Iin46_a ;
wire Iin70_d_d0 ;
output Ito_pd_x14_a ;
wire Iin5_d_d0 ;
wire Ioutx8_a ;
output Iin13_a ;
output Iin71_a ;
output Ioutx7_d_d0 ;
wire Iin66_d_d0 ;
output Iin68_a ;
wire Ineurons89_reset_B ;
wire Iin15_d_d0 ;
output Ito_pd_x4_d_d0 ;
output Iin56_a ;
wire Iin76_d_d0 ;
output Iin18_a ;
output Iin6_a ;
output Ito_pd_y0_a ;
wire Iouty3_a ;
output Ito_pd_y1_a ;
wire Iouty0_a ;
wire Iin21_d_d0 ;
output Iin62_a ;
wire Ioutx7_a ;
wire Iin25_d_d0 ;
wire Ioutx9_a ;
output Iin3_a ;
output Ioutx1_d_d0 ;
output Iin39_a ;
wire Iin68_d_d0 ;
wire Iin80_d_d0 ;
wire Iin35_d_d0 ;
output Ioutx13_d_d0 ;
wire Iin56_d_d0 ;
wire Iin29_d_d0 ;
wire Iin26_d_d0 ;
output Ito_pd_x7_a ;
output Iin56_a ;
wire Iin65_d_d0 ;
wire Ioutx11_a ;
output Iin29_a ;
wire Iin11_d_d0 ;
wire Iin89_d_d0 ;
output Iin31_a ;
wire Iin1_d_d0 ;
output Ito_pd_x13_d_d0 ;
output Ioutx4_d_d0 ;
wire Ioutx6_a ;
output Ioutx11_d_d0 ;
wire Iin55_d_d0 ;
output Iin88_a ;
output Ito_pd_x11_a ;
wire Iin10_d_d0 ;
wire Ioutx4_a ;
output Ito_pd_x10_a ;
output Iin77_a ;
wire Iin88_d_d0 ;
output Ito_pd_x4_a ;
output Ito_pd_x1_a ;
wire Iin35_d_d0 ;
output Iin81_a ;
output Ito_pd_x12_d_d0 ;
output Iin13_a ;
wire Iin47_d_d0 ;
output Iin53_a ;
output Ito_pd_x6_a ;
wire Iin51_d_d0 ;
wire Iin34_d_d0 ;
output Iin70_a ;
output Iin71_a ;
wire Iin40_d_d0 ;
wire Iin74_d_d0 ;
output Iin40_a ;
wire Iin56_d_d0 ;
wire Iin14_d_d0 ;
output Ito_pd_x2_d_d0 ;
output Iin59_a ;
wire Ioutx5_a ;
wire Iin15_d_d0 ;
wire Iin57_d_d0 ;
output Iin17_a ;
wire Iin75_d_d0 ;
output Ioutx1_d_d0 ;
output Iin63_a ;
wire Ioutx8_a ;
output Iin39_a ;
output Iin73_a ;
wire Iin63_d_d0 ;
output Ito_pd_y5_a ;
output Ito_pd_x14_d_d0 ;
output Ioutx9_d_d0 ;
output Iin68_a ;
wire Iin20_d_d0 ;
output Iin69_a ;
output Ito_pd_x8_a ;
wire Iin76_d_d0 ;
output Iin16_a ;
wire Iin37_d_d0 ;
wire Iin39_d_d0 ;
output Iin48_a ;
wire Iin48_d_d0 ;
output Iin75_a ;
wire Iin78_d_d0 ;
wire Iin6_d_d0 ;
wire Ineurons14_reset_B ;
wire Iin53_d_d0 ;
output Ioutx0_d_d0 ;
wire Iin54_d_d0 ;
wire Iin28_d_d0 ;
output Ito_pd_x12_a ;
output Iin10_a ;
wire Iin43_d_d0 ;
output Iin43_a ;
output Iin80_a ;
output Iin89_a ;
output Iin9_a ;
wire Iin60_d_d0 ;
output Iin61_a ;
output Iin32_a ;
wire Ineurons74_reset_B ;
output Ioutx3_d_d0 ;
output Iin1_a ;
output Iin15_a ;
wire Ioutx14_a ;
output Iin5_a ;
wire Ineurons44_reset_B ;
wire Iin18_d_d0 ;
wire Iouty0_a ;
output Iin24_a ;
output Iin42_a ;
wire Iin52_d_d0 ;
output Iin23_a ;
output Iin37_a ;
wire Iin42_d_d0 ;
output Iin47_a ;
output Iin12_a ;
wire Iin25_d_d0 ;
output Ioutx12_d_d0 ;
output Ito_pd_x5_d_d0 ;
output Iin60_a ;
output Ito_pd_x3_a ;
wire Iin84_d_d0 ;
output Iin86_a ;
wire Iouty5_a ;
wire Irsb5_in ;
wire Ioutx0_a ;
wire Iin41_d_d0 ;
output Iin62_a ;
wire Iin13_d_d0 ;
wire Ioutx10_a ;
wire Iin27_d_d0 ;
output Iin74_a ;
output Iin11_a ;
output Ito_pd_x6_d_d0 ;
output Iin50_a ;
wire Ioutx2_a ;
wire Iin82_d_d0 ;
wire Iin86_d_d0 ;
output Iin19_a ;
output Iouty1_d_d0 ;
output Ito_pd_x14_a ;
wire Iin70_d_d0 ;
output Iin82_a ;
output Iin64_a ;
output Iin72_a ;
wire Iin30_d_d0 ;
output Iin26_a ;
output Iin85_a ;
wire Iin9_d_d0 ;
output Ito_pd_x9_d_d0 ;
output Ioutx8_d_d0 ;
output Ito_pd_x10_d_d0 ;
wire Iin72_d_d0 ;
wire Iin21_d_d0 ;
output Iin18_a ;
wire Iouty1_a ;
output Iin55_a ;
wire Iin68_d_d0 ;
output Ioutx2_d_d0 ;
output Iin67_a ;
output Iin83_a ;
wire Iin83_d_d0 ;
output Iin84_a ;
output Iin57_a ;
wire Iin61_d_d0 ;
output Ito_pd_x9_a ;
output Iin2_a ;
wire Ioutx1_a ;
wire Iin62_d_d0 ;
output Iouty3_d_d0 ;
output Ito_pd_x13_a ;
wire Iin81_d_d0 ;
wire Iin71_d_d0 ;
wire Ioutx3_a ;
wire Iin31_d_d0 ;
wire Iin16_d_d0 ;
output Ito_pd_x4_d_d0 ;
output Iouty5_d_d0 ;
output Iin44_a ;
wire Iin73_d_d0 ;
output Iin8_a ;
wire Iin64_d_d0 ;
output Iouty2_d_d0 ;
wire Ioutx9_a ;
wire Iin38_d_d0 ;
output Ioutx10_d_d0 ;
output Ito_pd_x7_d_d0 ;
output Iin45_a ;
output Iin58_a ;
wire Iin80_d_d0 ;
output Iouty4_d_d0 ;
output Iin27_a ;
wire Iin2_d_d0 ;
output Ioutx7_d_d0 ;
output Ito_pd_x5_a ;
wire Iin59_d_d0 ;
output Iin3_a ;
wire Iin66_d_d0 ;
output Iin30_a ;
output Iin21_a ;
output Ito_pd_y2_d_d0 ;
wire Iin58_d_d0 ;
output Ito_pd_x8_d_d0 ;
wire Iin36_d_d0 ;
output Iin51_a ;
output Iin20_a ;
output Ito_pd_y3_d_d0 ;
output Ito_pd_y5_d_d0 ;
output Iin28_a ;
wire Iin5_d_d0 ;
output Iin36_a ;
output Iin46_a ;
output Iin41_a ;
wire Ineurons89_reset_B ;
output Ioutx14_d_d0 ;
output Ito_pd_x3_d_d0 ;
wire Ioutx12_a ;
output Ito_pd_y0_d_d0 ;
output Ito_pd_x1_d_d0 ;
output Ito_pd_y4_d_d0 ;
wire Iin7_d_d0 ;
wire Iouty3_a ;
output Iin49_a ;
wire Ioutx13_a ;
output Ito_pd_x2_a ;
output Iouty0_d_d0 ;
output Iin85_a ;
wire Ioutx11_a ;
wire Iin24_d_d0 ;
output Ito_pd_y0_d_d0 ;
output Iouty1_d_d0 ;
wire Iouty1_a ;
output Ito_pd_x11_d_d0 ;
wire Iin23_d_d0 ;
output Iin16_a ;
output Ito_pd_x9_a ;
wire Iin87_d_d0 ;
wire Iouty4_a ;
output Ito_pd_x9_d_d0 ;
output Iin72_a ;
wire Iin40_d_d0 ;
output Iouty5_d_d0 ;
output Ito_pd_x10_a ;
output Iin4_a ;
output Iin79_a ;
output Iouty3_d_d0 ;
wire Iin10_d_d0 ;
// --- instances
BUF_X4 Iout_req_buf_x0 (.y(Ioutx0_d_d0 ), .a(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));

12
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down/netlist/verilog.v

@ -1,18 +1,20 @@
module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, out, vdd, vss);
module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, Isupply_vdd , out, vdd, vss);
input vdd;
input vss;
input in;
input reset_B;
input Isupply_vdd ;
output out;
// -- signals ---
wire reset_B;
wire in;
wire out ;
wire in;
wire Iinv_y ;
wire reset_B;
wire Isupply_vdd ;
// --- instances
A_1N_U_X4 Ipull_down (.n1(in), .y(out), .vdd(vdd), .vss(vss));
A_1N_U_X4 Ipull_downR (.n1(Iinv_y ), .y(out), .vdd(vdd), .vss(vss));
A_2N_U_X4 Ipull_down (.n1(in), .n2(Isupply_vdd ), .y(out), .vdd(vdd), .vss(vss));
A_2N_U_X4 Ipull_downR (.n1(Iinv_y ), .n2(Isupply_vdd ), .y(out), .vdd(vdd), .vss(vss));
INV_X1 Iinv (.y(Iinv_y ), .a(reset_B), .vdd(vdd), .vss(vss));
endmodule

40
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_315_4/netlist/verilog.v

@ -19,32 +19,32 @@ module tmpl_0_0dataflow__neuro_0_0ortree_315_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin11 ;
wire Itmp19 ;
wire Itmp24 ;
wire Iin4 ;
wire Iin8 ;
wire Iin6 ;
wire Itmp24 ;
wire Iin3 ;
wire Itmp23 ;
wire out ;
wire Iin9 ;
wire Iin0 ;
wire Itmp21 ;
wire Itmp22 ;
wire Iin12 ;
wire Iin1 ;
wire Iin13 ;
wire Iin4 ;
wire Itmp19 ;
wire Iin5 ;
wire Itmp17 ;
wire Iin3 ;
wire Iin6 ;
wire out ;
wire Itmp20 ;
wire Itmp18 ;
wire Iin11 ;
wire Itmp16 ;
wire Iin9 ;
wire Iin7 ;
wire Iin1 ;
wire Itmp15 ;
wire Itmp23 ;
wire Iin14 ;
wire Iin13 ;
wire Iin12 ;
wire Itmp21 ;
wire Iin10 ;
wire Iin2 ;
wire Iin0 ;
wire Itmp22 ;
wire Iin10 ;
wire Iin14 ;
wire Itmp18 ;
wire Itmp15 ;
wire Itmp20 ;
// --- instances
OR3_X1 Ior3s0 (.y(Itmp21 ), .a(Iin12 ), .b(Iin13 ), .c(Iin14 ), .vdd(vdd), .vss(vss));

10
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_34_4/netlist/verilog.v

@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0ortree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, v
output out;
// -- signals ---
wire Iin2 ;
wire Itmp4 ;
wire Iin1 ;
wire Itmp5 ;
wire out ;
wire Iin0 ;
wire Iin3 ;
wire Itmp5 ;
wire Iin1 ;
wire out ;
wire Itmp4 ;
wire Iin2 ;
// --- instances
OR2_X1 Ior2s0 (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

198
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_358_4/netlist/verilog.v

@ -62,118 +62,118 @@ module tmpl_0_0dataflow__neuro_0_0ortree_358_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Itmp98 ;
wire Iin4 ;
wire Iin57 ;
wire Iin51 ;
wire Iin40 ;
wire Itmp109 ;
wire Itmp106 ;
wire Itmp84 ;
wire Itmp76 ;
wire Itmp64 ;
wire Itmp81 ;
wire Iin42 ;
wire Itmp78 ;
wire Iin31 ;
wire Iin18 ;
wire Iin12 ;
wire Itmp86 ;
wire Itmp103 ;
wire Itmp93 ;
wire Iin11 ;
wire Itmp61 ;
wire Itmp94 ;
wire Itmp72 ;
wire Itmp62 ;
wire Iin3 ;
wire Iin36 ;
wire Itmp69 ;
wire Iin19 ;
wire Iin14 ;
wire Itmp87 ;
wire Itmp83 ;
wire out ;
wire Itmp94 ;
wire Itmp90 ;
wire Iin54 ;
wire Iin15 ;
wire Iin56 ;
wire Iin49 ;
wire Itmp80 ;
wire Iin41 ;
wire Itmp65 ;
wire Iin9 ;
wire Itmp63 ;
wire Itmp105 ;
wire Iin39 ;
wire Iin20 ;
wire Iin13 ;
wire Iin30 ;
wire Iin24 ;
wire Itmp58 ;
wire Itmp99 ;
wire Iin47 ;
wire Iin16 ;
wire Itmp96 ;
wire Itmp66 ;
wire Itmp79 ;
wire Itmp88 ;
wire Iin48 ;
wire Iin29 ;
wire Iin7 ;
wire Iin46 ;
wire Iin4 ;
wire Itmp91 ;
wire Iin33 ;
wire Iin27 ;
wire Iin22 ;
wire Itmp97 ;
wire Itmp74 ;
wire Iin5 ;
wire Itmp104 ;
wire Itmp101 ;
wire Itmp75 ;
wire Itmp71 ;
wire Iin17 ;
wire Itmp84 ;
wire Iin50 ;
wire Iin38 ;
wire Iin34 ;
wire Iin46 ;
wire Itmp71 ;
wire Iin2 ;
wire Itmp100 ;
wire Itmp102 ;
wire Iin29 ;
wire Itmp66 ;
wire Iin7 ;
wire Itmp61 ;
wire Itmp60 ;
wire Itmp80 ;
wire Iin31 ;
wire out ;
wire Itmp89 ;
wire Itmp83 ;
wire Iin16 ;
wire Iin12 ;
wire Iin1 ;
wire Iin23 ;
wire Itmp79 ;
wire Itmp68 ;
wire Iin53 ;
wire Iin28 ;
wire Iin21 ;
wire Itmp81 ;
wire Iin18 ;
wire Itmp107 ;
wire Itmp82 ;
wire Iin43 ;
wire Itmp73 ;
wire Itmp63 ;
wire Iin32 ;
wire Itmp70 ;
wire Itmp110 ;
wire Itmp95 ;
wire Iin52 ;
wire Iin45 ;
wire Itmp67 ;
wire Iin2 ;
wire Itmp107 ;
wire Itmp100 ;
wire Iin37 ;
wire Itmp60 ;
wire Itmp59 ;
wire Iin10 ;
wire Iin8 ;
wire Itmp91 ;
wire Iin44 ;
wire Iin35 ;
wire Iin23 ;
wire Itmp68 ;
wire Itmp77 ;
wire Iin0 ;
wire Itmp85 ;
wire Itmp102 ;
wire Itmp92 ;
wire Itmp89 ;
wire Iin55 ;
wire Iin40 ;
wire Iin34 ;
wire Iin26 ;
wire Iin25 ;
wire Itmp67 ;
wire Iin48 ;
wire Itmp77 ;
wire Iin30 ;
wire Iin11 ;
wire Itmp87 ;
wire Itmp70 ;
wire Itmp104 ;
wire Itmp93 ;
wire Itmp90 ;
wire Iin57 ;
wire Itmp76 ;
wire Iin6 ;
wire Iin41 ;
wire Itmp59 ;
wire Iin55 ;
wire Iin47 ;
wire Itmp78 ;
wire Iin19 ;
wire Itmp101 ;
wire Itmp97 ;
wire Itmp62 ;
wire Itmp109 ;
wire Itmp98 ;
wire Itmp69 ;
wire Iin15 ;
wire Iin0 ;
wire Itmp108 ;
wire Itmp103 ;
wire Iin25 ;
wire Iin24 ;
wire Itmp65 ;
wire Iin32 ;
wire Iin17 ;
wire Iin9 ;
wire Itmp85 ;
wire Itmp92 ;
wire Itmp99 ;
wire Iin51 ;
wire Iin38 ;
wire Itmp64 ;
wire Itmp110 ;
wire Iin45 ;
wire Iin37 ;
wire Itmp74 ;
wire Iin27 ;
wire Iin22 ;
wire Iin20 ;
wire Iin14 ;
wire Iin5 ;
wire Itmp58 ;
wire Itmp106 ;
wire Iin35 ;
wire Iin28 ;
wire Iin21 ;
wire Itmp95 ;
wire Itmp88 ;
wire Iin52 ;
wire Iin42 ;
wire Iin39 ;
wire Iin10 ;
wire Iin54 ;
wire Iin49 ;
wire Itmp75 ;
wire Itmp73 ;
wire Iin8 ;
wire Itmp96 ;
wire Iin56 ;
wire Iin13 ;
wire Iin44 ;
wire Itmp86 ;
// --- instances
OR3_X1 Ior3s0 (.y(Itmp100 ), .a(Itmp84 ), .b(Itmp85 ), .c(Itmp86 ), .vdd(vdd), .vss(vss));

226
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_364_4/netlist/verilog.v

@ -68,133 +68,133 @@ module tmpl_0_0dataflow__neuro_0_0ortree_364_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
output out;
// -- signals ---
wire Iin51 ;
wire Itmp116 ;
wire Itmp102 ;
wire Iin15 ;
wire Itmp79 ;
wire Itmp87 ;
wire Iin33 ;
wire Itmp76 ;
wire Itmp73 ;
wire Iin14 ;
wire Iin39 ;
wire Iin28 ;
wire Iin17 ;
wire Itmp114 ;
wire Itmp111 ;
wire Itmp84 ;
wire out ;
wire Itmp122 ;
wire Itmp92 ;
wire Iin5 ;
wire Itmp108 ;
wire Itmp99 ;
wire Iin53 ;
wire Itmp70 ;
wire Iin10 ;
wire Itmp115 ;
wire Itmp104 ;
wire Iin54 ;
wire Itmp85 ;
wire Itmp113 ;
wire Itmp119 ;
wire Iin57 ;
wire Itmp91 ;
wire Iin37 ;
wire Itmp74 ;
wire Iin17 ;
wire Itmp72 ;
wire Iin12 ;
wire Iin0 ;
wire Itmp101 ;
wire Iin61 ;
wire Iin40 ;
wire Iin13 ;
wire Iin9 ;
wire Iin34 ;
wire Iin23 ;
wire Iin50 ;
wire Itmp88 ;
wire Itmp82 ;
wire Iin63 ;
wire Itmp93 ;
wire Itmp88 ;
wire Itmp78 ;
wire Iin24 ;
wire Iin13 ;
wire Itmp118 ;
wire Iin7 ;
wire Iin4 ;
wire Itmp97 ;
wire Iin43 ;
wire Iin38 ;
wire Iin18 ;
wire Iin1 ;
wire Iin47 ;
wire Iin6 ;
wire Itmp107 ;
wire Iin56 ;
wire Iin31 ;
wire Itmp76 ;
wire Iin16 ;
wire Itmp115 ;
wire Itmp84 ;
wire Itmp112 ;
wire Iin45 ;
wire Itmp80 ;
wire Iin10 ;
wire Iin0 ;
wire Itmp109 ;
wire Itmp102 ;
wire Itmp96 ;
wire Iin40 ;
wire Iin33 ;
wire Itmp114 ;
wire Iin59 ;
wire Iin43 ;
wire Iin42 ;
wire Itmp81 ;
wire Iin2 ;
wire Itmp119 ;
wire Iin59 ;
wire Iin44 ;
wire Iin32 ;
wire Iin25 ;
wire Itmp106 ;
wire Iin58 ;
wire Itmp75 ;
wire Iin48 ;
wire Iin30 ;
wire Iin62 ;
wire Iin60 ;
wire Itmp80 ;
wire Itmp74 ;
wire Iin19 ;
wire Itmp125 ;
wire Itmp108 ;
wire Iin27 ;
wire Iin21 ;
wire Iin14 ;
wire Itmp64 ;
wire Itmp124 ;
wire Itmp99 ;
wire Itmp73 ;
wire Itmp68 ;
wire out ;
wire Itmp111 ;
wire Iin53 ;
wire Iin46 ;
wire Iin36 ;
wire Iin45 ;
wire Itmp110 ;
wire Itmp105 ;
wire Itmp104 ;
wire Iin25 ;
wire Itmp69 ;
wire Iin41 ;
wire Itmp89 ;
wire Iin34 ;
wire Iin2 ;
wire Itmp121 ;
wire Itmp120 ;
wire Itmp85 ;
wire Iin11 ;
wire Iin9 ;
wire Itmp100 ;
wire Iin51 ;
wire Iin29 ;
wire Iin22 ;
wire Iin15 ;
wire Itmp70 ;
wire Itmp123 ;
wire Itmp93 ;
wire Itmp86 ;
wire Itmp77 ;
wire Iin5 ;
wire Iin1 ;
wire Itmp117 ;
wire Itmp103 ;
wire Iin58 ;
wire Iin35 ;
wire Iin8 ;
wire Iin6 ;
wire Itmp98 ;
wire Iin47 ;
wire Itmp87 ;
wire Iin19 ;
wire Itmp94 ;
wire Iin30 ;
wire Itmp79 ;
wire Iin23 ;
wire Iin60 ;
wire Itmp122 ;
wire Iin52 ;
wire Itmp90 ;
wire Itmp89 ;
wire Iin20 ;
wire Iin11 ;
wire Itmp78 ;
wire Itmp75 ;
wire Itmp71 ;
wire Iin49 ;
wire Iin21 ;
wire Itmp72 ;
wire Itmp66 ;
wire Iin55 ;
wire Itmp83 ;
wire Iin36 ;
wire Iin31 ;
wire Iin16 ;
wire Itmp103 ;
wire Itmp96 ;
wire Iin56 ;
wire Iin29 ;
wire Itmp98 ;
wire Itmp113 ;
wire Itmp95 ;
wire Iin41 ;
wire Iin39 ;
wire Itmp82 ;
wire Iin28 ;
wire Iin18 ;
wire Iin4 ;
wire Itmp97 ;
wire Itmp67 ;
wire Itmp100 ;
wire Itmp69 ;
wire Iin8 ;
wire Itmp109 ;
wire Itmp105 ;
wire Iin37 ;
wire Itmp77 ;
wire Iin24 ;
wire Itmp123 ;
wire Itmp118 ;
wire Itmp117 ;
wire Itmp91 ;
wire Itmp86 ;
wire Iin3 ;
wire Iin46 ;
wire Iin22 ;
wire Itmp68 ;
wire Itmp94 ;
wire Iin26 ;
wire Itmp124 ;
wire Itmp121 ;
wire Itmp110 ;
wire Itmp107 ;
wire Iin35 ;
wire Iin27 ;
wire Itmp65 ;
wire Itmp64 ;
wire Itmp116 ;
wire Iin62 ;
wire Iin55 ;
wire Iin50 ;
wire Iin32 ;
wire Itmp106 ;
wire Iin49 ;
wire Iin44 ;
wire Iin38 ;
wire Itmp71 ;
wire Iin3 ;
wire Itmp125 ;
wire Itmp101 ;
wire Iin61 ;
wire Iin54 ;
wire Iin26 ;
wire Iin20 ;
wire Itmp92 ;
wire Itmp83 ;
wire Itmp66 ;
// --- instances
OR2_X1 Ior2s0 (.y(Itmp64 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

20
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_38_4/netlist/verilog.v

@ -12,21 +12,21 @@ module tmpl_0_0dataflow__neuro_0_0ortree_38_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
output out;
// -- signals ---
wire Iin4 ;
wire Itmp12 ;
wire Itmp13 ;
wire Itmp9 ;
wire Iin3 ;
wire out ;
wire Iin7 ;
wire Itmp10 ;
wire Iin6 ;
wire Itmp11 ;
wire out ;
wire Iin5 ;
wire Iin6 ;
wire Itmp8 ;
wire Iin4 ;
wire Itmp9 ;
wire Itmp11 ;
wire Itmp12 ;
wire Iin3 ;
wire Itmp13 ;
wire Itmp10 ;
wire Iin1 ;
wire Iin2 ;
wire Iin0 ;
wire Iin2 ;
// --- instances
OR2_X1 Ior2s0 (.y(Itmp8 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

264
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4/netlist/verilog.v

@ -108,144 +108,144 @@ module tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Ii
input reset_B;
// -- signals ---
wire Iin_d_d0_d1 ;
output Iout_d5 ;
wire Iout_vtree_in_d18_d0 ;
wire Iin_d_d18_d0 ;
output Iout_d4 ;
wire Iout_vtree_in_d31_d0 ;
wire Iout_vtree_in_d30_d0 ;
output Iout_d28 ;
wire Iin_d_d0_d0 ;
output Iout_d14 ;
wire Iin_d_d1_d0 ;
output Iout_d9 ;
output Iout_d21 ;
wire Idly_in ;
output Iout_d19 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d11_d0 ;
output Iout_d18 ;
wire reset_B;
wire Idly_cfg1 ;
wire Iout_vtree_in_d15_d0 ;
wire Iout_vtree_in_d26_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d28_d0 ;
wire Iout_vtree_in_d8_d0 ;
output Iout_d22 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d23_d0 ;
output Iout_d2 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d25_d0 ;
wire Iout_vtree_in_d11_d0 ;
wire Iin_d_d24_d1 ;
wire Iin_d_d18_d1 ;
wire Iout_vtree_in_d10_d0 ;
wire Iin_d_d12_d1 ;
output Iout_d17 ;
wire Iout_vtree_in_d9_d0 ;
wire Iin_d_d31_d1 ;
wire Idly_cfg3 ;
wire Iin_d_d17_d1 ;
wire Iout_vtree_in_d25_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d17_d0 ;
output Iout_d7 ;
output Iout_d23 ;
wire Idly_cfg2 ;
wire Iin_d_d10_d0 ;
wire Iout_vtree_in_d2_d0 ;
wire Iout_vtree_in_d7_d0 ;
wire Iout_vtree_in_d20_d0 ;
wire Iout_vtree_in_d28_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d15_d1 ;
wire Iout_vtree_in_d13_d0 ;
wire Iin_d_d12_d0 ;
output Iout_d12 ;
wire Iin_d_d22_d1 ;
output Iout_d20 ;
output Iout_d15 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d21_d0 ;
output Iout_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d19_d0 ;
wire Iout_vtree_in_d17_d0 ;
wire Idly_cfg0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d27_d1 ;
output Iout_d11 ;
wire Iin_d_d21_d1 ;
wire Iout_vtree_in_d0_d0 ;
output Iout_d24 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d29_d1 ;
wire Iout_vtree_in_d16_d0 ;
wire Iin_d_d14_d1 ;
output Iin_v ;
wire Iout_vtree_in_d21_d0 ;
wire Iout_vtree_in_d27_d0 ;
wire Iout_vtree_in_d23_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d30_d0 ;
wire Iout_vtree_in_d3_d0 ;
output Iout_d8 ;
output Iout_d10 ;
output Iout_d25 ;
wire Iin_d_d9_d1 ;
wire Iin_d_d13_d1 ;
wire Iin_d_d23_d1 ;
wire Iout_vtree_in_d19_d0 ;
output Iout_r ;
wire Iin_d_d22_d0 ;
output Iout_d3 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d11_d1 ;
output Iout_d1 ;
wire Iout_vtree_in_d24_d0 ;
wire Iout_vtree_in_d12_d0 ;
wire Iin_d_d29_d0 ;
output Iin_a ;
wire Iout_vtree_in_d22_d0 ;
wire Iin_d_d26_d0 ;
output Iout_d30 ;
wire Iout_vtree_in_d5_d0 ;
wire Iout_vtree_in_d6_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d19_d1 ;
wire Iout_a ;
output Iout_d26 ;
output Iout_d31 ;
output Iout_d18 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d28_d1 ;
wire Iin_d_d31_d0 ;
wire Iout_vtree_in_d29_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d25_d1 ;
output Iout_d6 ;
output Iout_d29 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d8_d0 ;
wire Iout_vtree_in_d1_d0 ;
wire Iout_vtree_in_d4_d0 ;
wire Iout_vtree_in_d14_d0 ;
output Iout_d16 ;
output Iout_d13 ;
wire Iin_d_d28_d0 ;
output Iout_d27 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d24_d0 ;
wire Iin_d_d16_d1 ;
wire Iin_d_d17_d0 ;
wire Idly_cfg3 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d15_d0 ;
output Iout_d21 ;
wire Iout_vtree_in_d10_d0 ;
wire Iin_d_d3_d0 ;
output Iout_d30 ;
wire Iin_d_d27_d0 ;
output Iin_v ;
output Iout_d4 ;
output Iout_d13 ;
wire Iout_a ;
wire Iout_vtree_in_d31_d0 ;
wire Iin_d_d9_d1 ;
wire Iout_vtree_in_d20_d0 ;
wire Iout_vtree_in_d30_d0 ;
wire Iout_vtree_in_d7_d0 ;
output Iout_d25 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d25_d1 ;
wire Iout_vtree_in_d16_d0 ;
wire Iin_d_d21_d0 ;
wire Iout_vtree_in_d18_d0 ;
output Iout_r ;
wire Iout_vtree_in_d13_d0 ;
output Iout_d7 ;
output Iout_d28 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d7_d1 ;
wire Idly_in ;
wire Iin_d_d1_d0 ;
wire Iin_d_d19_d1 ;
wire Iin_d_d30_d0 ;
output Iout_d3 ;
wire Iout_vtree_in_d14_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d0 ;
wire Iout_vtree_in_d21_d0 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d29_d0 ;
output Iout_d26 ;
output Iout_d16 ;
output Iout_d22 ;
wire Iin_d_d5_d1 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d13_d0 ;
wire Iout_vtree_in_d27_d0 ;
output Iout_d24 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d23_d1 ;
wire Iout_vtree_in_d15_d0 ;
wire Iin_d_d24_d1 ;
wire Iout_vtree_in_d12_d0 ;
output Iout_d23 ;
wire Iin_d_d26_d0 ;
wire Iout_vtree_in_d11_d0 ;
output Iout_d15 ;
wire Iin_d_d27_d1 ;
wire Iout_vtree_in_d0_d0 ;
wire Iout_vtree_in_d25_d0 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d29 ;
wire Iin_d_d12_d1 ;
output Iout_d14 ;
wire Iout_vtree_in_d23_d0 ;
wire Iout_vtree_in_d22_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d22_d0 ;
output Iout_d9 ;
wire Iin_d_d17_d1 ;
output Iout_d20 ;
output Iout_d31 ;
wire Iin_d_d31_d0 ;
wire Iin_d_d7_d0 ;
wire Iout_vtree_in_d6_d0 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d6_d0 ;
wire Iout_vtree_in_d17_d0 ;
output Iout_d2 ;
wire Iin_d_d6_d1 ;
wire Iout_vtree_in_d4_d0 ;
wire Iin_d_d10_d1 ;
wire Iout_vtree_in_d24_d0 ;
wire Iin_d_d31_d1 ;
output Iin_a ;
wire Iin_d_d28_d1 ;
wire Iout_vtree_in_d5_d0 ;
wire Idly_cfg1 ;
wire Idly_cfg2 ;
output Iout_d6 ;
wire Iout_vtree_in_d8_d0 ;
wire Iin_d_d23_d0 ;
wire Iout_vtree_in_d26_d0 ;
wire Iin_d_d29_d1 ;
wire Iout_vtree_in_d28_d0 ;
wire reset_B;
wire Iin_d_d10_d0 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d22_d1 ;
wire Iout_vtree_in_d3_d0 ;
wire Iout_vtree_in_d29_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d30_d1 ;
output Iout_d5 ;
wire Iout_vtree_in_d19_d0 ;
output Iout_d19 ;
output Iout_d8 ;
output Iout_d12 ;
output Iout_d11 ;
wire Idly_cfg0 ;
wire Iin_d_d9_d0 ;
wire Iin_d_d0_d1 ;
wire Iout_vtree_in_d9_d0 ;
output Iout_d17 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d13_d1 ;
wire Iout_vtree_in_d1_d0 ;
output Iout_d1 ;
wire Iout_vtree_in_d2_d0 ;
// --- instances
tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly (.out(Iout_r ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));

182
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4/netlist/verilog.v

@ -98,112 +98,112 @@ module tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4(Iin_d_d0_d0 ,
input reset_B;
// -- signals ---
wire Iin_d_d12_d0 ;
wire Iin_d_d2_d0 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d15_d1 ;
wire Iin_d_d23_d1 ;
output Iout_d8_d1 ;
output Iout_d2_d1 ;
wire Iin_d_d15_d0 ;
wire IA_flush_sr_B ;
output Iout_d18_d1 ;
output Iout_d11_d1 ;
wire Iin_d_d21_d1 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d1_d0 ;
output Iout_d20_d1 ;
wire Ireset_sb_in ;
output Iout_d22_d1 ;
output Iout_d13_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d11_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d12_d1 ;
wire I_resetX0 ;
wire Iin_d_d11_d1 ;
output Iout_d12_d1 ;
output Iout_d7_d1 ;
wire Iin_d_d14_d0 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d11_d0 ;
output Iout_d7_d0 ;
output Iout_d1_d0 ;
wire Iin_d_d2_d0 ;
wire reset_B;
output Iout_d5_d1 ;
output Iout_d3_d1 ;
wire Iin_d_d12_d1 ;
output Iout_d14_d1 ;
output Iout_d6_d0 ;
output Iout_d3_d0 ;
wire Iin_d_d22_d1 ;
wire _out_v ;
wire Iin_d_d4_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d21_d0 ;
output Iout_d8_d0 ;
wire Iin_d_d9_d1 ;
output Iout_d9_d0 ;
output Iout_d7_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d17_d1 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d0_d1 ;
wire Iin_d_d3_d1 ;
wire _flushBX ;
wire Iflush_inv_y ;
output Iout_d21_d1 ;
output Iout_d20_d1 ;
output Iout_d19_d1 ;
output Iout_d17_d0 ;
output Iout_d16_d0 ;
output Iout_d10_d1 ;
output Iout_d4_d1 ;
wire Iin_d_d21_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d7_d1 ;
output Iout_d0_d1 ;
wire _enBX ;
output Iout_d13_d0 ;
output Iout_d7_d1 ;
output Iout_d0_d0 ;
output Iout_d12_d1 ;
output Iout_d12_d0 ;
output Iout_d11_d0 ;
wire Iin_d_d11_d1 ;
wire _en ;
output Iout_d15_d1 ;
output Iout_d14_d0 ;
output Iout_d6_d1 ;
output Iout_d5_d0 ;
output Iout_d1_d1 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d5_d1 ;
output Iout_d18_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d13_d1 ;
wire _flush ;
wire Iin_d_d18_d0 ;
wire Iin_d_d7_d0 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d6_d1 ;
wire Iin_d_d4_d1 ;
wire Iin_d_d2_d1 ;
output Iout_d16_d1 ;
output Iout_d13_d0 ;
wire Iin_d_d9_d0 ;
output Iout_d22_d0 ;
output Iout_d6_d1 ;
wire _flushBX ;
output Iout_d11_d1 ;
output Iout_d8_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d18_d1 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d1_d1 ;
output Iout_d4_d0 ;
output Iout_d1_d0 ;
wire Iin_d_d8_d0 ;
output Iout_d2_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d20_d0 ;
output Iout_d19_d0 ;
output Iout_d16_d1 ;
wire Ien_inv_y ;
wire Iin_d_d17_d0 ;
wire Iin_d_d16_d0 ;
output Iout_d14_d1 ;
output Iout_d1_d1 ;
output Iout_d0_d1 ;
wire Iin_d_d3_d1 ;
output Iout_d8_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d0_d0 ;
output Iin_a ;
wire IA_flush_sr_B ;
output Iout_d18_d0 ;
output Iout_d15_d1 ;
output Iout_d12_d0 ;
wire Iin_d_d6_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d2_d1 ;
wire Iin_d_d10_d1 ;
wire I_resetX0 ;
output Iout_d6_d0 ;
output Iout_d2_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d6_d1 ;
wire _enBX ;
output Iout_d14_d0 ;
wire _out_vB ;
wire Iin_d_d5_d0 ;
wire Iin_d_d19_d1 ;
output Iout_d22_d0 ;
output Iin_a ;
wire reset_B;
output Iout_d15_d0 ;
wire _out_vB ;
wire Iin_d_d11_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d13_d1 ;
output Iout_d10_d1 ;
output Iout_d9_d0 ;
wire Iin_d_d20_d1 ;
wire Iin_d_d14_d1 ;
output Iout_d19_d0 ;
output Iout_d4_d1 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d0_d1 ;
wire _en ;
output Iout_d22_d1 ;
output Iout_d17_d1 ;
output Iout_d10_d0 ;
output Iout_d5_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d16_d0 ;
wire Iin_d_d19_d0 ;
wire Iin_d_d15_d1 ;
wire Ien_inv_y ;
output Iout_d15_d0 ;
output Iout_d0_d0 ;
wire Iin_d_d21_d1 ;
output Iout_d9_d1 ;
wire Iin_d_d18_d0 ;
output Iout_d21_d0 ;
wire Iin_d_d17_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d7_d1 ;
output Iout_d18_d1 ;
output Iout_d17_d0 ;
wire Iin_d_d9_d1 ;
output Iout_d3_d0 ;
wire _out_v ;
wire Iin_d_d12_d0 ;
wire Iin_d_d17_d1 ;
output Iout_d19_d1 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d3_d0 ;
wire Iin_d_d13_d1 ;
output Iout_d21_d1 ;
// --- instances
INV_X2 Iout_val_inv (.y(_out_vB), .a(_out_v), .vdd(vdd), .vss(vss));

12620
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0register__wr__array_36_723_764_4/netlist/verilog.v

File diff suppressed because it is too large Load Diff

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_3124_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_3124_4(in, Iout0 , vdd, vss);
// -- signals ---
wire in;
output Iout0 ;
wire in;
// --- instances
BUF_X12 Ibuf12 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_314_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_314_4(in, Iout0 , vdd, vss);
// -- signals ---
output Iout0 ;
wire in;
output Iout0 ;
// --- instances
BUF_X4 Ibuf4 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_323_4/netlist/verilog.v

@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_323_4(in, Iout0 , vdd, vss);
// -- signals ---
wire in;
output Iout0 ;
wire in;
// --- instances
BUF_X8 Ibuf8 (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

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