bics
/
actlib_dataflow_neuro
18
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

added decoder refhres to hybrid hs

This commit is contained in:
alexmadison 2022-04-13 17:41:35 +02:00
parent bf4af13e04
commit 67f8197e8d
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
dataflow_neuro/coders.act
View File

@ -382,9 +382,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply); buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// Decoder X/Y And trees // Decoder X/Y And trees
decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply); decoder_dualrail_refresh<NxC,Nx> d_dr_x(.supply = supply);
(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];) (i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply); decoder_dualrail_refresh<NyC,Ny> d_dr_y(.supply = supply);
(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];) (i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
// sig buf for reqx lines, since they go to synapse pull down gates. // sig buf for reqx lines, since they go to synapse pull down gates.
@ -398,10 +398,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
// Validity // Validity
vtree<NxC> vtree_x (.supply = supply); vtree<NxC> vtree_x (.supply = supply);
vtree<NyC> vtree_y (.supply = supply); vtree<NyC> vtree_y (.supply = supply);
(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;) (i:0..NxC-1:vtree_x.in.d[i].t = d_dr_x.final_refresh.d[i].t;)
(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;) (i:0..NxC-1:vtree_x.in.d[i].f = d_dr_x.final_refresh.d[i].f;)
(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;) (i:0..NyC-1:vtree_y.in.d[i].t = d_dr_y.final_refresh.d[i].t;)
(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;) (i:0..NyC-1:vtree_y.in.d[i].f = d_dr_y.final_refresh.d[i].f;)
A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v, A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
.vdd = supply.vdd, .vss = supply.vss); .vdd = supply.vdd, .vss = supply.vss);