bics/actlib_dataflow_neuro
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did some sram shit, doesnt matter

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alexmadison 2022-06-22 19:16:04 +02:00
parent 6daea1ef02
commit 6c1e079fd4
1 changed files with 0 additions and 6 deletions
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dataflow_neuro/chips.act
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@ -643,17 +643,11 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
pre_sram_slice.in.a = sram_dmx.out2.a; pre_sram_slice.in.a = sram_dmx.out2.a;
pre_sram_slice.in.v = sram_dmx.out2.v; pre_sram_slice.in.v = sram_dmx.out2.v;
(i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];) (i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31]; pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30]; pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29]; pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr, fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
.reset_B = _reset_BX, .supply = supply); .reset_B = _reset_BX, .supply = supply);
// fifo_out_sram_wr.in.a = pre_sram_slice.out.a;
// fifo_out_sram_wr.in.v = pre_sram_slice.out.v;
// (i:29:fifo_out_sram_wr.in.d.d[i] = pre_sram_slice.out.d.d[i];)
// fifo_out_sram_wr.in.d.d[29] = pre_sram_slice.in.d.d[31];
// spikes from sram // spikes from sram
// requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx] // requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]