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register_rw (formerly register_rw_v2) compiles

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Michele
2022-03-09 16:44:44 +01:00
parent d2f643dc26
commit 6f1a970cfd
5 changed files with 2763 additions and 15 deletions
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78
dataflow_neuro/registers.act
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@ -39,7 +39,7 @@ open std::channel;
namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// Circuit for storing registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
@ -51,7 +51,7 @@ namespace tmpl {
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
@ -110,9 +110,25 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power sup
)
)
}
// Circuit for storing and reading registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the MSB is write/read_B
// - the next MSB bits (size lognw) are the location,
// - the LSB (size wl) are the word to write
// out -> in case a reading phase is required, the output is used to show the stored data
// - the MSB bits (size lognw) tell the read register
// - the LSB bits (size wl) tell the word read
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
bool _ff_v;
pint nw = 1<<lognw;
//Validation of the input
avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
@ -122,28 +138,37 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
// vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
// sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Read or write?
AND2_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
AND3_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.c = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
in.v = _in_temp2.v;
_in_flag.d.d[0] = in.d.d[lognw+wl];
(i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_write, .out2 = _in_read, .cond = _in_flag,.reset_B = reset_B);
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_read, .out2 = _in_write, .cond = _in_flag,.reset_B = reset_B);
read_write_demux.supply= supply;
//WRITE PATH
// Validation
vtree<lognw+wl> val_input(.in = _in_write,.out = _in_write.v, .supply = supply);
vtree<wl>
Mx1of2<lognw+wl> _in_write_temp;
(i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
vtree<lognw+wl> val_input(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
//READ PATH
//Validation
vtree<lognw+wl> val_input(.in = _in_read,.out = _in_read.v, .supply = supply);
// Sending signal to the output
Mx1of2<lognw+wl> _in_read_temp;
(i:lognw+wl:_in_read_temp.d[i] = _in_read.d.d[i];)
vtree<lognw+wl> val_input_read(.in = _in_read_temp,.out = _in_read.v, .supply = supply);
vtree<wl> ff_validator;
Mx1of2<wl> _out_temp;
(i:wl:_out_temp.d[i] = out.d.d[i];)
ff_validator.in = _out_temp;
ff_validator.out = _ff_v;
ff_validator.supply = supply;
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl*2> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
@ -152,8 +177,13 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
andtree<lognw> atree[nw];
d1of<wl> _data_f;
AND2_X1 and_encoder[nw];
AND3_X1 reading_activator_t[nw*wl],reading_activator_f[nw*wl];
sigbuf<wl*2> clock_buffer[nw];
DFFQ_R_X1 ff_t[2*nw*wl],ff_f[2*nw*wl];
DFFQ_R_X1 ff_t[nw*wl],ff_f[nw*wl];
OR2_X1 ff_val[wl];
(i:wl..lognw:out.d.d[i] = in.d.d[i];)
bool __ffout_dualrail[nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
@ -167,8 +197,11 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
// Encode which work is the right one
atree[word_idx].out = _out_encoder[word_idx];
// READ: use the encoder selection to read the value
// WRITE: Activating the fake clock for the right word
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
@ -184,12 +217,27 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
ff_t[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_t[bit_idx+word_idx*(wl)].vss = supply.vss;
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx+nw-1].out[bit_idx];
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx+wl-1];
ff_f[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].f;
ff_f[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff_f[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)+nw-1];
ff_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_f[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_t[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].t;
reading_activator_t[bit_idx+word_idx*(wl)].b = ff_t[bit_idx+word_idx*(wl)].q;
reading_activator_t[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
reading_activator_t[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].t;
reading_activator_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
reading_activator_t[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_f[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].f;
reading_activator_f[bit_idx+word_idx*(wl)].b = ff_f[bit_idx+word_idx*(wl)].q;
reading_activator_f[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].f;
reading_activator_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
reading_activator_f[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_f[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
)
)
}