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register_rw (formerly register_rw_v2) compiles

This commit is contained in:
Michele 2022-03-09 16:44:44 +01:00
parent d2f643dc26
commit 6f1a970cfd
5 changed files with 2763 additions and 15 deletions
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76
dataflow_neuro/registers.act
View File

@ -39,7 +39,7 @@ open std::channel;
namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// Circuit for storing registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
@ -51,7 +51,7 @@ namespace tmpl {
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
@ -110,9 +110,25 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power sup
)
)
}
// Circuit for storing and reading registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the MSB is write/read_B
// - the next MSB bits (size lognw) are the location,
// - the LSB (size wl) are the word to write
// out -> in case a reading phase is required, the output is used to show the stored data
// - the MSB bits (size lognw) tell the read register
// - the LSB bits (size wl) tell the word read
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
bool _ff_v;
pint nw = 1<<lognw;
//Validation of the input
avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
@ -122,28 +138,37 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
// vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
// sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Read or write?
AND2_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
AND3_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.c = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
in.v = _in_temp2.v;
_in_flag.d.d[0] = in.d.d[lognw+wl];
(i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_write, .out2 = _in_read, .cond = _in_flag,.reset_B = reset_B);
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_read, .out2 = _in_write, .cond = _in_flag,.reset_B = reset_B);
read_write_demux.supply= supply;
//WRITE PATH
// Validation
vtree<lognw+wl> val_input(.in = _in_write,.out = _in_write.v, .supply = supply);
vtree<wl>
Mx1of2<lognw+wl> _in_write_temp;
(i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
vtree<lognw+wl> val_input(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
//READ PATH
//Validation
vtree<lognw+wl> val_input(.in = _in_read,.out = _in_read.v, .supply = supply);
// Sending signal to the output
Mx1of2<lognw+wl> _in_read_temp;
(i:lognw+wl:_in_read_temp.d[i] = _in_read.d.d[i];)
vtree<lognw+wl> val_input_read(.in = _in_read_temp,.out = _in_read.v, .supply = supply);
vtree<wl> ff_validator;
Mx1of2<wl> _out_temp;
(i:wl:_out_temp.d[i] = out.d.d[i];)
ff_validator.in = _out_temp;
ff_validator.out = _ff_v;
ff_validator.supply = supply;
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl*2> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
@ -152,8 +177,13 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
andtree<lognw> atree[nw];
d1of<wl> _data_f;
AND2_X1 and_encoder[nw];
AND3_X1 reading_activator_t[nw*wl],reading_activator_f[nw*wl];
sigbuf<wl*2> clock_buffer[nw];
DFFQ_R_X1 ff_t[2*nw*wl],ff_f[2*nw*wl];
DFFQ_R_X1 ff_t[nw*wl],ff_f[nw*wl];
OR2_X1 ff_val[wl];
(i:wl..lognw:out.d.d[i] = in.d.d[i];)
bool __ffout_dualrail[nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
@ -167,8 +197,11 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
// Encode which work is the right one
atree[word_idx].out = _out_encoder[word_idx];
// READ: use the encoder selection to read the value
// WRITE: Activating the fake clock for the right word
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
@ -184,12 +217,27 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
ff_t[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_t[bit_idx+word_idx*(wl)].vss = supply.vss;
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx+nw-1].out[bit_idx];
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx+wl-1];
ff_f[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].f;
ff_f[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff_f[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)+nw-1];
ff_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_f[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_t[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].t;
reading_activator_t[bit_idx+word_idx*(wl)].b = ff_t[bit_idx+word_idx*(wl)].q;
reading_activator_t[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
reading_activator_t[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].t;
reading_activator_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
reading_activator_t[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_f[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].f;
reading_activator_f[bit_idx+word_idx*(wl)].b = ff_f[bit_idx+word_idx*(wl)].q;
reading_activator_f[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].f;
reading_activator_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
reading_activator_f[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_f[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
)
)
}

275
test/unit_tests/register_wrw/run/prsim.out Normal file
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@ -0,0 +1,275 @@
t.registers.read_write_demux.vc.ct.in[0] t.registers._clock_word_temp[0] t.registers.ff_f[4].clk_B t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.atree[2].in[1] t.registers.read_write_demux._in_v t.registers.read_write_demux._c_v t.registers.reading_activator_f[0].a t.registers.ff_t[0].d t.registers.ff_f[4].__clk_B t.registers.ff_t[0]._clk_B t.registers.ff_f[5]._clk_B t.registers.atree[0].in[1] t.registers.atree[0].in[0] t.registers.ff_f[6].clk_B t.registers.clock_buffer[1].buf1._y t.registers._out_encoder[2] t.registers.read_write_demux._out1_a_BX_t[0] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.ff_t[1]._clk_B t.registers.ff_f[0].d t.registers.atree[1].in[0] t.in.v t.registers.ff_t[4]._clk_B t.registers.ff_t[1].d t.registers.ff_f[0].clk_B t.registers.read_write_demux._out1_a_B t.registers.read_write_demux._c_t_buf[0] t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.read_write_demux._out2_a_BX_t[0] t.registers.ff_val[1].y t.registers.read_write_demux._out2_a_BX_f[0] t.registers.read_write_demux._out1_a_BX_f[0] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ff_f[1].d t.registers.ff_t[5]._clk_B t.registers.ff_t[4].__clk_B t.registers.reading_activator_t[0].a t.registers.clk_X.buf1._y t.registers.read_write_demux._c_f_buf[0] t.registers._clock_temp t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers._out_encoder[3] t.registers.read_write_demux.vc.ct.in[1] t.registers.clk_dly.dly[1]._y t.registers.read_write_demux.c_f_c_t_or._y t.registers.ff_t[0].__clk_B t.registers.ff_t[2]._clk_B t.registers.ff_val[1]._y t.registers.read_write_demux.vc.ct.in[2] t.registers._clock_word_temp[1] t.registers.clk_dly.mu2[0]._s t.registers.clock_buffer[2].buf1._y t.registers.ff_t[1].__clk_B t.registers.read_write_demux.in_v_buf._y t.registers.read_write_demux.out1_a_B_buf_f.buf1._y t.registers.clk_dly.dly[1].__y t.registers.ff_f[7]._clk_B t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.read_write_demux._out2_a_B t.dly_cfg[0] t.registers.and_encoder[0]._y t.registers.clk_dly._a[1] t.registers.read_write_demux._in_c_v_ t.registers.ff_f[2].__clk_B t.registers.read_write_demux.vc.ct.in[3] t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.read_write_demux.vc.ct.tmp[4] t.registers.read_write_demux.c_el._y t.registers.ff_f[7].__clk_B t.registers._in_read.a t.registers.read_write_demux.vc.OR2_tf[2]._y t.registers._clock_word_temp[2] t.registers.atree[2].and2s[0]._y t.registers.ff_f[0].__clk_B t.registers._in_write.a t.registers.ff_val[0].y t.registers.ff_t[6]._clk_B t.registers.read_write_demux.vc.ct.C2Els[1]._y t.registers.ff_f[4]._clk_B t.registers.read_write_demux.vc.OR2_tf[0]._y t.registers.clk_dly.dly[2].___y t.registers.read_write_demux.vc.ct.C2Els[2]._y t.registers.ff_f[2].clk_B t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.read_write_demux.vc.ct.tmp[5] t.registers.read_write_demux.vc.ct.C2Els[0]._y t.registers.clk_dly.dly[1].y t.registers.ff_f[2]._clk_B t.registers.clk_dly.dly[2].y t.registers.read_write_demux.c_buf_f.buf1._y t.registers.ff_val[1].b t.registers.read_write_demux.out1_a_B_buf_t.buf1._y t.registers.ff_val[0].a t.registers.ff_t[2].__clk_B t.registers.atree[1].and2s[0]._y t.registers.ff_f[3].__clk_B t.registers.ff_f[6].__clk_B t.registers.and_encoder[2]._y t.registers.ff_f[6]._clk_B t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_f[0]._clk_B t.registers.read_write_demux.c_buf_t.buf1._y t.registers.ff_val[1].a t.registers.ff_t[3]._clk_B t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.ff_f[1]._clk_B t.registers.ff_val[0]._y t.registers.ff_t[7].__clk_B t.registers.ff_t[7]._clk_B t.registers.read_write_demux.vc.OR2_tf[1]._y t.registers.ff_f[5].__clk_B t.registers.ff_f[1].__clk_B t.registers.and_encoder[1]._y t.registers.ff_t[5].__clk_B t.registers.ff_t[6].__clk_B t.registers.and_encoder[3]._y t.registers.read_write_demux.vc.OR2_tf[3]._y t.registers.ff_t[3].__clk_B t.registers.ff_f[3]._clk_B
[0] start test
Node `t._in_write.d.d[0].f' not found
Node `t._in_read.d.d[0].f' not found
250599 t.registers.ff_f[0].d : 0
250599 Reset : 0
250599 t.registers._in_read.a : 0
250599 t.registers.ff_f[1].d : 0
250599 t.registers.atree[0].in[1] : 0
250599 t.registers._in_write.a : 0
250599 t.registers.atree[1].in[0] : 0
250599 t.registers.ff_t[0].d : 0
250599 t.registers.atree[0].in[0] : 0
250599 t.registers.reading_activator_t[0].a : 0
250599 t.registers.ff_t[1].d : 0
250599 t.registers.reading_activator_f[0].a : 0
250599 t.registers.atree[2].in[1] : 0
250600 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.registers.ff_t[1].d:=0]
250602 t.registers.read_write_demux._out1_a_B : 1 [by t.registers._in_read.a:=0]
250603 t.registers.read_write_demux.c_buf_f.buf1._y : 1 [by t.registers.reading_activator_f[0].a:=0]
250603 t.registers.read_write_demux.out1_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1]
250647 t._reset_B : 1 [by Reset:=0]
250659 t.registers.reset_buf_BXX._y : 0 [by t._reset_B:=1]
250672 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.registers.reading_activator_f[0].a:=0]
250673 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1]
250696 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1]
250738 t.registers.read_write_demux.out1_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1]
250772 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0]
250777 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0]
250778 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1]
250783 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.registers.reading_activator_t[0].a:=0]
250794 t.registers.read_write_demux._out1_a_BX_t[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_f.buf1._y:=0]
250815 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0]
250816 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1]
250844 t.registers.read_write_demux._out1_a_BX_f[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_t.buf1._y:=0]
251426 t.registers.atree[2].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0]
251688 t.registers._reset_mem_BX : 1 [by t.registers.reset_buf_BXX._y:=0]
251701 t.registers.reset_bufarray.buf6._y : 0 [by t.registers._reset_mem_BX:=1]
253118 t.registers._out_encoder[2] : 0 [by t.registers.atree[2].and2s[0]._y:=1]
253475 t.registers.and_encoder[2]._y : 1 [by t.registers._out_encoder[2]:=0]
253500 t.registers._clock_word_temp[2] : 0 [by t.registers.and_encoder[2]._y:=1]
253521 t.registers.clock_buffer[2].buf1._y : 1 [by t.registers._clock_word_temp[2]:=0]
253522 t.registers.ff_f[4].clk_B : 0 [by t.registers.clock_buffer[2].buf1._y:=1]
253523 t.registers.ff_f[5]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0]
253523 t.registers.ff_t[4]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0]
253528 t.registers.ff_t[4].__clk_B : 0 [by t.registers.ff_t[4]._clk_B:=1]
253683 t.registers.ff_t[5]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0]
254264 t.registers.ff_t[5].__clk_B : 0 [by t.registers.ff_t[5]._clk_B:=1]
254380 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0]
254547 t.registers.read_write_demux.reset_buf._y : 0 [by t._reset_B:=1]
254558 t.registers.read_write_demux._reset_BX : 1 [by t.registers.read_write_demux.reset_buf._y:=0]
254560 t.registers.ff_f[5].__clk_B : 0 [by t.registers.ff_f[5]._clk_B:=1]
254606 t.registers.reset_buf_BX._y : 0 [by t._reset_B:=1]
254620 t.registers._reset_BX : 1 [by t.registers.reset_buf_BX._y:=0]
254788 t.registers.ff_f[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1]
254792 t.registers.ff_f[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
254806 t.registers.ff_f[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
254892 t.registers.ff_t[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
255120 t.registers.ff_t[0].__clk_B : 0 [by t.registers.ff_t[0]._clk_B:=1]
255605 t.registers.read_write_demux.reset_bufarray.buf3._y : 0 [by t.registers.read_write_demux._reset_BX:=1]
255996 t.registers.ff_f[1].__clk_B : 0 [by t.registers.ff_f[1]._clk_B:=1]
256448 t.registers.read_write_demux._reset_BXX[0] : 1 [by t.registers.read_write_demux.reset_bufarray.buf3._y:=0]
256550 t.registers.atree[3].and2s[0]._y : 1 [by t.registers.atree[1].in[0]:=0]
258009 t.registers._out_encoder[3] : 0 [by t.registers.atree[3].and2s[0]._y:=1]
258079 t.registers.and_encoder[3]._y : 1 [by t.registers._out_encoder[3]:=0]
262498 t.registers.read_write_demux._out2_a_B : 1 [by t.registers._in_write.a:=0]
262501 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1]
262509 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1]
262555 t.registers.read_write_demux._out2_a_BX_t[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=0]
263170 t.registers.ff_f[4]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0]
263261 t.registers.ff_f[0].__clk_B : 0 [by t.registers.ff_f[0]._clk_B:=1]
263657 t.registers.read_write_demux._out2_a_BX_f[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=0]
264331 t.registers.ff_f[4].__clk_B : 0 [by t.registers.ff_f[4]._clk_B:=1]
268685 t.registers._reset_mem_BXX[0] : 1 [by t.registers.reset_bufarray.buf6._y:=0]
269649 t.registers.read_write_demux._c_f_buf[0] : 0 [by t.registers.read_write_demux.c_buf_f.buf1._y:=1]
271576 t.registers.atree[1].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0]
274158 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1]
280228 t.registers._out_encoder[1] : 0 [by t.registers.atree[1].and2s[0]._y:=1]
280309 t.registers.and_encoder[1]._y : 1 [by t.registers._out_encoder[1]:=0]
286232 t.registers.ff_t[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
287887 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.registers.atree[2].in[1]:=0]
287979 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1]
290084 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.registers.ff_t[0].d:=0]
291386 t.registers._clock_word_temp[1] : 0 [by t.registers.and_encoder[1]._y:=1]
293130 t.registers.clock_buffer[1].buf1._y : 1 [by t.registers._clock_word_temp[1]:=0]
293743 t.registers.ff_f[2].clk_B : 0 [by t.registers.clock_buffer[1].buf1._y:=1]
293788 t.registers.ff_f[3]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0]
294313 t.registers.ff_f[3].__clk_B : 0 [by t.registers.ff_f[3]._clk_B:=1]
294740 t.registers.ff_t[2]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0]
295392 t.registers.ff_t[3]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0]
295444 t.registers.ff_t[3].__clk_B : 0 [by t.registers.ff_t[3]._clk_B:=1]
295640 t.registers.ff_t[2].__clk_B : 0 [by t.registers.ff_t[2]._clk_B:=1]
295778 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1]
295785 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[2]:=0]
298395 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1]
304215 t.registers.ff_t[1].__clk_B : 0 [by t.registers.ff_t[1]._clk_B:=1]
304862 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[0]:=0]
304864 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1]
307765 t.registers.ff_f[2]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0]
308119 t.registers.ff_f[2].__clk_B : 0 [by t.registers.ff_f[2]._clk_B:=1]
308501 t.registers._clock_word_temp[3] : 0 [by t.registers.and_encoder[3]._y:=1]
308634 t.registers.clock_buffer[3].buf1._y : 1 [by t.registers._clock_word_temp[3]:=0]
308635 t.registers.ff_f[6].clk_B : 0 [by t.registers.clock_buffer[3].buf1._y:=1]
308636 t.registers.ff_t[7]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0]
308639 t.registers.ff_f[6]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0]
308718 t.registers.ff_f[6].__clk_B : 0 [by t.registers.ff_f[6]._clk_B:=1]
309181 t.registers.ff_f[7]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0]
311397 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1]
311485 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[5]:=0]
311614 t.registers.ff_f[7].__clk_B : 0 [by t.registers.ff_f[7]._clk_B:=1]
319267 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1]
319326 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0]
319356 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1]
321014 t.registers.ff_t[7].__clk_B : 0 [by t.registers.ff_t[7]._clk_B:=1]
347594 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0]
349061 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1]
354198 t.registers.ff_t[6]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0]
413702 t.registers.ff_t[6].__clk_B : 0 [by t.registers.ff_t[6]._clk_B:=1]
t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.clk_dly.and2[1]._y t.registers.clk_dly.dly[1].a t.registers.ff_val[1].y t.registers.clk_X.buf1._y t.registers._clock_temp t.registers.clk_dly.dly[1]._y t.registers.ff_val[1]._y t.registers.clk_dly.mu2[0]._s t.registers.clk_dly.dly[1].__y t.registers.clk_dly.mu2[0]._y t.dly_cfg[0] t.registers.clk_dly._a[1] t.registers.clk_dly.dly[2].__y t.registers.ff_val[0].y t.registers.clk_dly.dly[2].___y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.clk_dly.dly[1].y t.registers.clk_dly.dly[2].y t.registers.ff_val[1].b t.registers.ff_val[0].a t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_val[1].a t.registers.clk_dly.mu2[1]._y t.registers.ff_val[0]._y
[1] reset completed
413702 t.dly_cfg[0] : 1
413702 t.dly_cfg[1] : 1
414387 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
433086 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
449801 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.mu2[0]._s:=0]
449928 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1]
450097 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0]
450140 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1]
450152 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0]
451431 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1]
451664 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0]
451667 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1]
451705 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0]
451706 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1]
464458 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0]
464550 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1]
467277 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0]
467279 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1]
467280 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0]
468781 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1]
468783 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0]
[2] delay line set
468783 t.registers.ff_t[0].d : 1
468783 t.registers.reading_activator_t[0].a : 1
468783 t.registers.atree[0].in[0] : 1
468783 t.registers.ff_t[1].d : 1
468783 t.registers.atree[0].in[1] : 1
468788 t.registers.read_write_demux.vc.OR2_tf[3]._y : 0 [by t.registers.atree[0].in[1]:=1]
468791 t.registers.read_write_demux.vc.OR2_tf[2]._y : 0 [by t.registers.atree[0].in[0]:=1]
468792 t.registers.read_write_demux.vc.ct.in[2] : 1 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=0]
468801 t.registers.read_write_demux.vc.OR2_tf[0]._y : 0 [by t.registers.ff_t[0].d:=1]
468837 t.registers.read_write_demux.vc.OR2_tf[1]._y : 0 [by t.registers.ff_t[1].d:=1]
468838 t.registers.read_write_demux.vc.ct.in[1] : 1 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=0]
468902 t.registers.read_write_demux.c_f_c_t_or._y : 0 [by t.registers.reading_activator_t[0].a:=1]
468939 t.registers.read_write_demux.vc.ct.in[0] : 1 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=0]
468966 t.registers.read_write_demux._c_v : 1 [by t.registers.read_write_demux.c_f_c_t_or._y:=0]
469062 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 0 [by t.registers.read_write_demux.vc.ct.in[0]:=1]
469064 t.registers.read_write_demux.vc.ct.tmp[4] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=0]
469855 t.registers.read_write_demux.vc.ct.in[3] : 1 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=0]
469892 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 0 [by t.registers.read_write_demux.vc.ct.in[3]:=1]
470035 t.registers.read_write_demux.vc.ct.tmp[5] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=0]
470086 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 0 [by t.registers.read_write_demux.vc.ct.tmp[5]:=1]
470528 t.registers.read_write_demux._in_v : 1 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=0]
470529 t.registers.read_write_demux.c_el._y : 0 [by t.registers.read_write_demux._in_v:=1]
470538 t.registers.read_write_demux._in_c_v_ : 1 [by t.registers.read_write_demux.c_el._y:=0]
470539 t.registers.read_write_demux.in_v_buf._y : 0 [by t.registers.read_write_demux._in_v:=1]
470564 t.in.v : 1 [by t.registers.read_write_demux.in_v_buf._y:=0]
474503 t.registers.read_write_demux.c_buf_t.buf1._y : 0 [by t.registers.reading_activator_t[0].a:=1]
484756 t.registers.read_write_demux._c_t_buf[0] : 1 [by t.registers.read_write_demux.c_buf_t.buf1._y:=0]
484901 t.registers.read_write_demux.out1_f_buf_func[3]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
484986 t.registers.read_write_demux.out1_t_buf_func[1]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
485000 t.registers._in_read_temp.d[1].t : 1 [by t.registers.read_write_demux.out1_t_buf_func[1]._y:=0]
485592 t.registers._in_read_temp.d[3].f : 1 [by t.registers.read_write_demux.out1_f_buf_func[3]._y:=0]
486543 t.registers.val_input_read.OR2_tf[1]._y : 0 [by t.registers._in_read_temp.d[1].t:=1]
487203 t.registers.val_input_read.OR2_tf[3]._y : 0 [by t.registers._in_read_temp.d[3].f:=1]
487214 t.registers.val_input_read.ct.in[3] : 1 [by t.registers.val_input_read.OR2_tf[3]._y:=0]
488277 t.registers.read_write_demux.out1_f_buf_func[2]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
488278 t.registers._in_read_temp.d[2].f : 1 [by t.registers.read_write_demux.out1_f_buf_func[2]._y:=0]
488279 t.registers.val_input_read.OR2_tf[2]._y : 0 [by t.registers._in_read_temp.d[2].f:=1]
494780 t.registers.val_input_read.ct.in[2] : 1 [by t.registers.val_input_read.OR2_tf[2]._y:=0]
495419 t.registers.val_input_read.ct.C2Els[1]._y : 0 [by t.registers.val_input_read.ct.in[2]:=1]
497212 t.registers.val_input_read.ct.tmp[5] : 1 [by t.registers.val_input_read.ct.C2Els[1]._y:=0]
500924 t.registers.read_write_demux.out1_t_buf_func[0]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
501056 t.registers._in_read_temp.d[0].t : 1 [by t.registers.read_write_demux.out1_t_buf_func[0]._y:=0]
501057 t.registers.val_input_read.OR2_tf[0]._y : 0 [by t.registers._in_read_temp.d[0].t:=1]
501074 t.registers.val_input_read.ct.in[0] : 1 [by t.registers.val_input_read.OR2_tf[0]._y:=0]
504055 t.registers.val_input_read.ct.in[1] : 1 [by t.registers.val_input_read.OR2_tf[1]._y:=0]
504207 t.registers.val_input_read.ct.C2Els[0]._y : 0 [by t.registers.val_input_read.ct.in[1]:=1]
507190 t.registers.val_input_read.ct.tmp[4] : 1 [by t.registers.val_input_read.ct.C2Els[0]._y:=0]
507193 t.registers.val_input_read.ct.C2Els[2]._y : 0 [by t.registers.val_input_read.ct.tmp[4]:=1]
507617 t.registers._in_read.v : 1 [by t.registers.val_input_read.ct.C2Els[2]._y:=0]
507623 t.registers.read_write_demux.out_or._y : 0 [by t.registers._in_read.v:=1]
510211 t.registers.read_write_demux._out_v : 1 [by t.registers.read_write_demux.out_or._y:=0]
512672 t.registers.read_write_demux.inack_ctl._y : 0 [by t.registers.read_write_demux._out_v:=1]
513502 t.registers.ack_and.a : 1 [by t.registers.read_write_demux.inack_ctl._y:=0]
519321 t.registers.atree[0].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1]
519323 t.registers._out_encoder[0] : 1 [by t.registers.atree[0].and2s[0]._y:=0]
519517 t.registers.and_encoder[0]._y : 0 [by t.registers._out_encoder[0]:=1]
520120 t.registers._clock_word_temp[0] : 1 [by t.registers.and_encoder[0]._y:=0]
520258 t.registers.clock_buffer[0].buf1._y : 0 [by t.registers._clock_word_temp[0]:=1]
520275 t.registers.ff_f[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0]
520276 t.registers.ff_t[0]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1]
520276 t.registers.ff_t[1]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1]
520277 t.registers.ff_t[1].__clk_B : 1 [by t.registers.ff_t[1]._clk_B:=0]
520292 t.registers.ff_f[0]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1]
520296 t.registers.ff_t[1]._mqib : 0 [by t.registers.ff_t[1].__clk_B:=1]
520460 t.registers.ff_f[0].__clk_B : 1 [by t.registers.ff_f[0]._clk_B:=0]
520701 t.registers.ff_f[1]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1]
520835 t.registers.ff_t[1]._mqi : 1 [by t.registers.ff_t[1]._mqib:=0]
520862 t.registers.ff_f[1].__clk_B : 1 [by t.registers.ff_f[1]._clk_B:=0]
521302 t.registers.ff_t[0].__clk_B : 1 [by t.registers.ff_t[0]._clk_B:=0]
521475 t.registers.ff_t[0]._mqib : 0 [by t.registers.ff_t[0].__clk_B:=1]
524022 t.registers.ff_t[0]._mqi : 1 [by t.registers.ff_t[0]._mqib:=0]
536434 t.registers.read_write_demux._en : 0 [by t.registers.ack_and.a:=1]
536435 t.registers.read_write_demux.out1_en_buf_t.buf1._y : 1 [by t.registers.read_write_demux._en:=0]
536435 t.registers.read_write_demux.out2_en_buf_t.buf1._y : 1 [by t.registers.read_write_demux._en:=0]
536642 t.registers.read_write_demux._en1_X_t[0] : 0 [by t.registers.read_write_demux.out1_en_buf_t.buf1._y:=1]
536824 t.registers.read_write_demux.out1_en_buf_f.buf1._y : 1 [by t.registers.read_write_demux._en:=0]
536852 t.registers.read_write_demux._en1_X_f[0] : 0 [by t.registers.read_write_demux.out1_en_buf_f.buf1._y:=1]
537268 t.registers.read_write_demux._en2_X_t[0] : 0 [by t.registers.read_write_demux.out2_en_buf_t.buf1._y:=1]
551495 t.registers.read_write_demux.out2_en_buf_f.buf1._y : 1 [by t.registers.read_write_demux._en:=0]
551502 t.registers.read_write_demux._en2_X_f[0] : 0 [by t.registers.read_write_demux.out2_en_buf_f.buf1._y:=1]
WRONG ASSERT: "t.registers._in_write.d.d[0].t" has value 0 and not 1.
WRONG ASSERT: "t.registers._in_write.d.d[1].t" has value 0 and not 1.
WRONG ASSERT: "t.registers._in_write.d.d[2].f" has value 0 and not 1.
WRONG ASSERT: "t.registers._in_write.d.d[3].f" has value 0 and not 1.
WRONG ASSERT: "t.registers._clock" has value 1 and not 0.
551502 t.registers.ff_t[0].d : 0
551502 t.registers.reading_activator_t[0].a : 0
551502 t.registers.atree[0].in[0] : 0
551502 t.registers.ff_t[1].d : 0
551502 t.registers.atree[0].in[1] : 0
551506 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.registers.ff_t[0].d:=0]
551645 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1]
551668 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0]
551916 t.registers.ff_t[0]._mqib : 1 [by t.registers.ff_t[0].d:=0]
552111 t.registers.ff_t[0]._mqi : 0 [by t.registers.ff_t[0]._mqib:=1]
552358 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0]
552360 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1]
552435 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.registers.ff_t[1].d:=0]
553281 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.registers.reading_activator_t[0].a:=0]
553287 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1]
560147 t.registers.ff_t[1]._mqib : 1 [by t.registers.ff_t[1].d:=0]
560401 t.registers.ff_t[1]._mqi : 0 [by t.registers.ff_t[1]._mqib:=1]
574376 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.registers.reading_activator_t[0].a:=0]
574384 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1]
577877 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1]
577878 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0]
577884 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1]
591372 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0]
594462 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1]
594688 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[2]:=0]
595507 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1]
605884 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1]
605885 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[1]:=0]
605891 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1]
605893 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[4]:=0]
609455 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1]
609470 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0]
609577 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1]
628920 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0]
629013 t.registers.ff_f[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1]
629771 t.registers.ff_t[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
630256 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0]
630257 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1]
630487 t.registers.ff_t[0].__clk_B : 0 [by t.registers.ff_t[0]._clk_B:=1]
630665 t.registers.ff_f[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
631636 t.registers.ff_t[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
631637 t.registers.ff_t[1].__clk_B : 0 [by t.registers.ff_t[1]._clk_B:=1]
632405 t.registers.ff_f[0].__clk_B : 0 [by t.registers.ff_f[0]._clk_B:=1]
632952 t.registers.ff_f[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0]
645104 t.registers.ff_f[1].__clk_B : 0 [by t.registers.ff_f[1]._clk_B:=1]
[3] clock checked
Node `t.registers.ff[0].q' not found
Node `t.registers.ff[1].q' not found

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test/unit_tests/register_wrw/run/test.prs Normal file
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test/unit_tests/register_wrw/test.act Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[2]){
register_rw<2,2,2> registers(.in=in,.data = data,.out = out);
//Low active Reset
bool _reset_B;
power _supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}
register_test t;

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watchall
system "echo '[0] start test'"
set-qdi-channel-neutral "t.in" 5
set-qdi-channel-neutral "t._in_write" 5
set-qdi-channel-neutral "t._in_read" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.registers._in_write.a 0
set t.registers._in_read.a 0
set t.registers._in_write.v 0
set t.registers._in_read.v 0
set Reset 0
cycle
status X
mode run
assert-qdi-channel-neutral "t.in" 5
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 19
cycle
assert-qdi-channel-valid "t.registers._in_write" 4 3
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"