regennmed tdc no read to have the same number of reg bits as normal tdcg

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/verilog.v

@@ -7,10 +7,10 @@ module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vs
    output out;
 
 // -- signals ---
-   wire out ;
-   wire Iin1 ;
    wire Iin2 ;
+   wire Iin1 ;
    wire Iin0 ;
+   wire out ;
 
 // --- instances
 AND3_X1 Iand3s0  (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_34_4/netlist/verilog.v

@@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0andtree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out,
    output out;
 
 // -- signals ---
-   wire Iin1 ;
-   wire Itmp4 ;
-   wire Iin2 ;
    wire out ;
-   wire Iin3 ;
+   wire Iin2 ;
    wire Iin0 ;
+   wire Itmp4 ;
+   wire Iin1 ;
    wire Itmp5 ;
+   wire Iin3 ;
 
 // --- instances
 AND2_X1 Iand2s0  (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_35_4/netlist/verilog.v

@@ -9,14 +9,14 @@ module tmpl_0_0dataflow__neuro_0_0andtree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
    output out;
 
 // -- signals ---
-   wire Iin0 ;
    wire Itmp5 ;
-   wire Iin1 ;
    wire Iin4 ;
-   wire Iin3 ;
-   wire Itmp6 ;
+   wire Iin1 ;
+   wire Iin0 ;
    wire out ;
    wire Iin2 ;
+   wire Iin3 ;
+   wire Itmp6 ;
 
 // --- instances
 AND3_X1 Iand3s0  (.y(Itmp6 ), .a(Iin2 ), .b(Iin3 ), .c(Iin4 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_36_4/netlist/verilog.v

@@ -10,16 +10,16 @@ module tmpl_0_0dataflow__neuro_0_0andtree_36_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
    output out;
 
 // -- signals ---
-   wire Itmp7 ;
    wire Iin3 ;
-   wire Itmp8 ;
-   wire Iin0 ;
-   wire Iin2 ;
+   wire out ;
    wire Iin1 ;
    wire Itmp6 ;
-   wire out ;
+   wire Iin2 ;
    wire Iin5 ;
+   wire Itmp7 ;
+   wire Itmp8 ;
    wire Iin4 ;
+   wire Iin0 ;
 
 // --- instances
 AND3_X1 Iand3s0  (.y(out), .a(Itmp6 ), .b(Itmp7 ), .c(Itmp8 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_39_4/netlist/verilog.v

@@ -13,22 +13,22 @@ module tmpl_0_0dataflow__neuro_0_0andtree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
    output out;
 
 // -- signals ---
-   wire Iin5 ;
-   wire out ;
-   wire Itmp10 ;
-   wire Itmp14 ;
-   wire Itmp9 ;
-   wire Iin3 ;
-   wire Iin8 ;
    wire Itmp11 ;
    wire Iin1 ;
-   wire Iin0 ;
-   wire Iin2 ;
-   wire Itmp13 ;
-   wire Iin7 ;
+   wire Iin5 ;
+   wire Iin8 ;
+   wire out ;
+   wire Itmp10 ;
    wire Iin4 ;
-   wire Iin6 ;
+   wire Itmp14 ;
+   wire Iin7 ;
    wire Itmp12 ;
+   wire Iin0 ;
+   wire Itmp13 ;
+   wire Itmp9 ;
+   wire Iin6 ;
+   wire Iin3 ;
+   wire Iin2 ;
 
 // --- instances
 AND3_X1 Iand3s0  (.y(Itmp12 ), .a(Iin6 ), .b(Iin7 ), .c(Iin8 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/verilog.v

@@ -68,72 +68,72 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
    input Isupply_vss ;
 
 // -- signals ---
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d30_d0 ;
-   wire Iin_d_d12_d0 ;
-   output Iout_d_d31_d1 ;
-   wire Iin_d_d19_d0 ;
-   wire Iin_d_d13_d1 ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d26_d1 ;
-   wire Iin_d_d2_d0 ;
-   wire Iin_d_d22_d0 ;
-   wire Iin_d_d16_d0 ;
-   wire Iin_d_d15_d0 ;
    wire Iin_d_d27_d0 ;
-   wire Iin_d_d22_d1 ;
-   wire Iin_d_d21_d0 ;
-   wire Iin_d_d25_d0 ;
-   wire Iin_d_d23_d0 ;
-   wire Iin_d_d7_d0 ;
-   wire Iin_d_d17_d1 ;
    wire Iin_d_d16_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Iin_d_d10_d1 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d20_d1 ;
    wire Iin_d_d10_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d29_d1 ;
    wire Iin_d_d4_d1 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d19_d0 ;
    wire Iin_d_d3_d1 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d23_d0 ;
+   wire Isupply_vss ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_d_d31_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d5_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Isb_in ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d26_d1 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d6_d0 ;
+   output Iout_d_d31_d0 ;
    wire Iin_d_d28_d1 ;
    wire Iin_d_d19_d1 ;
-   wire Iin_d_d15_d1 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d20_d1 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d31_d0 ;
-   wire Iin_d_d29_d1 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d0_d0 ;
-   wire Isb_in ;
-   wire Iin_d_d25_d1 ;
-   wire Iin_d_d24_d0 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d9_d1 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d18_d0 ;
-   wire Iin_d_d14_d1 ;
-   wire Iin_d_d5_d0 ;
-   wire Iin_d_d30_d1 ;
-   wire Iin_d_d27_d1 ;
-   wire Iin_d_d8_d1 ;
-   wire Iin_d_d21_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d23_d1 ;
+   wire Iin_d_d30_d0 ;
    wire Iin_d_d26_d0 ;
-   wire Iin_d_d8_d0 ;
-   wire Isupply_vss ;
-   wire Iin_d_d17_d0 ;
-   wire Iin_d_d13_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d27_d1 ;
    wire Iin_d_d12_d1 ;
-   wire Iin_d_d5_d1 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d29_d0 ;
-   wire Iin_d_d7_d1 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d2_d0 ;
 
 // --- instances
 TIELO_X1 Itielows0  (.y(Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v

@@ -68,72 +68,72 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
    input Isupply_vss ;
 
 // -- signals ---
-   wire Iin_d_d28_d1 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d13_d0 ;
-   wire Iin_d_d7_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d25_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Isupply_vss ;
-   wire Iin_d_d16_d1 ;
    wire Iin_d_d13_d1 ;
-   wire Iin_d_d9_d1 ;
-   wire Iin_d_d30_d0 ;
-   wire Iin_d_d23_d0 ;
-   wire Iin_d_d19_d1 ;
-   wire Iin_d_d18_d0 ;
-   wire Iin_d_d17_d0 ;
-   wire Iin_d_d10_d0 ;
    wire Iin_d_d6_d1 ;
-   wire Iin_d_d0_d0 ;
-   wire Iin_d_d21_d1 ;
-   wire Iin_d_d12_d0 ;
-   wire Iin_d_d22_d0 ;
-   wire Iin_d_d20_d1 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d27_d1 ;
-   wire Iin_d_d26_d1 ;
-   wire Iin_d_d19_d0 ;
-   output Iout_d_d31_d1 ;
-   wire Iin_d_d30_d1 ;
-   wire Iin_d_d5_d0 ;
-   wire Isb_in ;
-   wire Iin_d_d8_d0 ;
-   wire Iin_d_d23_d1 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d16_d0 ;
-   wire Iin_d_d15_d1 ;
-   wire Iin_d_d14_d1 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d3_d1 ;
-   output Iout_d_d31_d0 ;
-   wire Iin_d_d17_d1 ;
-   wire Iin_d_d12_d1 ;
-   wire Iin_d_d9_d0 ;
    wire Iin_d_d21_d0 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d29_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d5_d1 ;
+   wire Iin_d_d2_d1 ;
+   wire Isupply_vss ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d15_d1 ;
    wire Iin_d_d24_d0 ;
-   wire Iin_d_d3_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d14_d1 ;
    wire Iin_d_d2_d0 ;
    wire Iin_d_d22_d1 ;
-   wire Iin_d_d4_d1 ;
-   wire Iin_d_d27_d0 ;
-   wire Iin_d_d20_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d11_d0 ;
    wire Iin_d_d15_d0 ;
-   wire Iin_d_d8_d1 ;
-   wire Iin_d_d29_d0 ;
+   wire Iin_d_d25_d1 ;
+   output Iout_d_d31_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d3_d0 ;
    wire Iin_d_d26_d0 ;
-   wire Iin_d_d25_d0 ;
-   wire Iin_d_d10_d1 ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d31_d0 ;
+   wire Iin_d_d30_d0 ;
+   wire Iin_d_d26_d1 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d20_d0 ;
    wire Iin_d_d7_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d29_d1 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire Isb_in ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d17_d1 ;
 
 // --- instances
 TIELO_X1 Itielows0  (.y(Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v

@@ -43,47 +43,47 @@ module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
    input Isupply_vss ;
 
 // -- signals ---
-   output Iout_d_d29_d1 ;
-   output Iout_d_d20_d1 ;
-   wire Isupply_vss ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d5_d0 ;
-   output Iout_d_d26_d1 ;
-   output Iout_d_d25_d1 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d21_d1 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d3_d1 ;
-   output Iout_d_d12_d1 ;
-   wire Iin_d_d5_d1 ;
-   output Iout_d_d16_d1 ;
-   output Iout_d_d8_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Iin_d_d1_d0 ;
-   output Iout_d_d18_d1 ;
-   output Iout_d_d14_d1 ;
-   output Iout_d_d28_d1 ;
-   wire Iin_d_d4_d1 ;
-   wire Iin_d_d0_d1 ;
-   output Iout_d_d27_d1 ;
-   output Iout_d_d15_d1 ;
-   output Iout_d_d10_d1 ;
-   wire Isb_in ;
-   output Iout_d_d22_d1 ;
-   output Iout_d_d7_d0 ;
+   wire Iin_d_d2_d0 ;
    output Iout_d_d17_d1 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d19_d1 ;
-   output Iout_d_d7_d1 ;
-   output Iout_d_d24_d1 ;
+   wire Isb_in ;
+   output Iout_d_d29_d1 ;
+   output Iout_d_d13_d1 ;
    output Iout_d_d11_d1 ;
    wire Iin_d_d1_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d8_d1 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d25_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d5_d1 ;
+   wire Isupply_vss ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d19_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d7_d1 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d15_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d4_d0 ;
    wire Iin_d_d0_d0 ;
    output Iout_d_d30_d1 ;
-   wire Iin_d_d2_d0 ;
-   output Iout_d_d23_d1 ;
-   output Iout_d_d13_d1 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_d_d28_d1 ;
+   wire Iin_d_d6_d0 ;
+   output Iout_d_d20_d1 ;
+   output Iout_d_d27_d1 ;
+   output Iout_d_d12_d1 ;
+   output Iout_d_d16_d1 ;
+   wire Iin_d_d0_d1 ;
 
 // --- instances
 TIELO_X1 Itielows0  (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0arbiter__handshake/netlist/verilog.v

@@ -9,14 +9,14 @@ module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d
    input Iout_a ;
 
 // -- signals ---
-   output Iout_d_d0 ;
-   wire Iout_a ;
-   output Iin1_a ;
-   wire Iin1_d_d0 ;
-   wire Iin2_d_d0 ;
    wire _y2_arb ;
-   output Iin2_a ;
    wire _y1_arb ;
+   wire Iin2_d_d0 ;
+   output Iout_d_d0 ;
+   output Iin1_a ;
+   wire Iout_a ;
+   output Iin2_a ;
+   wire Iin1_d_d0 ;
 
 // --- instances
 A_2C_B_X1 Iack_cell1  (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_315_4/netlist/verilog.v

@@ -35,64 +35,64 @@ module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 ,
    input Iout_a ;
 
 // -- signals ---
-   output Iin10_a ;
-   wire Iin8_d_d0 ;
-   output Iin4_a ;
-   wire Itmp28_a ;
-   wire Itmp19_d_d0 ;
-   output Iin3_a ;
-   wire Itmp15_a ;
-   wire Itmp15_d_d0 ;
-   wire Iin13_d_d0 ;
-   wire Itmp27_d_d0 ;
-   wire Iin6_d_d0 ;
-   wire Itmp20_d_d0 ;
-   wire Iin4_d_d0 ;
-   wire Itmp28_d_d0 ;
+   output Iin9_a ;
    wire Iin5_d_d0 ;
-   wire Iin14_d_d0 ;
-   wire Itmp23_d_d0 ;
-   output Iin7_a ;
-   wire Iin1_d_d0 ;
-   wire Itmp24_a ;
-   wire Iin11_d_d0 ;
+   wire Itmp26_d_d0 ;
+   output Iin1_a ;
+   wire Itmp15_a ;
    wire Itmp17_a ;
    wire Itmp26_a ;
-   wire Itmp20_a ;
-   output Iin9_a ;
-   wire Iin2_d_d0 ;
-   wire Itmp27_a ;
-   output Iout_d_d0 ;
-   wire Itmp21_a ;
-   wire Iin10_d_d0 ;
-   wire Itmp19_a ;
+   wire Itmp27_d_d0 ;
+   wire Iin13_d_d0 ;
+   wire Iin11_d_d0 ;
+   output Iin4_a ;
    wire Itmp16_a ;
-   output Iin13_a ;
-   wire Iout_a ;
-   output Iin12_a ;
-   wire Iin12_d_d0 ;
-   wire Itmp16_d_d0 ;
-   wire Itmp26_d_d0 ;
-   wire Itmp21_d_d0 ;
-   wire Itmp23_a ;
+   output Iout_d_d0 ;
+   output Iin3_a ;
+   wire Iin1_d_d0 ;
+   wire Itmp28_a ;
+   output Iin5_a ;
    output Iin0_a ;
-   wire Itmp25_d_d0 ;
-   wire Iin7_d_d0 ;
+   wire Itmp15_d_d0 ;
+   wire Iin8_d_d0 ;
+   wire Itmp24_a ;
+   wire Iin12_d_d0 ;
+   wire Iin9_d_d0 ;
    output Iin2_a ;
-   output Iin1_a ;
-   output Iin8_a ;
-   wire Itmp17_d_d0 ;
-   output Iin11_a ;
+   wire Itmp25_d_d0 ;
+   wire Itmp25_a ;
+   wire Itmp19_a ;
    wire Itmp18_d_d0 ;
    wire Iin3_d_d0 ;
-   wire Itmp18_a ;
+   output Iin12_a ;
    wire Iin0_d_d0 ;
-   wire Itmp25_a ;
-   wire Itmp24_d_d0 ;
+   wire Iin2_d_d0 ;
+   wire Itmp27_a ;
+   wire Itmp23_d_d0 ;
+   output Iin8_a ;
+   wire Itmp28_d_d0 ;
+   wire Itmp21_a ;
+   output Iin7_a ;
+   wire Iout_a ;
+   wire Iin10_d_d0 ;
    output Iin14_a ;
-   wire Iin9_d_d0 ;
+   wire Itmp20_d_d0 ;
+   wire Itmp19_d_d0 ;
+   wire Iin4_d_d0 ;
+   wire Iin14_d_d0 ;
+   wire Itmp24_d_d0 ;
+   wire Itmp21_d_d0 ;
+   output Iin13_a ;
    output Iin6_a ;
-   output Iin5_a ;
+   wire Iin6_d_d0 ;
+   wire Itmp18_a ;
+   output Iin11_a ;
+   wire Itmp17_d_d0 ;
+   wire Itmp20_a ;
+   wire Itmp16_d_d0 ;
+   wire Itmp23_a ;
+   output Iin10_a ;
+   wire Iin7_d_d0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0  (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0arbtree_36_4/netlist/verilog.v

@@ -17,28 +17,28 @@ module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 ,
    input Iout_a ;
 
 // -- signals ---
-   wire Itmp6_d_d0 ;
-   wire Itmp9_d_d0 ;
-   output Iin0_a ;
-   output Iout_d_d0 ;
+   wire Iin3_d_d0 ;
+   output Iin3_a ;
+   output Iin2_a ;
    wire Iin1_d_d0 ;
+   output Iin1_a ;
+   wire Itmp9_d_d0 ;
+   wire Itmp10_a ;
    wire Itmp6_a ;
    wire Iin0_d_d0 ;
-   wire Itmp7_d_d0 ;
-   output Iin5_a ;
-   wire Iin4_d_d0 ;
-   wire Itmp10_a ;
+   wire Iout_a ;
    wire Itmp7_a ;
-   wire Iin2_d_d0 ;
-   output Iin1_a ;
+   wire Itmp7_d_d0 ;
    wire Itmp9_a ;
    wire Iin5_d_d0 ;
-   output Iin3_a ;
-   wire Iin3_d_d0 ;
+   wire Iin2_d_d0 ;
+   output Iin5_a ;
    wire Itmp10_d_d0 ;
    output Iin4_a ;
-   output Iin2_a ;
-   wire Iout_a ;
+   wire Iin4_d_d0 ;
+   output Iout_d_d0 ;
+   output Iin0_a ;
+   wire Itmp6_d_d0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0  (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp6_d_d0 ), .Iout_a (Itmp6_a ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4/netlist/verilog.v

@@ -110,156 +110,156 @@ module tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4(Iin_d0 , Iin_d1 , Iin_d2 ,
    input reset_B;
 
 // -- signals ---
-   wire I_inB28 ;
-   output Iout_d_d31_d1 ;
-   wire Iin_d19 ;
-   output Iout_d_d16_d1 ;
-   output Iout_d_d15_d1 ;
-   wire I_inB23 ;
-   wire Iin_d24 ;
-   wire Iin_d26 ;
-   output Iout_d_d1_d1 ;
-   output Iout_d_d28_d1 ;
-   output Iout_d_d27_d1 ;
-   wire Iin_d12 ;
-   wire Idly2_out ;
-   wire _reqX ;
-   wire Iin_d16 ;
-   wire I_inB31 ;
-   wire I_inB10 ;
-   wire Iin_d13 ;
-   wire Iin_d5 ;
-   output Iout_d_d12_d0 ;
-   wire Ien_buf_out0 ;
-   wire I_inB9 ;
-   output Iout_d_d24_d1 ;
-   wire Iin_d7 ;
-   output Iout_d_d21_d1 ;
-   wire _reset_BX ;
-   wire I_inB15 ;
-   output Iout_d_d9_d1 ;
-   wire Iin_d0 ;
-   wire I_inB6 ;
-   output Iout_d_d16_d0 ;
-   wire I_inB11 ;
-   wire Iin_d20 ;
-   wire _en ;
-   wire Iin_d29 ;
-   wire I_inB12 ;
-   output Iout_d_d18_d0 ;
-   output Iout_d_d19_d1 ;
-   output Iout_d_d15_d0 ;
-   wire I_inB13 ;
-   wire Iin_d27 ;
-   output Iout_d_d0_d0 ;
-   wire I_reset_BXX0 ;
-   wire Iin_d3 ;
-   wire Iin_d21 ;
-   output Iout_d_d14_d0 ;
-   output Iout_d_d23_d1 ;
-   wire _req_slowfall ;
-   output Iin_a ;
-   wire I_inB18 ;
-   output Iout_d_d3_d0 ;
-   wire Idly_cfg20 ;
-   wire I_inB7 ;
-   wire Iin_d22 ;
-   wire I_inB25 ;
-   output Iout_d_d30_d0 ;
-   output Iout_d_d8_d0 ;
-   output Iout_d_d28_d0 ;
-   output Iout_d_d25_d1 ;
-   wire I_inB1 ;
-   output Iout_d_d5_d1 ;
-   wire reset_B;
-   wire I_reqXX0 ;
-   output Iout_d_d31_d0 ;
-   wire Idly_cfg0 ;
-   wire Iin_d30 ;
-   output Iout_d_d21_d0 ;
-   wire I_inB4 ;
-   wire Iin_d8 ;
-   wire I_inB17 ;
-   wire I_inB26 ;
-   output Iout_d_d9_d0 ;
-   wire Iout_a ;
-   wire Iin_d15 ;
-   output Iout_d_d7_d1 ;
-   output Iout_d_d8_d1 ;
-   wire Idly_cfg21 ;
-   wire Iin_d4 ;
-   wire Iin_d25 ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d7_d0 ;
-   wire _req ;
-   wire I_inB8 ;
-   wire I_inB14 ;
-   output Iout_d_d20_d0 ;
    wire Iin_r ;
-   output Iout_d_d6_d1 ;
+   output Iout_d_d4_d1 ;
+   wire reset_B;
+   wire Iin_d23 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d22_d1 ;
+   wire Iin_d4 ;
+   wire Iin_d31 ;
+   wire I_inB18 ;
+   output Iout_d_d9_d0 ;
+   wire Iin_d1 ;
+   wire Iin_d11 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d22_d0 ;
+   wire Iin_d7 ;
+   wire Iin_d17 ;
+   wire Iin_d22 ;
+   output Iout_d_d0_d0 ;
+   wire Iin_d5 ;
+   wire I_inB29 ;
+   output Iin_a ;
+   wire Iin_d9 ;
+   wire Iin_d30 ;
+   wire I_inB14 ;
+   wire Iin_d21 ;
+   wire I_inB27 ;
+   wire Ien_buf_out0 ;
+   wire I_inB4 ;
+   wire Iin_d28 ;
+   output Iout_d_d20_d0 ;
+   output Iout_d_d21_d1 ;
+   wire Iin_d25 ;
+   wire I_inB1 ;
+   output Iout_d_d23_d0 ;
+   output Iout_d_d29_d0 ;
+   output Iout_d_d30_d0 ;
+   output Iout_d_d13_d1 ;
+   wire Iin_d13 ;
+   wire I_inB16 ;
+   wire I_inB24 ;
+   wire Iin_d26 ;
+   output Iout_d_d5_d0 ;
+   wire I_reqXX0 ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d28_d0 ;
+   wire I_inB3 ;
+   output Iout_d_d18_d0 ;
+   output Iout_d_d10_d0 ;
+   output Iout_d_d25_d0 ;
+   wire Iin_d16 ;
+   output Iout_d_d2_d1 ;
+   wire _out_a_B ;
+   wire Idly_cfg20 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Idly2_out ;
+   wire Idly_cfg21 ;
    wire I_inB22 ;
-   wire I_inB2 ;
+   wire Iin_d24 ;
+   output Iout_d_d12_d0 ;
+   wire I_inB11 ;
+   wire I_inB21 ;
+   wire I_inB28 ;
+   output Iout_d_d27_d1 ;
+   wire _req ;
+   wire Iin_d3 ;
+   output Iout_d_d15_d0 ;
+   wire I_reset_BXX0 ;
+   wire Iin_d0 ;
+   wire Iin_d29 ;
+   output Iout_d_d11_d1 ;
+   wire _req_slowfall ;
+   wire I_inB9 ;
+   wire I_inB20 ;
+   wire I_inB7 ;
+   wire I_inB8 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d1_d0 ;
    output Iout_d_d14_d1 ;
    wire Idly_cfg1 ;
-   wire I_inB16 ;
-   wire I_inB3 ;
-   output Iout_d_d26_d0 ;
-   output Iout_d_d5_d0 ;
-   output Iout_d_d29_d1 ;
-   wire I_inB19 ;
-   output Iout_d_d13_d0 ;
-   wire Iin_d17 ;
-   wire I_inB30 ;
-   output Iout_d_d18_d1 ;
-   output Iout_d_d27_d0 ;
-   wire I_inB0 ;
-   wire Iin_d1 ;
-   output Iout_d_d4_d0 ;
-   output Iout_d_d23_d0 ;
-   output Iout_d_d4_d1 ;
-   output Iout_d_d11_d1 ;
-   wire Iin_d11 ;
-   wire I_inB24 ;
-   output Iout_d_d1_d0 ;
-   output Iout_d_d30_d1 ;
-   output Iout_d_d12_d1 ;
-   output Iout_d_d19_d0 ;
-   wire _out_a_B ;
-   wire Iin_d18 ;
-   wire Iin_d31 ;
-   output Iout_d_d11_d0 ;
-   output Iout_d_d24_d0 ;
-   output Iout_d_d29_d0 ;
-   output Iout_d_d22_d1 ;
-   wire Iin_d9 ;
-   wire Iout_v ;
-   wire Iin_d28 ;
-   output Iout_d_d22_d0 ;
-   output Iout_d_d17_d1 ;
-   output Iout_d_d13_d1 ;
-   output Iout_d_d25_d0 ;
-   output Iout_d_d2_d0 ;
-   wire Iin_d2 ;
-   wire Iin_d14 ;
-   wire I_inB20 ;
-   wire Iin_d23 ;
-   wire If_buf_func31_c2 ;
-   output Iout_d_d10_d0 ;
    output Iout_d_d0_d1 ;
-   output Iout_d_d2_d1 ;
-   wire Idly_cfg3 ;
-   wire Iin_d6 ;
-   wire Idly_cfg2 ;
-   output Iout_d_d3_d1 ;
-   wire I_inB27 ;
-   output Iout_d_d17_d0 ;
-   wire Iin_d10 ;
-   wire I_inB29 ;
+   wire Iin_d15 ;
+   wire I_inB26 ;
+   output Iout_d_d15_d1 ;
+   wire I_inB25 ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d18 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d14_d0 ;
    output Iout_d_d26_d1 ;
+   output Iout_d_d12_d1 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d23_d1 ;
+   wire I_inB0 ;
+   output Iout_d_d16_d1 ;
+   wire I_inB30 ;
+   wire _reset_BX ;
+   wire Idly_cfg0 ;
+   wire Idly_cfg3 ;
+   wire I_inB23 ;
+   output Iout_d_d26_d0 ;
+   wire I_inB12 ;
+   wire Iin_d19 ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d18_d1 ;
+   wire I_inB6 ;
+   output Iout_d_d5_d1 ;
+   wire I_inB31 ;
+   output Iout_d_d31_d0 ;
+   output Iout_d_d1_d1 ;
    output Iout_d_d20_d1 ;
+   wire Iin_d10 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d7_d1 ;
+   wire I_inB17 ;
    wire I_inB5 ;
-   wire I_inB21 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d17_d0 ;
+   output Iout_d_d17_d1 ;
+   wire _reqX ;
+   wire Iin_d6 ;
+   wire I_inB10 ;
+   wire I_inB15 ;
+   wire Iin_d14 ;
+   wire _en ;
+   output Iout_d_d19_d0 ;
+   wire Iin_d2 ;
+   output Iout_d_d31_d1 ;
+   output Iout_d_d21_d0 ;
+   output Iout_d_d24_d1 ;
+   wire Iout_v ;
+   wire I_inB2 ;
+   wire Iin_d8 ;
    output Iout_d_d10_d1 ;
+   output Iout_d_d30_d1 ;
+   wire Idly_cfg2 ;
+   wire Iout_a ;
+   wire Iin_d20 ;
+   wire Iin_d27 ;
+   wire Iin_d12 ;
+   output Iout_d_d16_d0 ;
+   output Iout_d_d27_d0 ;
+   wire If_buf_func31_c2 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d28_d1 ;
+   output Iout_d_d25_d1 ;
+   wire I_inB19 ;
+   wire I_inB13 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_313_4/netlist/verilog.v

@@ -60,70 +60,70 @@ module tmpl_0_0dataflow__neuro_0_0buffer_313_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
    input reset_B;
 
 // -- signals ---
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d4_d0 ;
-   wire Iin_d_d10_d1 ;
-   wire _out_a_B ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d5_d0 ;
-   output Iout_d_d2_d0 ;
-   output Iout_d_d1_d0 ;
-   output Iout_d_d4_d1 ;
-   wire Iin_d_d7_d1 ;
-   wire I_reset_BXX0 ;
    output Iout_d_d8_d0 ;
-   output Iout_d_d12_d1 ;
-   output Iout_d_d10_d1 ;
-   wire Iin_d_d8_d0 ;
-   wire Iin_d_d9_d1 ;
-   output Iout_d_d6_d1 ;
-   wire Iin_d_d6_d0 ;
-   output Iout_d_d11_d0 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d7_d0 ;
+   wire Iin_d_d11_d1 ;
    wire Iin_d_d11_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d5_d1 ;
+   wire _out_a_B ;
+   output Iout_d_d7_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d8_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d11_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d2_d1 ;
+   wire Ien_buf_out0 ;
+   wire Iin_d_d1_d0 ;
    wire Iin_d_d6_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire I_reset_BXX0 ;
+   wire _reset_BX ;
+   wire Iin_d_d3_d0 ;
+   output Iout_d_d5_d1 ;
+   wire Iin_d_d10_d0 ;
+   output Iout_d_d3_d0 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d11_d0 ;
    wire Iin_d_d4_d0 ;
    output Iout_d_d10_d0 ;
-   output Iout_d_d11_d1 ;
-   wire _en ;
-   output Iout_d_d9_d0 ;
-   output Iout_d_d0_d1 ;
-   output Iout_d_d3_d0 ;
+   wire Iin_d_d0_d1 ;
    output Iout_d_d0_d0 ;
-   wire Iin_d_d5_d0 ;
-   wire Ien_buf_out0 ;
+   output Iout_d_d7_d1 ;
+   wire _en ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d7_d1 ;
    wire Iin_d_d9_d0 ;
    wire _in_v ;
-   output Iin_a ;
-   output Iin_v ;
-   output Iout_d_d3_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d2_d0 ;
-   wire _reset_BX ;
-   output Iout_d_d9_d1 ;
-   wire Iin_d_d4_d1 ;
-   wire Iout_a ;
-   output Iout_d_d8_d1 ;
-   output Iout_d_d12_d0 ;
-   wire Iin_d_d8_d1 ;
-   wire Iout_v ;
-   wire I_out_a_BX0 ;
-   output Iout_d_d7_d1 ;
-   wire reset_B;
+   output Iout_d_d12_d1 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d4_d1 ;
    wire Iin_d_d12_d0 ;
-   wire Iin_d_d12_d1 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout_d_d7_d0 ;
-   output Iout_d_d5_d1 ;
-   wire Iin_d_d3_d1 ;
    output Iout_d_d2_d1 ;
-   output Iout_d_d1_d1 ;
-   wire Iin_d_d5_d1 ;
+   output Iout_d_d0_d1 ;
+   wire reset_B;
    wire Iin_d_d0_d0 ;
+   output Iin_a ;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d3_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iout_a ;
+   output Iout_d_d10_d1 ;
+   output Iin_v ;
+   output Iout_d_d6_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d8_d1 ;
+   output Iout_d_d1_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire Iout_v ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d12_d0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_329_4/netlist/verilog.v

@@ -1,4 +1,4 @@
-module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
+module tmpl_0_0dataflow__neuro_0_0buffer_329_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
    input vdd;
    input vss;
    input Iin_d_d0_d0 ;
@@ -59,10 +59,6 @@ module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
    input Iin_d_d27_d1 ;
    input Iin_d_d28_d0 ;
    input Iin_d_d28_d1 ;
-   input Iin_d_d29_d0 ;
-   input Iin_d_d29_d1 ;
-   
-   
    
    
    
@@ -128,148 +124,144 @@ module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
    input reset_B;
 
 // -- signals ---
-   wire Iin_d_d13_d0 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d29_d0 ;
-   wire Ien_buf_out0 ;
-   output Iout_d_d26_d0 ;
-   wire Iin_d_d29_d1 ;
    output Iout_d_d15_d1 ;
-   wire Iin_d_d27_d1 ;
-   output Iout_d_d18_d0 ;
-   wire Iin_d_d9_d0 ;
-   output Iout_d_d5_d0 ;
-   wire Iin_d_d22_d0 ;
-   wire Iin_d_d26_d0 ;
-   wire Iin_d_d6_d1 ;
-   output Iout_d_d21_d1 ;
-   output Iout_d_d17_d0 ;
-   wire Iin_d_d14_d0 ;
-   output Iout_d_d16_d0 ;
-   output Iout_d_d19_d1 ;
-   output Iout_d_d20_d1 ;
-   wire Iin_d_d2_d0 ;
-   output Iout_d_d8_d1 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d4_d0 ;
    wire Iin_d_d25_d0 ;
-   output Iout_d_d14_d1 ;
-   wire Iin_d_d24_d0 ;
-   output Iout_d_d18_d1 ;
-   output Iout_d_d26_d1 ;
-   output Iout_d_d15_d0 ;
-   output Iout_d_d9_d0 ;
-   output Iout_d_d13_d1 ;
-   output Iout_d_d3_d0 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d23_d1 ;
-   output Iout_d_d22_d0 ;
-   wire Iin_d_d28_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d12_d1 ;
-   wire _in_v ;
-   wire Iin_d_d26_d1 ;
-   wire _reset_BX ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d19_d1 ;
-   output Iout_d_d0_d0 ;
-   wire Iin_d_d17_d1 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d24_d1 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d11_d0 ;
-   output Iout_d_d27_d1 ;
-   output Iout_d_d4_d0 ;
-   wire Iin_d_d9_d1 ;
-   output Iout_d_d17_d1 ;
-   wire Iout_a ;
-   output Iout_d_d13_d0 ;
-   output Iout_d_d25_d0 ;
-   wire Iin_d_d5_d0 ;
-   wire Iin_d_d1_d1 ;
-   output Iout_d_d2_d1 ;
-   output Iout_d_d7_d0 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d12_d0 ;
-   wire I_reset_BXX0 ;
    wire Iin_d_d8_d1 ;
-   wire Iin_d_d13_d1 ;
-   wire Iin_d_d3_d0 ;
-   wire Iin_d_d11_d0 ;
-   output Iout_d_d10_d1 ;
-   output Iout_d_d8_d0 ;
-   wire Iin_d_d17_d0 ;
-   output Iout_d_d6_d1 ;
-   output Iout_d_d22_d1 ;
-   wire Iout_v ;
-   wire Iin_d_d5_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout_d_d28_d1 ;
-   output Iout_d_d23_d0 ;
-   wire reset_B;
-   output Iout_d_d2_d0 ;
-   output Iout_d_d24_d0 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d23_d0 ;
-   output Iout_d_d0_d1 ;
-   output Iout_d_d3_d1 ;
-   wire Iin_d_d20_d1 ;
-   output Iout_d_d4_d1 ;
-   output Iin_a ;
-   output Iin_v ;
-   output Iout_d_d23_d1 ;
-   output Iout_d_d24_d1 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d15_d0 ;
-   wire Iin_d_d15_d1 ;
-   output Iout_d_d12_d0 ;
-   output Iout_d_d19_d0 ;
-   wire Iin_d_d19_d0 ;
-   wire _out_a_B ;
-   output Iout_d_d12_d1 ;
-   output Iout_d_d27_d0 ;
-   wire Iin_d_d10_d1 ;
+   output Iout_d_d17_d0 ;
+   output Iout_d_d0_d0 ;
    output Iout_d_d6_d0 ;
-   output Iout_d_d10_d0 ;
-   wire Iin_d_d4_d1 ;
-   wire Iin_d_d7_d0 ;
-   output Iout_d_d1_d1 ;
-   output Iout_d_d14_d0 ;
-   wire Iin_d_d8_d0 ;
-   wire Iin_d_d14_d1 ;
-   output Iout_d_d20_d0 ;
-   wire I_out_a_BX0 ;
-   wire Iin_d_d16_d0 ;
-   output Iout_d_d1_d0 ;
-   wire Iin_d_d25_d1 ;
-   wire Iin_d_d27_d0 ;
-   output Iout_d_d16_d1 ;
-   output Iout_d_d29_d0 ;
-   wire Iin_d_d0_d0 ;
-   output Iout_d_d11_d1 ;
+   wire Iin_d_d5_d0 ;
+   output Iout_d_d26_d0 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d6_d1 ;
+   output Iin_a ;
+   output Iout_d_d13_d1 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d1_d0 ;
    output Iout_d_d7_d1 ;
-   output Iout_d_d21_d0 ;
-   wire Iin_d_d21_d0 ;
-   wire Iin_d_d21_d1 ;
-   output Iout_d_d5_d1 ;
-   wire Iin_d_d11_d1 ;
-   output Iout_d_d29_d1 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d24_d1 ;
    wire Iin_d_d16_d1 ;
-   wire Iin_d_d18_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d6_d0 ;
    wire _en ;
-   output Iout_d_d25_d1 ;
+   output Iout_d_d16_d0 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d1_d0 ;
+   output Iout_d_d5_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire I_reset_BXX0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire _in_v ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d4_d1 ;
+   output Iout_d_d28_d1 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d23_d1 ;
+   wire Iin_d_d26_d0 ;
+   output Iout_d_d25_d0 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d11_d1 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d12_d0 ;
+   wire reset_B;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d8_d0 ;
+   output Iout_d_d21_d0 ;
+   output Iout_d_d19_d0 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d8_d0 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d2_d0 ;
+   output Iin_v ;
    output Iout_d_d28_d0 ;
+   wire _out_a_B ;
+   output Iout_d_d27_d0 ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d22_d0 ;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d15_d0 ;
+   output Iout_d_d18_d0 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d2_d1 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d3_d1 ;
+   output Iout_d_d15_d0 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d23_d0 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d4_d1 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d16_d1 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d15_d1 ;
+   output Iout_d_d27_d1 ;
+   wire Ien_buf_out0 ;
+   wire _reset_BX ;
+   wire Iout_v ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d13_d1 ;
+   output Iout_d_d14_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire Iout_a ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d10_d0 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d1_d1 ;
    wire Iin_d_d22_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d0_d0 ;
+   output Iout_d_d25_d1 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d20_d0 ;
 
 // --- instances
-tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
 A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
 INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0vtree_330_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_329_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
 A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
 BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
@@ -300,7 +292,6 @@ A_2C1N_RB_X4 It_buf_func25  (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a
 A_2C1N_RB_X4 It_buf_func26  (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func27  (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func28  (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
-A_2C1N_RB_X4 It_buf_func29  (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
@@ -330,5 +321,4 @@ A_2C1N_RB_X4 If_buf_func25  (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a
 A_2C1N_RB_X4 If_buf_func26  (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 If_buf_func27  (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 If_buf_func28  (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
-A_2C1N_RB_X4 If_buf_func29  (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
 endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_331_4/netlist/verilog.v

@@ -132,142 +132,142 @@ module tmpl_0_0dataflow__neuro_0_0buffer_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
    input reset_B;
 
 // -- signals ---
-   wire Iout_v ;
-   wire Iin_d_d8_d1 ;
-   wire Iin_d_d29_d1 ;
-   output Iout_d_d20_d0 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d25_d0 ;
-   output Iout_d_d6_d1 ;
-   output Iout_d_d27_d0 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d27_d0 ;
-   output Iout_d_d5_d0 ;
-   wire Iin_d_d12_d0 ;
-   wire Iin_d_d27_d1 ;
    wire Iin_d_d16_d1 ;
-   wire Ien_buf_out0 ;
-   output Iout_d_d18_d1 ;
-   wire Iin_d_d3_d0 ;
-   wire Iin_d_d22_d0 ;
-   wire Iin_d_d30_d0 ;
-   output Iout_d_d12_d1 ;
-   output Iout_d_d26_d0 ;
-   output Iout_d_d12_d0 ;
-   wire Iin_d_d7_d0 ;
-   output Iout_d_d15_d0 ;
-   wire Iin_d_d4_d0 ;
-   output Iout_d_d1_d1 ;
-   wire Iin_d_d4_d1 ;
-   wire Iin_d_d24_d0 ;
-   output Iout_d_d26_d1 ;
-   output Iout_d_d8_d1 ;
-   output Iout_d_d18_d0 ;
-   wire Iin_d_d12_d1 ;
-   wire Iin_d_d9_d1 ;
    output Iout_d_d29_d0 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d13_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout_d_d4_d1 ;
-   output Iout_d_d24_d1 ;
-   output Iout_d_d17_d1 ;
-   output Iout_d_d0_d0 ;
-   wire Iin_d_d17_d1 ;
-   wire Iin_d_d20_d1 ;
-   output Iout_d_d13_d1 ;
-   output Iout_d_d11_d0 ;
-   wire Iin_d_d15_d1 ;
-   output Iout_d_d7_d1 ;
-   output Iin_v ;
-   wire Iin_d_d0_d0 ;
-   output Iout_d_d19_d1 ;
-   output Iout_d_d28_d0 ;
-   output Iout_d_d15_d1 ;
-   wire Iin_d_d19_d1 ;
-   wire Iin_d_d28_d1 ;
-   output Iout_d_d14_d0 ;
-   wire Iin_d_d2_d0 ;
-   wire Iin_d_d20_d0 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d27_d1 ;
-   wire Iin_d_d13_d0 ;
-   output Iout_d_d22_d1 ;
-   output Iout_d_d17_d0 ;
-   wire Iin_d_d19_d0 ;
-   output Iout_d_d8_d0 ;
-   output Iout_d_d22_d0 ;
-   wire Iin_d_d8_d0 ;
-   output Iout_d_d4_d0 ;
-   output Iout_d_d16_d0 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d16_d0 ;
-   wire Iin_d_d25_d1 ;
-   output Iout_d_d10_d1 ;
-   output Iout_d_d20_d1 ;
-   output Iout_d_d6_d0 ;
-   wire Iin_d_d23_d1 ;
-   output Iout_d_d9_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire Iin_d_d11_d0 ;
-   output Iout_d_d23_d1 ;
-   output Iout_d_d13_d0 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d29_d0 ;
-   output Iout_d_d19_d0 ;
-   output Iout_d_d16_d1 ;
-   output Iout_d_d29_d1 ;
-   output Iout_d_d7_d0 ;
-   output Iout_d_d30_d0 ;
-   output Iout_d_d2_d0 ;
-   wire _in_v ;
-   wire Iin_d_d26_d1 ;
-   output Iout_d_d3_d1 ;
-   output Iout_d_d23_d0 ;
-   output Iin_a ;
-   wire Iin_d_d14_d1 ;
    wire Iin_d_d22_d1 ;
-   wire Iin_d_d23_d0 ;
-   output Iout_d_d10_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d26_d0 ;
-   output Iout_d_d3_d0 ;
-   output Iout_d_d21_d0 ;
-   wire _en ;
-   wire Iin_d_d17_d0 ;
-   output Iout_d_d24_d0 ;
-   wire _out_a_B ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d28_d0 ;
-   output Iout_d_d11_d1 ;
-   wire Iin_d_d5_d0 ;
-   wire Iin_d_d30_d1 ;
-   wire Iin_d_d6_d0 ;
-   output Iout_d_d14_d1 ;
-   output Iout_d_d5_d1 ;
-   wire I_reset_BXX0 ;
-   output Iout_d_d2_d1 ;
-   output Iout_d_d25_d0 ;
-   wire Iin_d_d14_d0 ;
-   output Iout_d_d30_d1 ;
-   wire Iin_d_d21_d0 ;
-   wire reset_B;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Ien_buf_out0 ;
    wire Iin_d_d15_d0 ;
-   wire I_out_a_BX0 ;
-   output Iout_d_d0_d1 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d19_d0 ;
+   output Iout_d_d30_d0 ;
+   wire Iin_d_d13_d0 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d0_d1 ;
+   output Iout_d_d27_d1 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d25_d0 ;
+   output Iout_d_d21_d0 ;
+   wire Iin_d_d8_d0 ;
+   output Iout_d_d7_d1 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d26_d0 ;
+   wire Iin_d_d30_d0 ;
+   output Iout_d_d8_d1 ;
+   output Iout_d_d28_d1 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d11_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d18_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d21_d1 ;
+   output Iout_d_d14_d0 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d25_d0 ;
+   wire Iin_d_d29_d1 ;
+   wire Iin_d_d30_d1 ;
+   output Iout_d_d22_d0 ;
+   output Iout_d_d30_d1 ;
+   wire Iout_v ;
+   wire Iout_a ;
+   wire Iin_d_d5_d1 ;
+   wire _in_v ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d9_d0 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d13_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d7_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d9_d0 ;
+   output Iout_d_d16_d1 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d28_d0 ;
+   wire _out_a_B ;
+   wire _reset_BX ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d28_d0 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d15_d1 ;
    output Iout_d_d21_d1 ;
    wire Iin_d_d10_d1 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d24_d0 ;
+   output Iin_a ;
+   output Iout_d_d18_d1 ;
+   wire Iin_d_d26_d0 ;
+   output Iout_d_d15_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d17_d0 ;
+   wire reset_B;
+   output Iout_d_d27_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d23_d1 ;
+   output Iout_d_d26_d1 ;
+   wire Iin_d_d27_d1 ;
+   output Iout_d_d2_d1 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d17_d0 ;
+   output Iout_d_d23_d0 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d13_d1 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire I_reset_BXX0 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d13_d0 ;
+   wire _en ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d16_d0 ;
    output Iout_d_d25_d1 ;
-   output Iout_d_d28_d1 ;
-   output Iout_d_d1_d0 ;
-   wire Iout_a ;
-   wire Iin_d_d18_d0 ;
-   wire _reset_BX ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d21_d1 ;
+   output Iin_v ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d10_d0 ;
+   wire Iin_d_d20_d0 ;
+   output Iout_d_d4_d1 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d16_d0 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d28_d1 ;
+   output Iout_d_d0_d1 ;
+   output Iout_d_d9_d1 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_332_4/netlist/verilog.v

@@ -136,146 +136,146 @@ module tmpl_0_0dataflow__neuro_0_0buffer_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
    input reset_B;
 
 // -- signals ---
-   wire Iin_d_d21_d1 ;
-   output Iout_d_d25_d1 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d26_d0 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d2_d0 ;
-   wire Iin_d_d13_d0 ;
-   wire Iin_d_d0_d0 ;
-   wire Iin_d_d26_d1 ;
-   output Iout_d_d10_d1 ;
-   output Iout_d_d8_d0 ;
-   output Iout_d_d8_d1 ;
-   output Iout_d_d26_d1 ;
-   wire Iin_d_d5_d1 ;
-   output Iout_d_d1_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d10_d0 ;
+   output Iout_d_d16_d1 ;
    output Iout_d_d28_d0 ;
-   wire Iin_d_d12_d1 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d19_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d20_d1 ;
+   wire _in_v ;
+   output Iout_d_d10_d0 ;
    output Iout_d_d11_d0 ;
+   output Iout_d_d25_d0 ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d14_d0 ;
+   wire Iin_d_d13_d0 ;
+   output Iout_d_d7_d1 ;
+   wire Iin_d_d28_d0 ;
+   wire Ien_buf_out0 ;
+   wire reset_B;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d29_d1 ;
+   output Iout_d_d1_d0 ;
    wire Iin_d_d13_d1 ;
    wire Iin_d_d14_d1 ;
-   wire Iin_d_d18_d1 ;
-   output Iout_d_d29_d1 ;
-   wire Iin_d_d22_d1 ;
-   wire Iin_d_d7_d0 ;
-   wire Iin_d_d12_d0 ;
-   output Iout_d_d16_d0 ;
-   wire Iin_d_d20_d1 ;
-   output Iout_d_d1_d0 ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d20_d0 ;
-   wire _reset_BX ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d21_d0 ;
-   wire Iin_d_d5_d0 ;
-   output Iout_d_d16_d1 ;
-   output Iout_d_d17_d0 ;
-   wire Iin_d_d20_d0 ;
-   output Iout_d_d6_d1 ;
-   output Iout_d_d14_d1 ;
-   wire Ien_buf_out0 ;
-   output Iout_d_d13_d1 ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d25_d1 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d28_d1 ;
-   wire Iin_d_d30_d1 ;
-   output Iout_d_d31_d1 ;
-   output Iout_d_d3_d0 ;
-   wire I_out_a_BX0 ;
-   wire Iin_d_d18_d0 ;
-   output Iout_d_d3_d1 ;
-   output Iout_d_d15_d0 ;
-   output Iout_d_d21_d0 ;
-   wire Iin_d_d25_d0 ;
-   wire Iin_d_d30_d0 ;
-   output Iout_d_d7_d1 ;
-   output Iout_d_d28_d1 ;
-   wire Iin_d_d19_d0 ;
-   wire Iin_d_d23_d0 ;
-   output Iout_d_d4_d1 ;
-   output Iout_d_d21_d1 ;
-   output Iout_d_d13_d0 ;
-   output Iout_d_d0_d1 ;
-   wire Iin_d_d24_d0 ;
-   output Iout_d_d23_d1 ;
-   output Iout_d_d2_d0 ;
-   wire _in_v ;
-   wire Iin_d_d14_d0 ;
-   output Iout_d_d15_d1 ;
-   output Iout_d_d22_d1 ;
-   output Iout_d_d11_d1 ;
-   wire Iin_d_d27_d0 ;
    wire Iin_d_d31_d0 ;
-   output Iout_d_d27_d1 ;
-   output Iout_d_d0_d0 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d8_d0 ;
-   output Iin_v ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d15_d1 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d11_d1 ;
    output Iout_d_d18_d1 ;
-   output Iout_d_d30_d0 ;
-   wire Iin_d_d29_d0 ;
-   wire Iin_d_d16_d0 ;
-   output Iout_d_d5_d0 ;
-   wire Iin_d_d4_d1 ;
-   output Iout_d_d9_d0 ;
-   output Iout_d_d27_d0 ;
-   output Iout_d_d24_d0 ;
-   wire Iin_d_d19_d1 ;
-   output Iout_d_d23_d0 ;
-   output Iout_d_d2_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout_d_d5_d1 ;
-   output Iout_d_d30_d1 ;
-   output Iout_d_d22_d0 ;
-   output Iout_d_d17_d1 ;
-   output Iout_d_d4_d0 ;
-   output Iout_d_d29_d0 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d31_d0 ;
-   wire I_reset_BXX0 ;
-   wire Iin_d_d4_d0 ;
-   output Iout_d_d26_d0 ;
-   wire Iin_d_d29_d1 ;
-   output Iout_d_d18_d0 ;
-   output Iout_d_d25_d0 ;
-   wire Iin_d_d0_d1 ;
+   wire Iin_d_d9_d0 ;
    wire Iin_d_d10_d1 ;
-   wire Iin_d_d31_d1 ;
-   output Iout_d_d14_d0 ;
-   output Iout_d_d19_d0 ;
-   wire Iin_d_d6_d0 ;
-   wire _en ;
-   wire Iin_d_d17_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d16_d0 ;
    wire Iin_d_d23_d1 ;
+   output Iout_d_d13_d1 ;
+   output Iout_d_d2_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire _en ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d7_d0 ;
    wire Iin_d_d24_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d27_d1 ;
-   wire Iin_d_d17_d0 ;
-   wire Iout_a ;
-   output Iout_d_d12_d1 ;
-   wire _out_a_B ;
-   wire Iout_v ;
-   wire Iin_d_d16_d1 ;
-   output Iin_a ;
-   output Iout_d_d19_d1 ;
-   output Iout_d_d7_d0 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d3_d0 ;
+   output Iout_d_d27_d0 ;
    wire Iin_d_d15_d0 ;
-   wire Iin_d_d22_d0 ;
-   wire reset_B;
-   output Iout_d_d10_d0 ;
-   output Iout_d_d24_d1 ;
+   output Iout_d_d2_d1 ;
+   output Iout_d_d28_d1 ;
+   wire _reset_BX ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d25_d1 ;
+   output Iout_d_d4_d1 ;
+   output Iin_a ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d17_d1 ;
+   output Iout_d_d30_d1 ;
+   wire Iin_d_d1_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d31_d0 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d_d25_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d27_d1 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d27_d1 ;
+   wire Iin_d_d27_d0 ;
+   output Iout_d_d0_d0 ;
+   wire I_reset_BXX0 ;
+   output Iout_d_d23_d0 ;
+   wire Iin_d_d8_d0 ;
    wire Iin_d_d8_d1 ;
-   output Iout_d_d20_d1 ;
-   wire Iin_d_d9_d1 ;
+   wire Iin_d_d29_d0 ;
+   wire Iout_v ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d26_d0 ;
+   output Iout_d_d31_d1 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d29_d0 ;
+   wire Iin_d_d19_d0 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d23_d0 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d23_d1 ;
+   wire Iin_d_d25_d0 ;
+   output Iout_d_d29_d1 ;
+   output Iout_d_d22_d1 ;
+   wire Iin_d_d31_d1 ;
+   output Iout_d_d18_d0 ;
+   output Iout_d_d26_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d21_d0 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d9_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d30_d0 ;
+   output Iout_d_d22_d0 ;
+   wire Iin_d_d18_d1 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d13_d0 ;
+   output Iin_v ;
+   wire Iout_a ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d28_d1 ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d_d30_d0 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d21_d0 ;
+   wire _out_a_B ;
+   wire Iin_d_d12_d0 ;
+   output Iout_d_d5_d1 ;
    output Iout_d_d12_d0 ;
+   wire Iin_d_d21_d1 ;
+   output Iout_d_d14_d1 ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d17_d0 ;
+   wire I_out_a_BX0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d24_d0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0buffer_37_4/netlist/verilog.v

@@ -36,46 +36,46 @@ module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
    input reset_B;
 
 // -- signals ---
-   output Iout_d_d5_d0 ;
-   wire I_reset_BXX0 ;
-   output Iin_v ;
-   wire Iin_d_d6_d1 ;
+   output Iout_d_d5_d1 ;
    wire Iin_d_d4_d1 ;
-   wire _in_v ;
+   output Iin_v ;
    output Iout_d_d3_d1 ;
-   output Iout_d_d3_d0 ;
-   output Iout_d_d0_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Iin_d_d1_d1 ;
+   wire _out_a_B ;
+   wire Iout_a ;
+   output Iout_d_d2_d0 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d1_d0 ;
    wire reset_B;
    wire Ien_buf_out0 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire _en ;
-   output Iout_d_d4_d1 ;
-   wire Iin_d_d2_d1 ;
-   output Iout_d_d5_d1 ;
-   wire Iin_d_d0_d1 ;
-   wire _out_a_B ;
-   wire _reset_BX ;
-   output Iout_d_d0_d0 ;
    wire Iin_d_d5_d0 ;
-   wire I_out_a_BX0 ;
-   output Iin_a ;
-   output Iout_d_d1_d0 ;
-   output Iout_d_d2_d0 ;
    output Iout_d_d1_d1 ;
-   wire Iout_v ;
-   wire Iin_d_d0_d0 ;
-   wire Iin_d_d3_d1 ;
-   output Iout_d_d4_d0 ;
-   wire Iin_d_d3_d0 ;
-   wire Iin_d_d2_d0 ;
    output Iout_d_d6_d1 ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d2_d1 ;
    wire Iin_d_d1_d0 ;
-   wire Iout_a ;
+   wire _reset_BX ;
+   wire Iin_d_d3_d1 ;
+   wire I_reset_BXX0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d3_d0 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d_d6_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d0_d0 ;
+   output Iout_d_d5_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire I_out_a_BX0 ;
+   output Iout_d_d4_d1 ;
+   wire _in_v ;
+   wire Iin_d_d2_d1 ;
+   wire _en ;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d2_d1 ;
+   wire Iin_d_d2_d0 ;
+   output Iin_a ;
+   wire Iin_d_d1_d1 ;
+   wire Iout_v ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_313_4/netlist/verilog.v

@@ -17,28 +17,28 @@ module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Itmp21 ;
-   wire Iin7 ;
-   wire Iin1 ;
-   wire Iin12 ;
-   wire Iin11 ;
-   wire Itmp17 ;
-   wire Iin9 ;
-   wire Itmp15 ;
+   wire Itmp18 ;
+   wire Iin5 ;
    wire Iin0 ;
+   wire Itmp13 ;
+   wire Itmp19 ;
+   wire Iin7 ;
    wire Iin6 ;
    wire Iin2 ;
-   wire Itmp19 ;
-   wire Iin5 ;
-   wire Itmp14 ;
-   wire Iin10 ;
-   wire Itmp20 ;
-   wire Itmp18 ;
-   wire out ;
+   wire Iin11 ;
+   wire Itmp15 ;
    wire Itmp16 ;
+   wire Iin9 ;
+   wire Iin12 ;
+   wire Itmp21 ;
    wire Iin4 ;
    wire Iin8 ;
-   wire Itmp13 ;
+   wire Itmp17 ;
+   wire Itmp14 ;
+   wire Iin1 ;
+   wire out ;
+   wire Iin10 ;
+   wire Itmp20 ;
    wire Iin3 ;
 
 // --- instances

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_323_4/netlist/verilog.v

@@ -0,0 +1,93 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_323_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   output out;
+
+// -- signals ---
+   wire Itmp27 ;
+   wire Itmp40 ;
+   wire Iin20 ;
+   wire Iin22 ;
+   wire out ;
+   wire Iin18 ;
+   wire Iin14 ;
+   wire Iin7 ;
+   wire Itmp35 ;
+   wire Itmp28 ;
+   wire Itmp23 ;
+   wire Iin13 ;
+   wire Iin12 ;
+   wire Itmp29 ;
+   wire Iin10 ;
+   wire Itmp38 ;
+   wire Iin8 ;
+   wire Iin15 ;
+   wire Itmp37 ;
+   wire Itmp26 ;
+   wire Iin17 ;
+   wire Iin21 ;
+   wire Iin9 ;
+   wire Iin4 ;
+   wire Itmp24 ;
+   wire Itmp33 ;
+   wire Itmp39 ;
+   wire Iin0 ;
+   wire Iin19 ;
+   wire Itmp30 ;
+   wire Iin11 ;
+   wire Itmp25 ;
+   wire Iin3 ;
+   wire Itmp32 ;
+   wire Iin5 ;
+   wire Itmp34 ;
+   wire Iin16 ;
+   wire Itmp31 ;
+   wire Iin6 ;
+   wire Itmp36 ;
+   wire Iin2 ;
+   wire Iin1 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp23 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp24 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp25 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp26 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp27 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp28 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp29 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp30 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp31 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp32 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp34 ), .c1(Itmp23 ), .c2(Itmp24 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp35 ), .c1(Itmp25 ), .c2(Itmp26 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp36 ), .c1(Itmp27 ), .c2(Itmp28 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp37 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp39 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(out), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp33 ), .c1(Iin20 ), .c2(Iin21 ), .c3(Iin22 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(Itmp38 ), .c1(Itmp31 ), .c2(Itmp32 ), .c3(Itmp33 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els2  (.y(Itmp40 ), .c1(Itmp36 ), .c2(Itmp37 ), .c3(Itmp38 ), .vdd(vdd), .vss(vss));
+endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_324_4/netlist/verilog.v

@@ -1,101 +0,0 @@
-module tmpl_0_0dataflow__neuro_0_0ctree_324_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , out, vdd, vss); 
-   input vdd;
-   input vss;
-   input Iin0 ;
-   input Iin1 ;
-   input Iin2 ;
-   input Iin3 ;
-   input Iin4 ;
-   input Iin5 ;
-   input Iin6 ;
-   input Iin7 ;
-   input Iin8 ;
-   input Iin9 ;
-   input Iin10 ;
-   input Iin11 ;
-   input Iin12 ;
-   input Iin13 ;
-   input Iin14 ;
-   input Iin15 ;
-   input Iin16 ;
-   input Iin17 ;
-   input Iin18 ;
-   input Iin19 ;
-   input Iin20 ;
-   input Iin21 ;
-   input Iin22 ;
-   input Iin23 ;
-   output out;
-
-// -- signals ---
-   wire Itmp35 ;
-   wire Itmp27 ;
-   wire Iin2 ;
-   wire Itmp38 ;
-   wire Iin21 ;
-   wire Iin12 ;
-   wire Iin1 ;
-   wire Iin16 ;
-   wire Iin20 ;
-   wire Itmp32 ;
-   wire Itmp40 ;
-   wire Itmp44 ;
-   wire Iin17 ;
-   wire Iin14 ;
-   wire Iin8 ;
-   wire Itmp28 ;
-   wire Itmp29 ;
-   wire Iin0 ;
-   wire Itmp24 ;
-   wire Itmp33 ;
-   wire Itmp42 ;
-   wire Itmp34 ;
-   wire Itmp41 ;
-   wire Iin11 ;
-   wire Iin10 ;
-   wire Iin4 ;
-   wire Itmp31 ;
-   wire Iin19 ;
-   wire Itmp36 ;
-   wire Iin9 ;
-   wire Iin23 ;
-   wire Iin13 ;
-   wire Iin5 ;
-   wire Iin18 ;
-   wire out ;
-   wire Iin7 ;
-   wire Itmp25 ;
-   wire Itmp37 ;
-   wire Iin6 ;
-   wire Itmp26 ;
-   wire Iin3 ;
-   wire Itmp43 ;
-   wire Itmp39 ;
-   wire Iin22 ;
-   wire Iin15 ;
-   wire Itmp30 ;
-
-// --- instances
-A_2C_B_X1 IC2Els0  (.y(Itmp24 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els1  (.y(Itmp25 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els2  (.y(Itmp26 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els3  (.y(Itmp27 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els4  (.y(Itmp28 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els5  (.y(Itmp29 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els6  (.y(Itmp30 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els7  (.y(Itmp31 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els8  (.y(Itmp32 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els9  (.y(Itmp33 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els10  (.y(Itmp34 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els11  (.y(Itmp35 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els12  (.y(Itmp36 ), .c1(Itmp24 ), .c2(Itmp25 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els13  (.y(Itmp37 ), .c1(Itmp26 ), .c2(Itmp27 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els14  (.y(Itmp38 ), .c1(Itmp28 ), .c2(Itmp29 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els15  (.y(Itmp39 ), .c1(Itmp30 ), .c2(Itmp31 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els16  (.y(Itmp40 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els17  (.y(Itmp41 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els18  (.y(Itmp42 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els19  (.y(Itmp43 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
-A_2C_B_X1 IC2Els20  (.y(Itmp44 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
-A_3C_B_X1 IC3Els0  (.y(out), .c1(Itmp42 ), .c2(Itmp43 ), .c3(Itmp44 ), .vdd(vdd), .vss(vss));
-endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_329_4/netlist/verilog.v

@@ -0,0 +1,117 @@
+module tmpl_0_0dataflow__neuro_0_0ctree_329_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , out, vdd, vss); 
+   input vdd;
+   input vss;
+   input Iin0 ;
+   input Iin1 ;
+   input Iin2 ;
+   input Iin3 ;
+   input Iin4 ;
+   input Iin5 ;
+   input Iin6 ;
+   input Iin7 ;
+   input Iin8 ;
+   input Iin9 ;
+   input Iin10 ;
+   input Iin11 ;
+   input Iin12 ;
+   input Iin13 ;
+   input Iin14 ;
+   input Iin15 ;
+   input Iin16 ;
+   input Iin17 ;
+   input Iin18 ;
+   input Iin19 ;
+   input Iin20 ;
+   input Iin21 ;
+   input Iin22 ;
+   input Iin23 ;
+   input Iin24 ;
+   input Iin25 ;
+   input Iin26 ;
+   input Iin27 ;
+   input Iin28 ;
+   output out;
+
+// -- signals ---
+   wire Itmp52 ;
+   wire Itmp51 ;
+   wire Iin4 ;
+   wire Itmp36 ;
+   wire Iin13 ;
+   wire Itmp32 ;
+   wire Iin14 ;
+   wire Iin23 ;
+   wire Itmp41 ;
+   wire Iin22 ;
+   wire Iin0 ;
+   wire Itmp43 ;
+   wire Iin8 ;
+   wire Iin20 ;
+   wire Iin9 ;
+   wire Iin2 ;
+   wire Iin19 ;
+   wire Itmp30 ;
+   wire Iin16 ;
+   wire Iin24 ;
+   wire Itmp34 ;
+   wire Iin10 ;
+   wire Iin1 ;
+   wire Itmp29 ;
+   wire Itmp49 ;
+   wire Iin7 ;
+   wire Iin28 ;
+   wire Iin21 ;
+   wire Iin18 ;
+   wire Iin11 ;
+   wire Itmp44 ;
+   wire Iin6 ;
+   wire Itmp38 ;
+   wire Iin17 ;
+   wire Itmp35 ;
+   wire Iin3 ;
+   wire Iin27 ;
+   wire Itmp42 ;
+   wire Itmp45 ;
+   wire Itmp40 ;
+   wire Iin12 ;
+   wire Itmp50 ;
+   wire Itmp47 ;
+   wire Iin5 ;
+   wire Itmp31 ;
+   wire Iin15 ;
+   wire Iin26 ;
+   wire Itmp37 ;
+   wire Itmp48 ;
+   wire Itmp39 ;
+   wire Itmp46 ;
+   wire Iin25 ;
+   wire out ;
+   wire Itmp33 ;
+
+// --- instances
+A_2C_B_X1 IC2Els0  (.y(Itmp29 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els1  (.y(Itmp30 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els2  (.y(Itmp31 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els3  (.y(Itmp32 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els4  (.y(Itmp33 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els5  (.y(Itmp34 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els6  (.y(Itmp35 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els7  (.y(Itmp36 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els8  (.y(Itmp37 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els9  (.y(Itmp38 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els10  (.y(Itmp39 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els11  (.y(Itmp40 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els12  (.y(Itmp41 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els13  (.y(Itmp43 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els14  (.y(Itmp44 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els15  (.y(Itmp45 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els16  (.y(Itmp46 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els17  (.y(Itmp47 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els18  (.y(Itmp48 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els19  (.y(Itmp49 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els20  (.y(Itmp50 ), .c1(Itmp43 ), .c2(Itmp44 ), .vdd(vdd), .vss(vss));
+A_2C_B_X1 IC2Els21  (.y(Itmp51 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els0  (.y(Itmp42 ), .c1(Iin26 ), .c2(Iin27 ), .c3(Iin28 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els1  (.y(Itmp52 ), .c1(Itmp47 ), .c2(Itmp48 ), .c3(Itmp49 ), .vdd(vdd), .vss(vss));
+A_3C_B_X1 IC3Els2  (.y(out), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
+endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_330_4/netlist/verilog.v

@@ -34,62 +34,62 @@ module tmpl_0_0dataflow__neuro_0_0ctree_330_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Itmp45 ;
-   wire Iin2 ;
-   wire Itmp49 ;
-   wire Itmp43 ;
-   wire Iin12 ;
-   wire Iin10 ;
+   wire Itmp30 ;
+   wire Iin21 ;
    wire Iin25 ;
-   wire Itmp42 ;
-   wire Itmp32 ;
-   wire Itmp35 ;
-   wire Iin1 ;
-   wire Iin6 ;
-   wire Itmp31 ;
-   wire Iin19 ;
+   wire Itmp38 ;
+   wire Iin9 ;
+   wire Itmp47 ;
+   wire Itmp41 ;
+   wire Iin12 ;
+   wire Iin8 ;
+   wire Itmp34 ;
+   wire Itmp54 ;
+   wire Itmp51 ;
    wire Itmp52 ;
-   wire Itmp44 ;
+   wire Itmp48 ;
+   wire Iin17 ;
+   wire Iin14 ;
+   wire Itmp36 ;
+   wire Itmp32 ;
+   wire Iin26 ;
+   wire Iin16 ;
+   wire Iin5 ;
+   wire Iin10 ;
+   wire Iin24 ;
+   wire Iin15 ;
+   wire Iin6 ;
+   wire Itmp46 ;
+   wire Itmp42 ;
+   wire Iin23 ;
+   wire Iin19 ;
+   wire Itmp39 ;
    wire Iin11 ;
+   wire Iin18 ;
+   wire Itmp37 ;
+   wire Iin3 ;
+   wire Itmp45 ;
+   wire Iin22 ;
+   wire Itmp44 ;
+   wire Iin27 ;
+   wire Iin20 ;
+   wire Itmp31 ;
+   wire Itmp53 ;
+   wire Iin29 ;
+   wire Itmp40 ;
    wire Iin7 ;
    wire Iin4 ;
-   wire Iin3 ;
-   wire Iin27 ;
-   wire Iin18 ;
-   wire Itmp54 ;
-   wire Iin5 ;
-   wire Itmp37 ;
-   wire Iin28 ;
-   wire Iin16 ;
-   wire Iin9 ;
-   wire Itmp50 ;
-   wire Itmp47 ;
-   wire Iin29 ;
-   wire Iin23 ;
-   wire Itmp30 ;
-   wire Itmp53 ;
-   wire Itmp40 ;
-   wire Itmp38 ;
-   wire Itmp46 ;
-   wire Itmp36 ;
-   wire Iin0 ;
-   wire Iin22 ;
-   wire Iin14 ;
-   wire Iin26 ;
-   wire Iin21 ;
-   wire Iin17 ;
-   wire Iin15 ;
-   wire Itmp34 ;
+   wire Iin1 ;
    wire Itmp33 ;
-   wire Itmp41 ;
+   wire Itmp43 ;
    wire Iin13 ;
-   wire Iin20 ;
+   wire Iin2 ;
+   wire Itmp35 ;
+   wire Iin28 ;
    wire out ;
-   wire Itmp51 ;
-   wire Itmp48 ;
-   wire Itmp39 ;
-   wire Iin24 ;
-   wire Iin8 ;
+   wire Itmp49 ;
+   wire Iin0 ;
+   wire Itmp50 ;
 
 // --- instances
 A_2C_B_X1 IC2Els0  (.y(Itmp30 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_331_4/netlist/verilog.v

@@ -35,63 +35,63 @@ module tmpl_0_0dataflow__neuro_0_0ctree_331_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Itmp49 ;
-   wire Itmp39 ;
-   wire Iin27 ;
-   wire Iin14 ;
-   wire Iin3 ;
-   wire Iin30 ;
-   wire Itmp51 ;
-   wire Iin21 ;
-   wire Iin11 ;
-   wire Itmp52 ;
-   wire Iin12 ;
-   wire Itmp45 ;
-   wire Iin15 ;
-   wire Iin7 ;
-   wire Iin17 ;
-   wire Itmp53 ;
-   wire Iin9 ;
-   wire Itmp46 ;
-   wire Iin24 ;
-   wire Iin26 ;
-   wire Itmp48 ;
-   wire Itmp50 ;
-   wire Itmp37 ;
-   wire Iin4 ;
-   wire Iin2 ;
-   wire Iin0 ;
-   wire Itmp31 ;
-   wire Itmp55 ;
-   wire Itmp42 ;
-   wire Iin16 ;
-   wire Itmp54 ;
-   wire Iin19 ;
-   wire Iin29 ;
-   wire Itmp41 ;
-   wire Iin6 ;
-   wire Iin1 ;
-   wire Itmp34 ;
+   wire Itmp38 ;
    wire out ;
-   wire Itmp43 ;
-   wire Iin18 ;
-   wire Iin5 ;
-   wire Itmp40 ;
-   wire Iin8 ;
-   wire Iin23 ;
+   wire Iin22 ;
    wire Itmp36 ;
+   wire Itmp43 ;
+   wire Iin23 ;
+   wire Itmp42 ;
    wire Itmp32 ;
-   wire Iin13 ;
+   wire Itmp52 ;
+   wire Itmp53 ;
+   wire Iin27 ;
+   wire Iin11 ;
+   wire Iin4 ;
+   wire Iin21 ;
+   wire Iin20 ;
+   wire Iin16 ;
+   wire Iin6 ;
+   wire Itmp48 ;
+   wire Iin7 ;
+   wire Iin29 ;
+   wire Itmp46 ;
    wire Itmp33 ;
+   wire Itmp55 ;
+   wire Itmp45 ;
+   wire Iin14 ;
+   wire Iin8 ;
+   wire Itmp35 ;
+   wire Itmp54 ;
+   wire Iin28 ;
+   wire Iin30 ;
+   wire Iin24 ;
+   wire Itmp41 ;
+   wire Iin18 ;
+   wire Itmp31 ;
+   wire Iin26 ;
+   wire Iin19 ;
+   wire Iin12 ;
+   wire Itmp51 ;
+   wire Iin1 ;
+   wire Iin0 ;
+   wire Iin2 ;
+   wire Iin9 ;
+   wire Itmp34 ;
    wire Itmp44 ;
    wire Iin25 ;
-   wire Itmp38 ;
-   wire Itmp35 ;
-   wire Iin28 ;
+   wire Iin17 ;
+   wire Itmp50 ;
    wire Itmp47 ;
-   wire Iin22 ;
-   wire Iin20 ;
+   wire Itmp40 ;
+   wire Itmp39 ;
+   wire Itmp37 ;
+   wire Itmp49 ;
    wire Iin10 ;
+   wire Iin3 ;
+   wire Iin15 ;
+   wire Iin5 ;
+   wire Iin13 ;
 
 // --- instances
 A_2C_B_X1 IC2Els0  (.y(Itmp31 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_332_4/netlist/verilog.v

@@ -36,69 +36,69 @@ module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Itmp55 ;
-   wire Itmp49 ;
-   wire Iin21 ;
-   wire Itmp46 ;
-   wire Itmp41 ;
-   wire Iin6 ;
-   wire out ;
-   wire Iin26 ;
-   wire Iin7 ;
-   wire Itmp36 ;
-   wire Iin3 ;
-   wire Itmp59 ;
-   wire Iin19 ;
-   wire Itmp60 ;
-   wire Itmp51 ;
-   wire Itmp40 ;
-   wire Iin12 ;
-   wire Itmp57 ;
-   wire Iin29 ;
-   wire Iin20 ;
-   wire Iin10 ;
-   wire Iin2 ;
-   wire Itmp52 ;
    wire Iin23 ;
-   wire Itmp44 ;
-   wire Itmp38 ;
-   wire Iin28 ;
-   wire Iin22 ;
-   wire Iin4 ;
-   wire Itmp45 ;
-   wire Iin25 ;
-   wire Iin15 ;
-   wire Itmp39 ;
-   wire Iin1 ;
-   wire Itmp37 ;
-   wire Itmp32 ;
-   wire Iin5 ;
-   wire Itmp58 ;
-   wire Iin30 ;
-   wire Itmp42 ;
-   wire Iin14 ;
-   wire Itmp53 ;
-   wire Iin24 ;
-   wire Itmp33 ;
-   wire Iin8 ;
-   wire Iin27 ;
-   wire Iin13 ;
-   wire Iin9 ;
-   wire Itmp34 ;
-   wire Itmp61 ;
-   wire Iin18 ;
-   wire Itmp35 ;
-   wire Iin31 ;
-   wire Itmp43 ;
+   wire out ;
    wire Itmp56 ;
+   wire Iin2 ;
    wire Itmp47 ;
-   wire Iin17 ;
+   wire Itmp37 ;
+   wire Iin4 ;
+   wire Itmp46 ;
+   wire Itmp39 ;
    wire Iin11 ;
+   wire Iin5 ;
+   wire Itmp51 ;
+   wire Iin26 ;
+   wire Iin20 ;
+   wire Iin19 ;
+   wire Itmp36 ;
+   wire Itmp59 ;
    wire Itmp54 ;
-   wire Itmp50 ;
+   wire Itmp40 ;
    wire Itmp48 ;
-   wire Iin16 ;
+   wire Iin24 ;
+   wire Iin12 ;
+   wire Itmp61 ;
+   wire Iin30 ;
+   wire Iin29 ;
+   wire Iin27 ;
+   wire Iin25 ;
+   wire Itmp32 ;
+   wire Itmp44 ;
+   wire Iin15 ;
+   wire Itmp35 ;
    wire Iin0 ;
+   wire Itmp43 ;
+   wire Iin9 ;
+   wire Itmp53 ;
+   wire Itmp49 ;
+   wire Itmp42 ;
+   wire Iin18 ;
+   wire Itmp60 ;
+   wire Itmp57 ;
+   wire Itmp52 ;
+   wire Itmp34 ;
+   wire Iin13 ;
+   wire Itmp50 ;
+   wire Iin31 ;
+   wire Itmp45 ;
+   wire Iin21 ;
+   wire Iin17 ;
+   wire Iin10 ;
+   wire Iin3 ;
+   wire Iin28 ;
+   wire Itmp38 ;
+   wire Iin22 ;
+   wire Iin14 ;
+   wire Itmp33 ;
+   wire Iin16 ;
+   wire Iin8 ;
+   wire Itmp41 ;
+   wire Iin7 ;
+   wire Iin6 ;
+   wire Iin1 ;
+   wire Itmp58 ;
+   wire Itmp55 ;
 
 // --- instances
 A_2C_B_X1 IC2Els0  (.y(Itmp32 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_34_4/netlist/verilog.v

@@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0ctree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vd
    output out;
 
 // -- signals ---
-   wire Iin2 ;
-   wire Itmp5 ;
-   wire Itmp4 ;
-   wire Iin1 ;
-   wire Iin0 ;
    wire Iin3 ;
+   wire Iin0 ;
+   wire Itmp4 ;
    wire out ;
+   wire Itmp5 ;
+   wire Iin2 ;
+   wire Iin1 ;
 
 // --- instances
 A_2C_B_X1 IC2Els0  (.y(Itmp4 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_37_4/netlist/verilog.v

@@ -11,17 +11,17 @@ module tmpl_0_0dataflow__neuro_0_0ctree_37_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Iin5 ;
-   wire Itmp9 ;
-   wire Iin4 ;
    wire Itmp8 ;
-   wire Iin2 ;
-   wire Iin6 ;
-   wire Iin1 ;
-   wire Iin0 ;
    wire Iin3 ;
-   wire Itmp7 ;
    wire out ;
+   wire Iin0 ;
+   wire Iin6 ;
+   wire Iin4 ;
+   wire Iin2 ;
+   wire Iin1 ;
+   wire Itmp9 ;
+   wire Iin5 ;
+   wire Itmp7 ;
 
 // --- instances
 A_2C_B_X1 IC2Els0  (.y(Itmp7 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ctree_39_4/netlist/verilog.v

@@ -13,22 +13,22 @@ module tmpl_0_0dataflow__neuro_0_0ctree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Itmp12 ;
-   wire Itmp9 ;
-   wire Itmp10 ;
-   wire Iin7 ;
-   wire Iin0 ;
-   wire Iin2 ;
-   wire Iin8 ;
-   wire Itmp13 ;
    wire Iin5 ;
    wire Iin1 ;
-   wire Iin3 ;
-   wire out ;
-   wire Itmp11 ;
+   wire Itmp13 ;
+   wire Iin2 ;
+   wire Iin0 ;
    wire Itmp14 ;
-   wire Iin6 ;
+   wire Itmp10 ;
+   wire Itmp11 ;
+   wire Itmp9 ;
+   wire out ;
+   wire Iin3 ;
+   wire Iin8 ;
    wire Iin4 ;
+   wire Iin6 ;
+   wire Itmp12 ;
+   wire Iin7 ;
 
 // --- instances
 A_2C_B_X1 IC2Els0  (.y(Itmp9 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4/netlist/verilog.v

@@ -79,94 +79,94 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4(Iin_d0_d0 , Iin_d0_
    
 
 // -- signals ---
-   output Iout38 ;
+   output Iout19 ;
+   output Iout17 ;
+   output Iout12 ;
+   wire Iatree63_in3 ;
+   wire Iin_d2_d0 ;
+   output Iout54 ;
+   output Iout50 ;
+   output Iout23 ;
+   output Iout24 ;
+   wire Iatree63_in4 ;
+   output Iout47 ;
+   output Iout46 ;
+   output Iout0 ;
+   output Iout20 ;
+   wire Iin_d1_d1 ;
+   output Iout41 ;
+   output Iout40 ;
+   output Iout22 ;
    output Iout13 ;
    wire Iin_d1_d0 ;
-   output Iout45 ;
-   wire Iatree63_in1 ;
    output Iout33 ;
-   output Iout29 ;
-   output Iout14 ;
-   output Iout55 ;
-   output Iout37 ;
-   output Iout5 ;
-   wire Iin_d4_d1 ;
-   wire Iin_d3_d1 ;
-   output Iout63 ;
-   wire Iatree63_in0 ;
-   wire Iatree47_in4 ;
-   output Iout46 ;
-   output Iout36 ;
-   output Iout16 ;
-   output Iout59 ;
-   output Iout23 ;
-   output Iout19 ;
-   wire Iatree63_in3 ;
-   output Iout57 ;
-   wire Iatree63_in4 ;
-   output Iout10 ;
-   wire Iin_d5_d0 ;
-   output Iout61 ;
-   output Iout40 ;
+   output Iout6 ;
    wire Iin_d3_d0 ;
-   output Iout49 ;
-   wire Iatree59_in2 ;
-   output Iout60 ;
-   output Iout41 ;
-   output Iout18 ;
-   output Iout7 ;
-   wire Iin_d0_d0 ;
+   output Iout62 ;
    output Iout27 ;
-   output Iout54 ;
+   wire Iin_d2_d1 ;
    output Iout34 ;
+   wire Iatree55_in3 ;
+   output Iout52 ;
+   wire Iatree47_in4 ;
+   wire Iin_d4_d1 ;
+   output Iout44 ;
+   output Iout45 ;
    output Iout25 ;
+   output Iout10 ;
+   output Iout7 ;
+   wire Iin_d5_d0 ;
+   wire Iin_d4_d0 ;
+   output Iout9 ;
    output Iout8 ;
    output Iout30 ;
-   output Iout17 ;
-   output Iout4 ;
-   wire Iatree61_in1 ;
-   wire Iin_d2_d0 ;
-   output Iout44 ;
-   output Iout42 ;
-   output Iout35 ;
-   output Iout22 ;
-   output Iout56 ;
-   wire Iatree63_in5 ;
-   output Iout21 ;
-   output Iout15 ;
-   output Iout6 ;
-   output Iout2 ;
-   output Iout0 ;
-   output Iout31 ;
-   output Iout9 ;
-   output Iout52 ;
-   wire Iatree62_in0 ;
-   output Iout58 ;
-   wire Iin_d5_d1 ;
+   output Iout61 ;
    output Iout43 ;
-   output Iout32 ;
-   output Iout26 ;
    output Iout11 ;
-   output Iout1 ;
-   wire Iin_d4_d0 ;
-   wire Iin_d1_d1 ;
-   wire Iin_d0_d1 ;
-   output Iout39 ;
-   wire Iatree55_in3 ;
-   output Iout48 ;
-   output Iout3 ;
-   output Iout53 ;
-   output Iout51 ;
-   wire Iin_d2_d1 ;
-   output Iout62 ;
-   output Iout50 ;
-   output Iout24 ;
    wire Iatree63_in2 ;
+   wire Iatree62_in0 ;
+   output Iout60 ;
+   output Iout51 ;
+   output Iout3 ;
+   output Iout57 ;
+   output Iout49 ;
+   wire Iatree63_in5 ;
+   output Iout31 ;
+   output Iout14 ;
+   output Iout59 ;
+   output Iout39 ;
    output Iout28 ;
-   output Iout20 ;
+   output Iout16 ;
+   output Iout5 ;
+   output Iout4 ;
+   wire Iin_d5_d1 ;
+   output Iout56 ;
+   wire Iatree63_in1 ;
+   output Iout42 ;
+   output Iout29 ;
+   output Iout1 ;
+   wire Iatree59_in2 ;
+   output Iout58 ;
+   output Iout32 ;
+   output Iout15 ;
+   wire Iin_d0_d0 ;
+   wire Iin_d0_d1 ;
+   output Iout26 ;
+   wire Iatree63_in0 ;
    wire Iatree31_in5 ;
-   output Iout47 ;
-   output Iout12 ;
+   wire Iatree61_in1 ;
+   output Iout18 ;
+   wire Iin_d3_d1 ;
+   output Iout63 ;
+   output Iout53 ;
+   output Iout37 ;
+   output Iout36 ;
+   output Iout35 ;
+   output Iout21 ;
+   output Iout2 ;
+   output Iout55 ;
+   output Iout48 ;
+   output Iout38 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0  (.Iin0 (Iatree62_in0 ), .Iin1 (Iatree61_in1 ), .Iin2 (Iatree59_in2 ), .Iin3 (Iatree55_in3 ), .Iin4 (Iatree47_in4 ), .Iin5 (Iatree31_in5 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4/netlist/verilog.v

@@ -16,32 +16,32 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4(Iin_d0_d0 , Iin_
    
 
 // -- signals ---
-   wire Idecoder_final_refresh_d2_d0 ;
+   output Iout0 ;
+   wire Iin_d2_d1 ;
+   wire Iin_d1_d1 ;
+   wire Iin_d2_d0 ;
+   wire Idecoder_final_refresh_d0_d0 ;
    wire Iin_d0_d0 ;
-   wire Ien_ands_t0_y ;
    output Iout4 ;
+   wire Idecoder_final_refresh_d2_d1 ;
+   wire Idecoder_final_refresh_d1_d0 ;
+   wire Iin_d1_d0 ;
+   wire Iin_d0_d1 ;
+   wire Ien_ands_f0_y ;
    output Iout1 ;
    wire Ien_ands_t2_y ;
-   wire Iin_d2_d1 ;
-   wire Ien_ands_t1_y ;
-   wire Ien_ands_f2_y ;
-   wire Ien_ands_f0_y ;
-   wire en;
-   wire Iin_d1_d1 ;
-   wire Idecoder_final_refresh_d2_d1 ;
-   output Iout0 ;
-   wire Iin_d0_d1 ;
-   wire Idecoder_final_refresh_d1_d0 ;
-   output Iout5 ;
-   wire Iin_d2_d0 ;
-   wire Ien_ands_f1_y ;
-   wire Idecoder_final_refresh_d0_d0 ;
-   wire Idecoder_final_refresh_d0_d1 ;
-   wire Iin_d1_d0 ;
+   wire Idecoder_final_refresh_d2_d0 ;
    output Iout3 ;
    output Iout2 ;
+   wire Ien_ands_t1_y ;
+   wire Ien_ands_f2_y ;
    wire Isb_en_out0 ;
+   output Iout5 ;
    wire Idecoder_final_refresh_d1_d1 ;
+   wire Ien_ands_t0_y ;
+   wire en;
+   wire Idecoder_final_refresh_d0_d1 ;
+   wire Ien_ands_f1_y ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4 Idecoder  (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist/verilog.v

@@ -44,68 +44,68 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4(Iin_d0_d0 , Iin
    
 
 // -- signals ---
-   output Iout15 ;
-   wire Iin_d3_d0 ;
-   wire Iin_d1_d0 ;
-   output Iout14 ;
-   wire Iin_d1_d1 ;
-   wire Iin_d0_d0 ;
-   output Iout26 ;
-   output Iout18 ;
-   wire Ien_ands_t3_y ;
-   wire Ien_ands_f2_y ;
-   output Iout13 ;
-   output Iout10 ;
-   wire Ien_ands_t4_y ;
-   wire Iin_d2_d1 ;
    wire Idecoder_final_refresh_d3_d1 ;
-   wire Idecoder_final_refresh_d0_d0 ;
-   wire Idecoder_final_refresh_d3_d0 ;
-   wire Idecoder_final_refresh_d2_d1 ;
-   wire Idecoder_final_refresh_d1_d1 ;
-   output Iout28 ;
-   output Iout8 ;
-   output Iout24 ;
-   output Iout16 ;
-   wire Ien_ands_f1_y ;
-   output Iout22 ;
-   output Iout19 ;
-   output Iout9 ;
-   wire Iin_d4_d0 ;
-   wire en;
-   output Iout7 ;
-   output Iout6 ;
-   output Iout4 ;
-   wire Iin_d3_d1 ;
-   output Iout3 ;
-   wire Ien_ands_t0_y ;
-   wire Idecoder_final_refresh_d2_d0 ;
-   wire Ien_ands_f3_y ;
-   wire Idecoder_final_refresh_d4_d0 ;
-   output Iout29 ;
-   output Iout27 ;
-   wire Isb_en_out0 ;
-   wire Ien_ands_t2_y ;
-   output Iout11 ;
-   output Iout21 ;
-   output Iout0 ;
-   wire Ien_ands_f0_y ;
-   wire Idecoder_final_refresh_d0_d1 ;
-   wire Ien_ands_t1_y ;
-   wire Idecoder_final_refresh_d4_d1 ;
-   output Iout1 ;
-   output Iout5 ;
-   wire Iin_d4_d1 ;
-   output Iout23 ;
-   output Iout2 ;
-   wire Iin_d2_d0 ;
    wire Idecoder_final_refresh_d1_d0 ;
-   output Iout25 ;
+   wire Ien_ands_t1_y ;
+   wire en;
+   output Iout2 ;
+   output Iout27 ;
+   wire Iin_d3_d0 ;
+   wire Idecoder_final_refresh_d2_d1 ;
+   output Iout29 ;
    output Iout17 ;
-   output Iout12 ;
-   wire Ien_ands_f4_y ;
-   wire Iin_d0_d1 ;
+   wire Ien_ands_f2_y ;
    output Iout20 ;
+   output Iout11 ;
+   output Iout12 ;
+   output Iout5 ;
+   wire Iin_d4_d0 ;
+   wire Iin_d4_d1 ;
+   output Iout8 ;
+   output Iout25 ;
+   output Iout22 ;
+   wire Iin_d2_d1 ;
+   output Iout19 ;
+   output Iout13 ;
+   wire Ien_ands_f3_y ;
+   wire Ien_ands_f4_y ;
+   wire Ien_ands_t3_y ;
+   wire Iin_d0_d1 ;
+   wire Isb_en_out0 ;
+   wire Idecoder_final_refresh_d0_d1 ;
+   wire Iin_d1_d1 ;
+   wire Idecoder_final_refresh_d3_d0 ;
+   wire Ien_ands_t0_y ;
+   output Iout6 ;
+   output Iout24 ;
+   output Iout23 ;
+   wire Ien_ands_f1_y ;
+   wire Iin_d0_d0 ;
+   wire Idecoder_final_refresh_d4_d1 ;
+   wire Ien_ands_f0_y ;
+   output Iout15 ;
+   wire Iin_d2_d0 ;
+   wire Idecoder_final_refresh_d1_d1 ;
+   output Iout21 ;
+   output Iout4 ;
+   wire Idecoder_final_refresh_d4_d0 ;
+   wire Idecoder_final_refresh_d0_d0 ;
+   output Iout3 ;
+   wire Iin_d1_d0 ;
+   wire Idecoder_final_refresh_d2_d0 ;
+   output Iout18 ;
+   wire Ien_ands_t2_y ;
+   wire Iin_d3_d1 ;
+   output Iout1 ;
+   output Iout26 ;
+   output Iout16 ;
+   output Iout14 ;
+   output Iout7 ;
+   wire Ien_ands_t4_y ;
+   output Iout28 ;
+   output Iout10 ;
+   output Iout9 ;
+   output Iout0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4 Idecoder  (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4/netlist/verilog.v

@@ -76,104 +76,104 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4(Iin_d0_d0 , Iin
    
 
 // -- signals ---
-   wire Idecoder_final_refresh_d3_d0 ;
-   output Iout58 ;
-   output Iout43 ;
-   output Iout28 ;
-   wire Ien_ands_t2_y ;
-   wire Iin_d5_d1 ;
-   wire Idecoder_final_refresh_d4_d1 ;
-   wire Idecoder_final_refresh_d0_d0 ;
-   output Iout45 ;
-   output Iout56 ;
-   wire Idecoder_final_refresh_d3_d1 ;
-   wire Idecoder_final_refresh_d0_d1 ;
-   output Iout40 ;
-   output Iout37 ;
-   output Iout19 ;
-   output Iout21 ;
-   output Iout34 ;
-   output Iout8 ;
-   output Iout42 ;
-   output Iout10 ;
-   wire Ien_ands_f0_y ;
-   wire Idecoder_final_refresh_d5_d1 ;
-   output Iout59 ;
-   output Iout26 ;
-   output Iout15 ;
-   output Iout24 ;
-   wire Ien_ands_t4_y ;
-   output Iout25 ;
-   output Iout57 ;
-   output Iout46 ;
-   output Iout4 ;
-   wire Ien_ands_f2_y ;
-   wire Ien_ands_t0_y ;
-   output Iout47 ;
-   output Iout41 ;
-   output Iout23 ;
-   output Iout11 ;
-   wire Iin_d1_d0 ;
-   output Iout29 ;
-   output Iout22 ;
-   output Iout1 ;
-   wire Ien_ands_f4_y ;
-   wire Iin_d3_d1 ;
-   output Iout16 ;
-   output Iout0 ;
-   wire Iin_d0_d0 ;
-   output Iout14 ;
-   output Iout9 ;
-   output Iout3 ;
-   wire en;
-   wire Idecoder_final_refresh_d2_d0 ;
-   output Iout51 ;
-   output Iout39 ;
-   output Iout17 ;
-   wire Ien_ands_t5_y ;
-   wire Ien_ands_f1_y ;
-   wire Iin_d2_d0 ;
-   wire Ien_ands_t3_y ;
-   output Iout30 ;
-   output Iout27 ;
-   output Iout48 ;
-   output Iout35 ;
-   output Iout31 ;
-   output Iout20 ;
-   output Iout7 ;
-   wire Iin_d1_d1 ;
-   wire Idecoder_final_refresh_d4_d0 ;
-   wire Iin_d0_d1 ;
    output Iout49 ;
-   wire Iin_d4_d1 ;
-   wire Iin_d2_d1 ;
-   wire Isb_en_out0 ;
-   output Iout33 ;
-   output Iout32 ;
-   wire Idecoder_final_refresh_d2_d1 ;
-   output Iout44 ;
-   output Iout52 ;
+   wire Idecoder_final_refresh_d0_d0 ;
+   wire Iin_d3_d1 ;
+   output Iout50 ;
+   output Iout26 ;
+   wire Idecoder_final_refresh_d3_d0 ;
+   output Iout35 ;
+   output Iout17 ;
+   output Iout1 ;
+   output Iout42 ;
+   output Iout40 ;
+   output Iout22 ;
+   output Iout9 ;
+   output Iout48 ;
+   wire Iin_d3_d0 ;
+   output Iout34 ;
+   output Iout6 ;
+   output Iout0 ;
+   wire Iin_d5_d1 ;
+   wire Ien_ands_t2_y ;
+   output Iout25 ;
    output Iout13 ;
-   output Iout2 ;
-   wire Idecoder_final_refresh_d5_d0 ;
-   wire Idecoder_final_refresh_d1_d1 ;
+   wire Iin_d2_d1 ;
+   wire Iin_d0_d1 ;
+   wire Idecoder_final_refresh_d4_d0 ;
+   output Iout57 ;
+   output Iout24 ;
    output Iout55 ;
-   output Iout38 ;
-   output Iout36 ;
+   output Iout46 ;
+   output Iout2 ;
+   wire Iin_d4_d0 ;
+   wire Idecoder_final_refresh_d5_d1 ;
+   output Iout21 ;
+   output Iout19 ;
+   wire Ien_ands_f1_y ;
+   wire Idecoder_final_refresh_d2_d0 ;
+   output Iout27 ;
+   output Iout3 ;
+   wire Ien_ands_f3_y ;
+   wire Iin_d4_d1 ;
+   output Iout39 ;
    output Iout18 ;
    output Iout12 ;
-   output Iout6 ;
-   wire Ien_ands_t1_y ;
-   wire Idecoder_final_refresh_d1_d0 ;
-   output Iout50 ;
-   output Iout5 ;
-   wire Iin_d5_d0 ;
-   wire Iin_d4_d0 ;
-   wire Iin_d3_d0 ;
-   output Iout54 ;
-   output Iout53 ;
+   wire Ien_ands_t3_y ;
+   output Iout52 ;
+   output Iout31 ;
+   output Iout14 ;
+   output Iout8 ;
+   wire Idecoder_final_refresh_d2_d1 ;
+   output Iout56 ;
+   output Iout45 ;
+   output Iout36 ;
+   wire Ien_ands_f2_y ;
+   output Iout51 ;
+   output Iout33 ;
    wire Ien_ands_f5_y ;
-   wire Ien_ands_f3_y ;
+   wire Ien_ands_f0_y ;
+   output Iout43 ;
+   output Iout37 ;
+   output Iout30 ;
+   output Iout41 ;
+   output Iout5 ;
+   wire Ien_ands_t0_y ;
+   wire Idecoder_final_refresh_d1_d0 ;
+   wire Iin_d2_d0 ;
+   wire Iin_d1_d0 ;
+   wire Isb_en_out0 ;
+   output Iout58 ;
+   output Iout28 ;
+   output Iout16 ;
+   wire Iin_d1_d1 ;
+   wire Ien_ands_t1_y ;
+   wire Iin_d0_d0 ;
+   wire Idecoder_final_refresh_d0_d1 ;
+   output Iout54 ;
+   output Iout32 ;
+   output Iout20 ;
+   output Iout11 ;
+   output Iout10 ;
+   output Iout7 ;
+   wire Ien_ands_t5_y ;
+   wire Idecoder_final_refresh_d3_d1 ;
+   output Iout44 ;
+   wire Ien_ands_f4_y ;
+   output Iout4 ;
+   wire Idecoder_final_refresh_d5_d0 ;
+   wire Idecoder_final_refresh_d1_d1 ;
+   output Iout29 ;
+   output Iout23 ;
+   output Iout15 ;
+   wire Ien_ands_t4_y ;
+   wire Iin_d5_d0 ;
+   wire en;
+   wire Idecoder_final_refresh_d4_d1 ;
+   output Iout38 ;
+   output Iout47 ;
+   output Iout59 ;
+   output Iout53 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4 Idecoder  (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iin_d5_d0 (Ien_ands_f5_y ), .Iin_d5_d1 (Ien_ands_t5_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Iout30 (Iout30 ), .Iout31 (Iout31 ), .Iout32 (Iout32 ), .Iout33 (Iout33 ), .Iout34 (Iout34 ), .Iout35 (Iout35 ), .Iout36 (Iout36 ), .Iout37 (Iout37 ), .Iout38 (Iout38 ), .Iout39 (Iout39 ), .Iout40 (Iout40 ), .Iout41 (Iout41 ), .Iout42 (Iout42 ), .Iout43 (Iout43 ), .Iout44 (Iout44 ), .Iout45 (Iout45 ), .Iout46 (Iout46 ), .Iout47 (Iout47 ), .Iout48 (Iout48 ), .Iout49 (Iout49 ), .Iout50 (Iout50 ), .Iout51 (Iout51 ), .Iout52 (Iout52 ), .Iout53 (Iout53 ), .Iout54 (Iout54 ), .Iout55 (Iout55 ), .Iout56 (Iout56 ), .Iout57 (Iout57 ), .Iout58 (Iout58 ), .Iout59 (Iout59 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .Ifinal_refresh_d5_d0 (Idecoder_final_refresh_d5_d0 ), .Ifinal_refresh_d5_d1 (Idecoder_final_refresh_d5_d1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4/netlist/verilog.v

@@ -21,24 +21,24 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4(Iin_d0_d0 ,
    
 
 // -- signals ---
-   wire Iin_d1_d0 ;
-   output Iout5 ;
-   output Ifinal_refresh_d1_d1 ;
-   output Ifinal_refresh_d2_d1 ;
-   output Iout3 ;
-   output Ifinal_refresh_d0_d1 ;
    output Ifinal_refresh_d0_d0 ;
-   wire Iin_d0_d1 ;
+   output Iout0 ;
+   output Ifinal_refresh_d1_d0 ;
+   wire Iin_d2_d0 ;
    output Iout4 ;
+   output Iout1 ;
+   wire Iin_d0_d1 ;
+   output Ifinal_refresh_d0_d1 ;
    wire Iin_d2_d1 ;
    output Ifinal_refresh_d2_d0 ;
-   output Iout2 ;
-   output Iout1 ;
-   wire Iin_d2_d0 ;
+   wire Iin_d1_d0 ;
    wire Iin_d0_d0 ;
-   output Ifinal_refresh_d1_d0 ;
+   output Iout3 ;
+   output Iout2 ;
+   output Ifinal_refresh_d1_d1 ;
    wire Iin_d1_d1 ;
-   output Iout0 ;
+   output Iout5 ;
+   output Ifinal_refresh_d2_d1 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree0  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4/netlist/verilog.v

@@ -34,37 +34,37 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4(Iin_d0_d0
    
 
 // -- signals ---
-   output Iout2 ;
-   wire Iin_d2_d1 ;
-   output Ifinal_refresh_d1_d0 ;
-   output Iout7 ;
-   wire Iin_d3_d1 ;
-   output Iout9 ;
-   wire Iin_d1_d1 ;
    output Iout12 ;
-   wire Iin_d1_d0 ;
-   output Iout3 ;
-   output Ifinal_refresh_d0_d1 ;
-   output Iout4 ;
+   output Iout10 ;
+   output Iout9 ;
+   output Ifinal_refresh_d0_d0 ;
+   wire Iin_d3_d0 ;
    output Iout14 ;
    output Iout0 ;
-   wire Iin_d3_d0 ;
-   wire Iin_d2_d0 ;
-   output Iout11 ;
-   output Ifinal_refresh_d0_d0 ;
-   wire Iin_d0_d1 ;
-   output Iout10 ;
    output Iout8 ;
-   output Ifinal_refresh_d3_d1 ;
-   output Ifinal_refresh_d2_d0 ;
-   output Iout13 ;
-   output Iout6 ;
-   output Iout1 ;
-   wire Iin_d0_d0 ;
    output Ifinal_refresh_d2_d1 ;
-   output Ifinal_refresh_d3_d0 ;
+   output Ifinal_refresh_d3_d1 ;
+   wire Iin_d0_d1 ;
+   output Iout4 ;
    output Ifinal_refresh_d1_d1 ;
+   output Iout11 ;
+   wire Iin_d1_d1 ;
    output Iout5 ;
+   output Iout3 ;
+   wire Iin_d0_d0 ;
+   wire Iin_d3_d1 ;
+   output Ifinal_refresh_d1_d0 ;
+   output Ifinal_refresh_d0_d1 ;
+   output Ifinal_refresh_d3_d0 ;
+   output Iout13 ;
+   output Iout1 ;
+   output Iout7 ;
+   wire Iin_d1_d0 ;
+   output Ifinal_refresh_d2_d0 ;
+   wire Iin_d2_d0 ;
+   output Iout6 ;
+   wire Iin_d2_d1 ;
+   output Iout2 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree0  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4/netlist/verilog.v

@@ -53,56 +53,56 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4(Iin_d0_d0
    
 
 // -- signals ---
-   wire Iin_d0_d1 ;
-   output Iout23 ;
-   output Iout15 ;
-   output Iout14 ;
-   output Iout12 ;
-   output Iout26 ;
-   output Iout5 ;
-   output Iout22 ;
-   output Iout29 ;
-   output Iout19 ;
-   wire Iin_d3_d0 ;
-   wire Iin_d1_d0 ;
-   output Iout3 ;
-   output Ifinal_refresh_d4_d1 ;
-   output Iout2 ;
-   wire Iin_d3_d1 ;
-   output Iout25 ;
-   output Iout18 ;
-   output Iout9 ;
-   output Ifinal_refresh_d0_d1 ;
-   wire Iin_d0_d0 ;
-   output Iout21 ;
-   output Iout1 ;
-   wire Iin_d2_d0 ;
-   output Iout11 ;
-   output Ifinal_refresh_d1_d1 ;
-   output Iout8 ;
-   wire Iin_d1_d1 ;
-   output Iout17 ;
-   output Iout7 ;
-   wire Iin_d4_d1 ;
-   wire Iin_d2_d1 ;
-   output Iout20 ;
-   output Iout10 ;
-   output Ifinal_refresh_d0_d0 ;
    output Iout24 ;
+   output Iout11 ;
+   output Iout3 ;
+   output Iout18 ;
    output Iout16 ;
-   wire Iin_d4_d0 ;
+   output Ifinal_refresh_d0_d0 ;
+   wire Iin_d3_d0 ;
+   output Iout22 ;
    output Ifinal_refresh_d1_d0 ;
-   output Iout0 ;
-   output Ifinal_refresh_d3_d1 ;
-   output Ifinal_refresh_d4_d0 ;
+   output Iout29 ;
    output Iout27 ;
+   output Iout15 ;
+   wire Iin_d0_d1 ;
+   output Iout5 ;
    output Ifinal_refresh_d2_d1 ;
+   wire Iin_d4_d0 ;
+   output Iout10 ;
+   wire Iin_d2_d1 ;
+   output Ifinal_refresh_d4_d1 ;
+   output Iout9 ;
+   wire Iin_d0_d0 ;
    output Iout28 ;
-   output Iout4 ;
-   output Iout6 ;
-   output Ifinal_refresh_d2_d0 ;
    output Iout13 ;
+   output Ifinal_refresh_d4_d0 ;
    output Ifinal_refresh_d3_d0 ;
+   wire Iin_d2_d0 ;
+   output Iout4 ;
+   output Iout12 ;
+   output Ifinal_refresh_d1_d1 ;
+   wire Iin_d1_d1 ;
+   output Iout1 ;
+   output Iout26 ;
+   output Iout21 ;
+   output Iout23 ;
+   output Iout25 ;
+   output Iout8 ;
+   output Ifinal_refresh_d2_d0 ;
+   output Iout7 ;
+   output Iout0 ;
+   output Iout2 ;
+   output Ifinal_refresh_d0_d1 ;
+   output Iout14 ;
+   output Iout6 ;
+   output Ifinal_refresh_d3_d1 ;
+   wire Iin_d1_d0 ;
+   wire Iin_d4_d1 ;
+   output Iout17 ;
+   wire Iin_d3_d1 ;
+   output Iout20 ;
+   output Iout19 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree0  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4/netlist/verilog.v

@@ -87,90 +87,90 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4(Iin_d0_d0
    
 
 // -- signals ---
-   output Iout59 ;
    output Iout48 ;
-   output Iout12 ;
-   output Ifinal_refresh_d2_d1 ;
-   output Ifinal_refresh_d1_d1 ;
-   wire Iin_d0_d1 ;
-   output Iout40 ;
-   output Iout28 ;
-   output Iout19 ;
-   output Iout11 ;
-   output Iout44 ;
-   output Iout42 ;
-   output Iout25 ;
-   output Iout58 ;
-   output Iout46 ;
-   output Ifinal_refresh_d0_d1 ;
-   output Iout57 ;
-   output Ifinal_refresh_d4_d1 ;
-   output Iout14 ;
-   wire Iin_d3_d1 ;
-   output Iout53 ;
    output Iout31 ;
-   output Iout18 ;
-   output Ifinal_refresh_d5_d1 ;
-   output Iout17 ;
-   output Ifinal_refresh_d3_d1 ;
-   output Iout4 ;
-   output Iout21 ;
-   output Iout16 ;
-   output Iout29 ;
-   output Iout6 ;
-   output Ifinal_refresh_d4_d0 ;
-   output Iout39 ;
-   output Iout32 ;
-   output Iout20 ;
-   wire Iin_d5_d0 ;
-   wire Iin_d4_d0 ;
-   wire Iin_d3_d0 ;
    output Iout37 ;
-   output Iout36 ;
+   output Iout19 ;
+   output Ifinal_refresh_d4_d0 ;
+   output Iout45 ;
+   output Iout59 ;
+   output Iout34 ;
+   output Iout28 ;
+   output Iout27 ;
+   output Iout17 ;
+   output Iout2 ;
+   wire Iin_d1_d1 ;
+   output Iout16 ;
+   output Iout14 ;
+   output Iout21 ;
+   output Iout12 ;
+   wire Iin_d3_d0 ;
+   output Iout0 ;
+   output Ifinal_refresh_d1_d0 ;
+   output Iout54 ;
+   output Iout52 ;
+   output Iout11 ;
+   wire Iin_d3_d1 ;
+   wire Iin_d0_d1 ;
+   output Iout56 ;
+   output Ifinal_refresh_d5_d0 ;
+   wire Iin_d0_d0 ;
+   output Iout55 ;
+   output Iout50 ;
+   output Iout41 ;
+   output Iout33 ;
+   wire Iin_d5_d1 ;
+   output Iout29 ;
    output Iout22 ;
+   output Ifinal_refresh_d4_d1 ;
+   output Iout43 ;
+   wire Iin_d4_d0 ;
+   output Iout49 ;
+   output Iout47 ;
+   output Iout9 ;
+   output Iout5 ;
+   output Ifinal_refresh_d2_d1 ;
+   output Iout18 ;
+   output Iout1 ;
+   output Iout36 ;
+   output Iout35 ;
+   output Iout30 ;
+   output Ifinal_refresh_d3_d1 ;
+   output Iout40 ;
+   output Iout39 ;
+   wire Iin_d4_d1 ;
+   output Iout51 ;
+   output Iout25 ;
+   output Iout20 ;
+   output Iout42 ;
+   output Iout38 ;
+   output Iout32 ;
+   output Iout8 ;
+   output Iout7 ;
+   output Ifinal_refresh_d0_d1 ;
+   wire Iin_d5_d0 ;
+   output Iout26 ;
+   output Iout13 ;
+   output Iout6 ;
+   output Ifinal_refresh_d3_d0 ;
+   output Ifinal_refresh_d0_d0 ;
+   output Ifinal_refresh_d2_d0 ;
    wire Iin_d2_d0 ;
    wire Iin_d2_d1 ;
-   wire Iin_d1_d1 ;
-   output Iout9 ;
-   output Iout0 ;
-   output Ifinal_refresh_d5_d0 ;
-   output Iout55 ;
-   wire Iin_d4_d1 ;
-   output Iout45 ;
-   output Iout15 ;
-   output Iout7 ;
-   output Iout3 ;
-   wire Iin_d0_d0 ;
-   output Iout49 ;
-   output Ifinal_refresh_d3_d0 ;
-   output Iout34 ;
-   output Iout26 ;
-   output Iout35 ;
-   wire Iin_d5_d1 ;
-   output Iout41 ;
-   output Iout27 ;
-   output Iout30 ;
-   output Iout43 ;
-   output Iout10 ;
-   output Iout5 ;
-   output Iout51 ;
-   output Iout13 ;
-   output Iout8 ;
-   wire Iin_d1_d0 ;
-   output Iout33 ;
+   output Iout44 ;
    output Iout24 ;
-   output Iout54 ;
-   output Iout50 ;
+   output Iout58 ;
+   output Iout4 ;
+   output Iout3 ;
+   output Iout57 ;
+   output Iout46 ;
+   output Iout15 ;
+   wire Iin_d1_d0 ;
+   output Iout53 ;
+   output Ifinal_refresh_d5_d1 ;
+   output Iout10 ;
+   output Ifinal_refresh_d1_d1 ;
    output Iout23 ;
-   output Ifinal_refresh_d1_d0 ;
-   output Ifinal_refresh_d0_d0 ;
-   output Iout56 ;
-   output Iout52 ;
-   output Iout1 ;
-   output Iout38 ;
-   output Ifinal_refresh_d2_d0 ;
-   output Iout47 ;
-   output Iout2 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4/netlist/verilog.v

@@ -387,444 +387,444 @@ module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4(Iin_d0_d0
    
 
 // -- signals ---
-   output Ifinal_refresh_d6_d1 ;
-   output Iout275 ;
-   output Iout234 ;
-   output Iout25 ;
-   output Iout134 ;
-   output Iout135 ;
-   output Iout143 ;
-   output Iout268 ;
-   output Iout212 ;
-   output Iout186 ;
-   output Iout346 ;
-   output Iout303 ;
-   output Iout130 ;
-   output Iout146 ;
-   wire Iin_tX18_a ;
-   output Iout40 ;
-   wire Iin_fX11_a ;
-   output Iout92 ;
-   output Iout19 ;
-   wire Iin_tX34_a ;
-   wire Iin_fX26_a ;
-   wire Iin_fX25_a ;
-   output Iout111 ;
-   output Iout337 ;
-   output Iout325 ;
-   output Iout262 ;
-   output Iout252 ;
-   output Iout238 ;
-   output Iout100 ;
-   output Iout137 ;
-   output Iout52 ;
-   output Iout110 ;
-   wire Iin_d5_d1 ;
-   output Iout99 ;
-   output Iout61 ;
-   wire Iin_d1_d1 ;
-   output Iout271 ;
-   output Iout250 ;
-   wire Iin_fX21_a ;
-   output Iout147 ;
-   output Iout170 ;
-   output Iout182 ;
-   output Ifinal_refresh_d8_d0 ;
-   output Iout253 ;
-   output Iout151 ;
-   output Iout33 ;
-   output Iout142 ;
-   output Ifinal_refresh_d7_d1 ;
-   output Iout329 ;
-   output Iout240 ;
-   output Iout310 ;
-   output Ifinal_refresh_d8_d1 ;
-   wire Iin_tX32_a ;
-   wire Iin_fX18_a ;
-   wire Iin_tX10_a ;
-   wire Iin_fX12_a ;
-   output Iout179 ;
-   wire Iin_fX28_a ;
-   output Iout193 ;
-   wire Iin_fX22_a ;
-   output Iout73 ;
-   output Iout51 ;
-   output Iout254 ;
-   output Iout78 ;
-   output Iout109 ;
-   output Iout120 ;
-   output Iout155 ;
-   output Iout259 ;
-   wire Iin_fX33_a ;
+   output Iout317 ;
+   output Iout287 ;
    output Iout245 ;
-   wire Iin_fX32_a ;
-   output Iout336 ;
-   output Ifinal_refresh_d5_d1 ;
-   output Iout273 ;
-   output Iout263 ;
-   output Iout23 ;
-   output Iout192 ;
-   output Iout197 ;
-   wire Iin_d4_d1 ;
-   output Iout347 ;
-   output Iout96 ;
-   output Iout338 ;
-   wire Iin_tX29_a ;
-   output Ifinal_refresh_d7_d0 ;
-   output Iout249 ;
-   output Iout66 ;
-   output Iout129 ;
-   output Iout172 ;
-   output Iout207 ;
-   output Iout270 ;
-   wire Iin_tX20_a ;
-   output Iout149 ;
-   output Iout168 ;
-   wire Iin_tX23_a ;
-   output Iout45 ;
-   output Iout43 ;
-   output Iout21 ;
-   output Iout190 ;
-   output Iout204 ;
-   output Iout302 ;
-   wire Iin_d1_d0 ;
-   output Iout344 ;
-   output Iout255 ;
-   wire Iin_tX15_a ;
-   output Iout122 ;
-   output Iout88 ;
-   output Iout18 ;
-   output Iout297 ;
-   output Ifinal_refresh_d3_d0 ;
-   output Iout75 ;
-   output Iout64 ;
-   output Iout184 ;
+   output Iout92 ;
+   output Iout25 ;
+   output Ifinal_refresh_d8_d0 ;
+   output Iout346 ;
+   output Iout321 ;
+   output Iout306 ;
+   output Iout239 ;
+   output Iout155 ;
    output Iout283 ;
-   output Iout65 ;
-   output Iout202 ;
-   wire Iin_d2_d0 ;
-   output Iout30 ;
-   output Iout331 ;
-   output Iout80 ;
-   wire Iin_fX24_a ;
-   output Iout173 ;
-   output Iout256 ;
-   output Iout220 ;
-   output Iout264 ;
-   output Iout14 ;
-   wire Iin_fX13_a ;
-   output Iout341 ;
-   output Iout267 ;
-   output Iout241 ;
-   output Iout63 ;
-   output Iout117 ;
-   output Iout159 ;
-   output Iout175 ;
-   output Iout178 ;
-   output Iout295 ;
-   output Iout102 ;
-   output Iout114 ;
-   output Iout223 ;
+   wire Iin_fX34_a ;
+   output Iout96 ;
+   output Iout45 ;
+   output Iout4 ;
+   output Iout190 ;
+   output Iout320 ;
+   output Iout270 ;
+   output Iout243 ;
+   wire Iin_tX26_a ;
+   output Iout337 ;
+   output Iout301 ;
+   output Iout296 ;
+   wire Iin_tX24_a ;
+   output Iout183 ;
+   wire Iin_d1_d1 ;
+   output Iout138 ;
+   output Iout151 ;
+   output Iout213 ;
+   output Iout19 ;
+   output Iout325 ;
    output Iout56 ;
-   wire Iin_tX21_a ;
-   wire Iin_fX35_a ;
-   output Iout292 ;
-   output Ifinal_refresh_d0_d0 ;
-   output Iout280 ;
-   output Iout195 ;
-   wire Iin_tX16_a ;
-   output Iout305 ;
-   output Iout298 ;
-   output Iout227 ;
-   output Iout69 ;
-   output Iout115 ;
-   output Iout153 ;
-   output Iout343 ;
-   output Iout322 ;
-   output Iout281 ;
-   output Iout266 ;
-   output Iout133 ;
-   wire Iin_tX19_a ;
-   output Iout79 ;
-   output Iout29 ;
-   output Iout15 ;
-   output Iout108 ;
-   output Iout132 ;
-   wire Iin_d5_d0 ;
-   output Iout257 ;
-   output Iout165 ;
-   output Iout157 ;
-   wire Iin_d8_d0 ;
-   output Iout68 ;
-   output Iout36 ;
-   wire Iin_fX15_a ;
-   output Iout164 ;
-   output Iout339 ;
-   output Ifinal_refresh_d6_d0 ;
-   output Iout38 ;
+   output Iout17 ;
+   wire Iin_d1_d0 ;
+   wire Iin_d8_d1 ;
+   output Iout219 ;
+   output Iout215 ;
+   output Iout26 ;
+   output Iout297 ;
+   output Iout252 ;
+   output Iout90 ;
+   output Iout131 ;
+   output Iout166 ;
+   output Iout214 ;
+   output Iout118 ;
+   output Iout156 ;
+   output Iout202 ;
+   wire Iin_d0_d1 ;
+   output Iout43 ;
    output Iout11 ;
+   output Iout72 ;
+   output Iout102 ;
+   output Iout112 ;
+   output Iout115 ;
+   output Iout121 ;
+   output Iout197 ;
+   output Iout208 ;
+   wire Iin_tX12_a ;
+   wire Iin_fX31_a ;
+   output Iout277 ;
+   output Iout125 ;
+   output Iout204 ;
+   wire Iin_d0_d0 ;
+   output Iout68 ;
+   output Iout18 ;
+   output Iout15 ;
+   output Iout178 ;
+   wire Iin_fX14_a ;
+   wire Iin_fX18_a ;
+   output Iout75 ;
+   output Iout310 ;
+   output Iout268 ;
+   output Iout108 ;
+   output Iout231 ;
+   output Iout0 ;
+   wire Iin_d2_d0 ;
+   output Ifinal_refresh_d8_d1 ;
+   output Iout269 ;
+   wire Iin_tX35_a ;
+   output Iout223 ;
+   output Iout55 ;
+   wire Iin_tX21_a ;
+   output Iout167 ;
+   wire Iin_fX13_a ;
+   wire Iin_fX32_a ;
+   output Iout144 ;
+   output Iout145 ;
+   output Iout234 ;
+   output Iout224 ;
+   output Iout126 ;
+   output Iout189 ;
+   output Iout289 ;
+   output Iout275 ;
+   wire Iin_fX21_a ;
+   output Iout85 ;
+   output Iout160 ;
+   wire Iin_d7_d0 ;
+   wire Iin_d4_d0 ;
+   output Iout293 ;
+   output Iout86 ;
+   wire Iin_tX14_a ;
+   output Iout9 ;
+   output Iout3 ;
    output Iout171 ;
+   wire Iin_d6_d1 ;
+   output Iout227 ;
+   output Iout120 ;
+   output Iout315 ;
+   output Iout39 ;
+   output Iout262 ;
+   output Iout218 ;
+   output Iout41 ;
+   output Iout180 ;
+   output Iout236 ;
+   output Iout173 ;
+   output Iout314 ;
+   output Ifinal_refresh_d4_d1 ;
+   output Iout286 ;
+   wire Iin_tX11_a ;
+   output Iout157 ;
+   output Iout169 ;
+   output Iout205 ;
+   output Iout257 ;
+   output Iout116 ;
+   output Iout148 ;
+   output Iout220 ;
+   output Iout100 ;
+   output Iout76 ;
+   output Iout58 ;
+   output Iout52 ;
+   wire Iin_tX25_a ;
+   wire Iin_fX29_a ;
+   output Ifinal_refresh_d5_d0 ;
+   output Iout149 ;
+   output Iout159 ;
+   wire Iin_d5_d0 ;
+   output Iout338 ;
+   output Iout313 ;
+   output Iout200 ;
+   wire Iin_d6_d0 ;
+   output Ifinal_refresh_d2_d1 ;
+   output Iout258 ;
+   output Iout95 ;
+   output Iout302 ;
+   output Iout110 ;
+   wire Iin_fX24_a ;
+   output Iout168 ;
+   output Iout254 ;
+   output Iout64 ;
+   output Iout31 ;
+   wire Iin_tX9_a ;
+   wire Iin_fX9_a ;
+   output Iout104 ;
+   output Iout114 ;
+   output Iout122 ;
+   output Iout140 ;
+   wire Iin_tX18_a ;
+   output Ifinal_refresh_d0_d1 ;
+   output Iout237 ;
+   output Iout53 ;
+   output Iout226 ;
+   wire Iin_fX15_a ;
+   output Iout193 ;
+   output Ifinal_refresh_d2_d0 ;
+   output Ifinal_refresh_d1_d0 ;
+   output Iout246 ;
+   output Iout84 ;
+   output Iout2 ;
+   wire Iin_fX28_a ;
+   wire Iin_d3_d1 ;
+   output Iout284 ;
+   output Iout225 ;
+   output Iout67 ;
+   output Iout132 ;
+   output Iout179 ;
+   wire Iin_fX30_a ;
+   output Iout345 ;
+   output Iout278 ;
+   output Iout230 ;
+   output Iout34 ;
+   output Iout273 ;
+   wire Iin_fX25_a ;
+   output Iout16 ;
+   output Iout163 ;
+   output Iout191 ;
+   wire Iin_fX35_a ;
+   output Iout316 ;
+   output Iout62 ;
+   output Iout50 ;
+   output Iout44 ;
+   wire Iin_fX16_a ;
+   output Iout105 ;
+   output Iout188 ;
+   output Ifinal_refresh_d3_d1 ;
+   wire Iin_fX10_a ;
+   output Iout175 ;
+   output Iout194 ;
+   output Iout196 ;
+   output Iout47 ;
+   output Iout1 ;
+   output Iout195 ;
+   output Iout65 ;
+   output Iout42 ;
+   output Iout35 ;
+   output Iout79 ;
+   output Iout137 ;
+   output Iout142 ;
+   output Iout324 ;
+   output Iout292 ;
+   wire Iin_d4_d1 ;
+   output Iout141 ;
+   output Iout336 ;
+   output Ifinal_refresh_d3_d0 ;
+   output Iout228 ;
+   wire Iin_fX22_a ;
+   output Iout7 ;
+   output Iout192 ;
+   output Iout251 ;
+   output Iout78 ;
+   output Iout332 ;
+   output Ifinal_refresh_d7_d0 ;
+   output Iout211 ;
+   output Iout117 ;
+   output Iout130 ;
+   wire Iin_tX29_a ;
+   output Iout295 ;
+   output Ifinal_refresh_d1_d1 ;
+   output Iout63 ;
+   wire Iin_d3_d0 ;
+   output Iout331 ;
+   output Ifinal_refresh_d6_d0 ;
+   output Iout60 ;
+   output Iout172 ;
+   output Iout98 ;
+   output Iout77 ;
+   wire Iin_tX15_a ;
+   output Iout111 ;
+   wire Iin_fX27_a ;
+   output Iout271 ;
+   output Iout233 ;
+   output Iout232 ;
+   output Iout66 ;
    output Iout177 ;
+   output Iout341 ;
+   output Iout248 ;
+   output Iout235 ;
+   output Iout22 ;
+   output Iout221 ;
+   output Iout240 ;
+   output Iout91 ;
+   output Iout13 ;
+   output Iout339 ;
+   output Iout323 ;
+   output Iout128 ;
+   wire Iin_fX17_a ;
+   output Iout327 ;
+   output Iout97 ;
+   output Iout20 ;
+   output Iout101 ;
+   output Iout139 ;
+   output Iout146 ;
+   output Iout152 ;
+   output Iout344 ;
+   output Iout249 ;
+   output Iout49 ;
+   output Iout37 ;
+   output Iout29 ;
+   output Iout10 ;
+   output Iout106 ;
+   output Iout158 ;
+   wire Iin_d5_d1 ;
+   output Ifinal_refresh_d4_d0 ;
+   output Iout250 ;
+   output Iout244 ;
+   wire Iin_tX10_a ;
+   output Iout247 ;
+   output Iout174 ;
+   output Iout298 ;
+   output Iout89 ;
+   output Iout209 ;
+   output Iout307 ;
+   output Iout123 ;
+   output Iout147 ;
+   output Iout94 ;
+   output Iout27 ;
+   output Iout182 ;
+   output Iout201 ;
+   output Iout32 ;
+   output Iout12 ;
+   output Iout347 ;
+   wire Iin_tX13_a ;
+   output Iout308 ;
+   output Iout212 ;
+   output Iout124 ;
+   output Iout265 ;
+   output Iout256 ;
+   output Iout165 ;
+   wire Iin_d8_d0 ;
+   output Iout334 ;
+   output Iout294 ;
+   output Iout71 ;
+   output Iout127 ;
    output Iout333 ;
    output Iout261 ;
-   output Iout84 ;
-   output Iout28 ;
-   output Iout309 ;
-   output Iout219 ;
-   output Iout94 ;
-   wire Iin_tX13_a ;
-   wire Iin_fX31_a ;
-   output Iout22 ;
-   output Iout138 ;
-   output Iout158 ;
-   output Iout215 ;
-   wire Iin_fX19_a ;
-   output Iout162 ;
-   wire Iin_fX27_a ;
-   wire Iin_d6_d1 ;
-   output Iout332 ;
-   output Ifinal_refresh_d4_d0 ;
-   output Iout276 ;
-   output Iout304 ;
-   wire Iin_tX27_a ;
-   output Iout288 ;
-   output Iout85 ;
-   output Iout50 ;
-   output Iout24 ;
-   wire Iin_tX33_a ;
-   output Iout196 ;
-   output Iout315 ;
-   output Iout225 ;
-   output Iout13 ;
-   output Iout116 ;
-   output Iout58 ;
-   output Iout104 ;
-   output Iout166 ;
-   output Iout198 ;
-   output Iout154 ;
-   output Iout209 ;
-   output Iout321 ;
-   output Iout311 ;
-   output Ifinal_refresh_d1_d0 ;
-   output Iout237 ;
-   output Iout42 ;
-   wire Iin_tX24_a ;
-   output Iout90 ;
-   output Iout123 ;
-   wire Iin_tX17_a ;
+   wire Iin_tX23_a ;
+   output Iout14 ;
+   output Iout143 ;
+   output Ifinal_refresh_d7_d1 ;
    wire Iin_d7_d1 ;
-   output Iout59 ;
-   output Iout174 ;
-   output Iout189 ;
-   output Iout274 ;
-   output Iout230 ;
-   wire Iin_fX14_a ;
-   output Iout277 ;
-   output Iout48 ;
-   output Iout326 ;
-   output Iout289 ;
-   output Iout228 ;
-   output Iout70 ;
-   output Iout290 ;
-   output Iout9 ;
-   output Iout278 ;
-   wire Iin_fX10_a ;
-   output Iout118 ;
-   output Iout144 ;
-   output Iout35 ;
-   output Iout187 ;
-   output Iout306 ;
-   wire Iin_fX34_a ;
-   output Iout231 ;
-   output Iout60 ;
-   output Iout317 ;
-   output Iout308 ;
-   output Iout239 ;
-   wire Iin_fX20_a ;
-   output Iout74 ;
-   output Iout32 ;
-   output Iout20 ;
-   wire Iin_tX28_a ;
-   output Iout201 ;
-   output Iout224 ;
-   output Iout47 ;
-   output Iout16 ;
-   output Iout216 ;
-   output Iout2 ;
-   wire Iin_fX23_a ;
-   output Iout244 ;
-   output Iout112 ;
-   output Iout140 ;
-   wire Iin_fX29_a ;
-   output Iout206 ;
-   output Iout34 ;
-   output Iout124 ;
-   wire Iin_d3_d1 ;
-   output Iout342 ;
-   output Iout37 ;
-   output Iout235 ;
-   output Iout221 ;
-   wire Iin_tX12_a ;
-   wire Iin_d0_d1 ;
-   wire Iin_tX14_a ;
-   output Iout7 ;
-   output Iout150 ;
-   wire Iin_tX26_a ;
-   output Iout247 ;
-   output Iout3 ;
-   output Iout183 ;
-   output Iout233 ;
-   output Iout67 ;
-   wire Iin_d4_d0 ;
-   output Ifinal_refresh_d2_d1 ;
-   output Iout222 ;
-   output Iout98 ;
-   output Iout81 ;
-   output Iout26 ;
-   output Iout6 ;
-   wire Iin_d6_d0 ;
-   output Iout106 ;
-   output Iout205 ;
-   output Iout328 ;
-   output Iout229 ;
-   output Iout211 ;
-   output Iout54 ;
-   output Iout10 ;
-   output Iout8 ;
-   wire Iin_d7_d0 ;
-   output Iout72 ;
-   output Iout131 ;
-   output Iout191 ;
-   output Iout17 ;
-   wire Iin_d3_d0 ;
-   output Iout226 ;
-   wire Iin_tX31_a ;
-   output Iout320 ;
-   output Iout248 ;
-   output Iout213 ;
-   output Iout161 ;
-   output Iout323 ;
-   output Iout307 ;
-   output Iout95 ;
-   output Iout5 ;
-   output Iout334 ;
-   output Iout265 ;
-   output Iout214 ;
-   output Iout107 ;
-   wire Iin_d8_d1 ;
-   output Iout335 ;
-   output Iout246 ;
-   output Iout103 ;
-   output Iout127 ;
-   output Iout319 ;
-   wire Iin_tX25_a ;
-   output Iout148 ;
-   wire Iin_fX30_a ;
-   wire Iin_tX30_a ;
-   output Iout1 ;
-   output Iout194 ;
-   output Iout203 ;
-   output Iout77 ;
    output Iout46 ;
-   output Iout39 ;
-   output Iout272 ;
-   output Iout121 ;
-   output Iout296 ;
-   wire Iin_fX16_a ;
-   wire Iin_fX9_a ;
-   output Ifinal_refresh_d2_d0 ;
-   wire Iin_fX17_a ;
-   output Iout128 ;
-   output Iout101 ;
-   output Iout185 ;
-   output Iout318 ;
-   output Ifinal_refresh_d0_d1 ;
-   output Iout282 ;
-   output Iout113 ;
-   output Iout93 ;
-   output Iout27 ;
-   output Iout139 ;
-   output Iout340 ;
-   output Iout91 ;
-   output Iout293 ;
-   output Iout41 ;
-   output Iout31 ;
-   output Iout12 ;
-   output Iout55 ;
-   output Iout232 ;
-   output Iout97 ;
-   output Iout89 ;
-   output Iout163 ;
-   output Iout345 ;
-   output Iout44 ;
-   output Iout167 ;
-   output Iout314 ;
-   output Iout299 ;
-   output Iout291 ;
-   output Iout285 ;
-   output Iout269 ;
-   wire Iin_tX11_a ;
-   wire Iin_d2_d1 ;
-   output Iout145 ;
-   output Iout156 ;
-   output Iout316 ;
-   output Iout284 ;
-   output Iout87 ;
-   output Iout313 ;
-   output Iout217 ;
-   output Iout86 ;
-   output Iout125 ;
-   output Iout208 ;
-   output Ifinal_refresh_d5_d0 ;
-   output Iout286 ;
-   output Iout105 ;
-   output Iout324 ;
-   output Iout236 ;
-   wire Iin_tX9_a ;
-   wire Iin_tX22_a ;
-   output Iout180 ;
-   output Iout200 ;
-   output Iout330 ;
-   output Ifinal_refresh_d4_d1 ;
-   output Ifinal_refresh_d1_d1 ;
-   output Iout210 ;
-   output Iout76 ;
-   output Iout152 ;
-   output Iout188 ;
-   wire Iin_d0_d0 ;
-   output Ifinal_refresh_d3_d1 ;
-   output Iout83 ;
-   output Iout71 ;
-   output Iout199 ;
-   output Iout301 ;
+   wire Iin_tX16_a ;
+   output Iout309 ;
    output Iout279 ;
-   wire Iin_tX35_a ;
-   output Iout57 ;
-   output Iout169 ;
+   output Iout103 ;
    output Iout181 ;
-   output Iout327 ;
-   output Iout294 ;
-   output Iout49 ;
-   output Iout4 ;
-   output Iout126 ;
-   output Iout136 ;
-   output Iout82 ;
-   output Iout53 ;
-   output Iout160 ;
-   output Iout176 ;
-   output Iout243 ;
-   output Iout141 ;
-   output Iout119 ;
-   output Iout312 ;
-   output Iout300 ;
-   output Iout258 ;
-   output Iout251 ;
+   output Iout198 ;
+   output Iout80 ;
+   output Iout326 ;
+   output Ifinal_refresh_d0_d0 ;
+   output Iout241 ;
+   wire Iin_fX26_a ;
+   output Iout51 ;
+   output Iout229 ;
    output Iout242 ;
+   output Iout5 ;
+   output Iout162 ;
+   output Iout329 ;
+   wire Iin_fX33_a ;
+   output Iout255 ;
+   output Iout222 ;
+   output Iout164 ;
+   output Iout285 ;
+   output Iout61 ;
+   output Iout38 ;
+   output Iout150 ;
+   output Iout291 ;
+   output Iout267 ;
+   output Iout87 ;
+   output Iout36 ;
+   output Iout33 ;
+   output Iout129 ;
+   output Iout186 ;
+   output Iout322 ;
+   wire Iin_tX19_a ;
+   output Iout134 ;
+   output Iout210 ;
+   output Iout70 ;
+   output Iout57 ;
+   output Iout24 ;
+   output Iout299 ;
+   output Iout342 ;
+   output Ifinal_refresh_d6_d1 ;
+   output Iout280 ;
+   wire Iin_d2_d1 ;
+   output Iout319 ;
+   output Iout99 ;
+   output Iout184 ;
+   wire Iin_tX33_a ;
+   wire Iin_tX17_a ;
+   output Iout343 ;
+   wire Iin_tX30_a ;
+   output Iout328 ;
+   output Iout305 ;
+   output Iout264 ;
+   wire Iin_tX20_a ;
+   output Iout185 ;
+   output Iout206 ;
+   output Iout312 ;
+   output Iout272 ;
+   output Iout263 ;
+   output Iout303 ;
+   output Iout135 ;
+   output Iout282 ;
    output Iout260 ;
-   output Iout218 ;
-   output Iout62 ;
-   output Iout287 ;
-   output Iout0 ;
+   output Iout40 ;
+   output Iout28 ;
+   wire Iin_fX11_a ;
+   wire Iin_fX19_a ;
+   output Iout107 ;
+   output Iout119 ;
+   output Iout330 ;
+   output Iout276 ;
+   output Iout136 ;
+   output Iout311 ;
+   output Iout274 ;
+   output Iout82 ;
+   output Iout23 ;
+   output Iout207 ;
+   wire Iin_tX31_a ;
+   output Iout259 ;
+   output Iout8 ;
+   wire Iin_fX23_a ;
+   output Iout340 ;
+   output Iout253 ;
+   output Iout83 ;
+   output Iout187 ;
+   wire Iin_tX34_a ;
+   output Iout199 ;
+   output Iout93 ;
+   output Iout54 ;
+   output Iout176 ;
+   output Iout281 ;
+   output Iout238 ;
+   output Iout73 ;
+   output Iout30 ;
+   output Iout318 ;
+   output Iout290 ;
+   wire Iin_tX32_a ;
+   output Iout48 ;
+   output Iout21 ;
+   output Iout335 ;
+   wire Iin_fX12_a ;
+   output Iout109 ;
+   output Iout153 ;
+   wire Iin_tX28_a ;
+   output Iout69 ;
+   wire Iin_tX22_a ;
+   output Iout216 ;
+   wire Iin_fX20_a ;
+   output Iout154 ;
+   output Iout203 ;
+   output Ifinal_refresh_d5_d1 ;
+   output Iout6 ;
+   output Iout161 ;
+   output Iout288 ;
+   output Iout217 ;
+   output Iout74 ;
+   output Iout59 ;
+   output Iout113 ;
+   wire Iin_tX27_a ;
+   output Iout88 ;
+   output Iout133 ;
+   output Iout304 ;
+   output Iout300 ;
+   output Iout266 ;
+   output Iout81 ;
+   output Iout170 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0andtree_39_4 Iatree0  (.Iin0 (Iin_fX9_a ), .Iin1 (Iin_fX10_a ), .Iin2 (Iin_fX11_a ), .Iin3 (Iin_fX12_a ), .Iin4 (Iin_fX13_a ), .Iin5 (Iin_fX14_a ), .Iin6 (Iin_fX15_a ), .Iin7 (Iin_fX16_a ), .Iin8 (Iin_fX17_a ), .out(Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_32_4/netlist/verilog.v

@@ -7,16 +7,16 @@ module tmpl_0_0dataflow__neuro_0_0delayprog_32_4(out, in, Is0 , Is1 , vdd, vss);
    input Is1 ;
 
 // -- signals ---
-   wire I_a1 ;
-   wire Idly0_a ;
-   wire out ;
-   wire Idly1_a ;
+   wire Idly0_y ;
    wire Is0 ;
-   wire Idly2_y ;
+   wire I_a1 ;
+   wire Idly1_a ;
+   wire Idly0_a ;
    wire Idly2_a ;
    wire in;
+   wire out ;
+   wire Idly2_y ;
    wire Is1 ;
-   wire Idly0_y ;
 
 // --- instances
 AND2_X1 Iand20  (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0delayprog_34_4/netlist/verilog.v

@@ -9,34 +9,34 @@ module tmpl_0_0dataflow__neuro_0_0delayprog_34_4(out, in, Is0 , Is1 , Is2 , Is3
    input Is3 ;
 
 // -- signals ---
-   wire Idly6_y ;
-   wire Is1 ;
-   wire Idly4_a ;
-   wire Idly3_a ;
-   wire Is0 ;
-   wire Idly14_y ;
-   wire out ;
-   wire Idly10_a ;
-   wire Is3 ;
-   wire I_a2 ;
-   wire in;
-   wire Idly6_a ;
-   wire Idly9_a ;
    wire I_a3 ;
-   wire Idly5_a ;
-   wire Idly0_y ;
-   wire I_a1 ;
-   wire Idly0_a ;
    wire Idly1_a ;
+   wire Idly5_a ;
+   wire in;
    wire Idly14_a ;
+   wire Idly8_a ;
+   wire Idly9_a ;
+   wire I_a2 ;
+   wire Idly10_a ;
+   wire Idly0_y ;
+   wire Idly2_y ;
+   wire Idly4_a ;
+   wire out ;
+   wire Is3 ;
+   wire Idly12_a ;
    wire Idly11_a ;
    wire Idly2_a ;
-   wire Idly2_y ;
-   wire Idly12_a ;
-   wire Is2 ;
+   wire I_a1 ;
+   wire Idly6_y ;
    wire Idly13_a ;
+   wire Is0 ;
+   wire Is1 ;
    wire Idly7_a ;
-   wire Idly8_a ;
+   wire Idly3_a ;
+   wire Is2 ;
+   wire Idly6_a ;
+   wire Idly0_a ;
+   wire Idly14_y ;
 
 // --- instances
 AND2_X1 Iand20  (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0demux_330_4/netlist/verilog.v

@@ -193,209 +193,209 @@ module tmpl_0_0dataflow__neuro_0_0demux_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
    
 
 // -- signals ---
-   wire Icond_d_d0_d1 ;
-   output Iout2_d_d27_d1 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d17_d0 ;
-   output Iout1_d_d22_d1 ;
-   output Iin_v ;
-   wire _reset_BX ;
-   output Iout2_d_d3_d1 ;
-   output Iout2_d_d5_d1 ;
-   output Iout2_d_d8_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Iin_d_d22_d0 ;
-   output Iout2_d_d28_d0 ;
-   wire I_reset_BXX0 ;
-   output Iout2_d_d28_d1 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d15_d0 ;
-   output Iout1_d_d26_d1 ;
-   output Iout1_d_d25_d1 ;
-   output Iout1_d_d14_d1 ;
-   wire Iin_d_d25_d0 ;
-   wire Iout1_a_B_buf_out0 ;
-   output Iout2_d_d24_d1 ;
-   wire Iin_d_d28_d1 ;
-   output Iout1_d_d18_d0 ;
-   output Iout1_d_d15_d0 ;
-   wire Iin_d_d2_d1 ;
-   output Iout2_d_d16_d1 ;
-   wire Iin_d_d21_d1 ;
-   output Iout2_d_d18_d0 ;
-   output Iout1_d_d17_d0 ;
-   output Iout1_d_d16_d0 ;
-   output Iout1_d_d28_d1 ;
-   output Iout2_d_d26_d1 ;
-   wire Iin_d_d23_d0 ;
-   wire Iin_d_d24_d0 ;
-   output Iout2_d_d29_d0 ;
-   wire Iout2_a ;
-   wire Iout1_v ;
-   output Iout2_d_d6_d1 ;
-   output Iout2_d_d14_d1 ;
-   wire Iin_d_d20_d1 ;
-   wire Iin_d_d3_d0 ;
-   output Iout1_d_d27_d1 ;
-   output Iout2_d_d5_d0 ;
-   output Iout2_d_d11_d0 ;
-   output Iout2_d_d12_d0 ;
-   output Iout2_d_d22_d0 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d7_d0 ;
-   output Iout1_d_d19_d1 ;
-   wire Iin_d_d8_d1 ;
-   output Iout1_d_d28_d0 ;
-   output Iout1_d_d1_d0 ;
-   wire Iin_d_d10_d1 ;
-   output Iout1_d_d24_d1 ;
-   output Iout1_d_d19_d0 ;
-   output Iout2_d_d19_d1 ;
-   output Iout2_d_d2_d0 ;
-   wire Iout2_v ;
-   output Iout2_d_d6_d0 ;
-   output Iout2_d_d0_d0 ;
-   output Iout2_d_d27_d0 ;
-   output Iout2_d_d10_d1 ;
-   output Iout1_d_d3_d1 ;
-   output Iout1_d_d26_d0 ;
-   output Iout1_d_d11_d0 ;
-   wire Iin_d_d25_d1 ;
-   output Iout1_d_d29_d0 ;
-   output Iout1_d_d13_d0 ;
-   wire _en ;
-   wire reset_B;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d5_d0 ;
-   output Iout1_d_d16_d1 ;
-   output Iout1_d_d5_d1 ;
-   output Iout1_d_d23_d0 ;
-   output Iout1_d_d4_d0 ;
-   output Iout1_d_d0_d0 ;
-   output Iout2_d_d18_d1 ;
-   wire Iin_d_d10_d0 ;
-   wire Iin_d_d21_d0 ;
-   output Iout1_d_d10_d1 ;
-   wire Iin_d_d26_d0 ;
-   output Iout1_d_d12_d1 ;
-   output Iout1_d_d1_d1 ;
-   output Iout2_d_d12_d1 ;
-   wire Iin_d_d19_d1 ;
-   wire Iin_d_d20_d0 ;
-   wire _out_v ;
-   wire Iin_d_d17_d1 ;
-   output Iout1_d_d27_d0 ;
-   output Iout1_d_d10_d0 ;
-   wire Iin_d_d29_d1 ;
-   output Iout2_d_d9_d0 ;
-   output Iout1_d_d9_d0 ;
-   output Iout1_d_d8_d0 ;
-   output Iout2_d_d9_d1 ;
-   wire Iin_d_d27_d1 ;
-   output Iout2_d_d10_d0 ;
-   output Iout1_d_d4_d1 ;
-   wire Iin_d_d3_d1 ;
-   output Iout2_d_d7_d1 ;
-   wire Iin_d_d14_d1 ;
-   output Iout2_d_d13_d0 ;
-   wire I_c_t_buf0 ;
-   output Iout2_d_d7_d0 ;
-   output Iout1_d_d0_d1 ;
-   output Iout1_d_d2_d0 ;
-   wire _out1_a_B ;
+   output Iout1_d_d7_d0 ;
    wire _c_v ;
-   wire Iin_d_d29_d0 ;
-   wire Iin_d_d26_d1 ;
-   output Iout1_d_d9_d1 ;
-   wire Iin_d_d5_d1 ;
-   output Iout1_d_d20_d0 ;
-   wire Icond_d_d0_d0 ;
-   wire Iout2_a_B_buf_out0 ;
-   wire Iin_d_d19_d0 ;
-   wire Iin_d_d7_d1 ;
-   output Iout2_d_d15_d1 ;
-   wire Iin_d_d8_d0 ;
-   output Iout1_d_d12_d0 ;
-   wire Iin_d_d15_d1 ;
-   wire Iin_d_d16_d1 ;
-   output Iout2_d_d29_d1 ;
-   wire Iin_d_d18_d0 ;
-   output Iout1_d_d6_d0 ;
-   output Iout2_d_d4_d1 ;
-   output Iout2_d_d25_d1 ;
-   output Iout1_d_d18_d1 ;
-   output Iout1_d_d17_d1 ;
-   output Iout1_d_d7_d1 ;
-   output Iout2_d_d17_d1 ;
-   wire Iin_d_d16_d0 ;
-   output Iout1_d_d11_d1 ;
-   wire Iin_d_d12_d1 ;
-   output Iout2_d_d4_d0 ;
-   output Iout2_d_d8_d0 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d0_d1 ;
-   output Iout2_d_d19_d0 ;
-   output Iout2_d_d20_d0 ;
+   wire Iin_d_d4_d0 ;
    output Iout2_d_d23_d0 ;
-   wire Iout1_a ;
-   output Iout2_d_d0_d1 ;
-   output Iout1_d_d29_d1 ;
-   output Iout1_d_d20_d1 ;
-   output Iout2_d_d25_d0 ;
-   output Iout1_d_d21_d1 ;
-   wire _in_v ;
+   output Iout1_d_d23_d1 ;
+   output Iout1_d_d7_d1 ;
    wire _out2_a_B ;
-   output Iin_a ;
-   output Iout2_d_d20_d1 ;
+   wire Iin_d_d0_d1 ;
+   output Iout2_d_d11_d0 ;
+   output Iout2_d_d6_d1 ;
    output Iout2_d_d21_d1 ;
-   output Iout2_d_d1_d0 ;
-   output Iout2_d_d2_d1 ;
+   output Iout2_d_d22_d1 ;
+   output Iout2_d_d23_d1 ;
+   output Iout2_d_d20_d0 ;
+   output Iout1_d_d4_d1 ;
+   wire Iout1_v ;
+   wire Iin_d_d7_d0 ;
+   output Iout1_d_d2_d0 ;
+   wire Iin_d_d16_d1 ;
+   output Iout2_d_d25_d1 ;
+   output Iout1_d_d21_d1 ;
+   output Iout1_d_d29_d0 ;
+   output Iout1_d_d27_d0 ;
+   wire Iin_d_d9_d1 ;
    output Iout2_d_d14_d0 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d23_d1 ;
-   output Iout1_d_d8_d1 ;
-   output Iout2_d_d1_d1 ;
-   wire Iin_d_d22_d1 ;
-   output Iout2_d_d3_d0 ;
-   output Iout2_d_d17_d0 ;
    output Iout2_d_d21_d0 ;
+   output Iout1_d_d18_d0 ;
+   output Iout2_d_d0_d0 ;
+   output Iout1_d_d22_d1 ;
+   wire _in_v ;
+   wire Iout2_a ;
+   wire Iin_d_d21_d0 ;
+   output Iout1_d_d27_d1 ;
+   output Iout1_d_d6_d0 ;
+   output Iout1_d_d1_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d13_d1 ;
+   output Iout2_d_d26_d1 ;
+   output Iout1_d_d20_d1 ;
+   output Iout1_d_d16_d1 ;
+   output Iout1_d_d16_d0 ;
+   output Iout2_d_d10_d0 ;
+   output Iout2_d_d17_d0 ;
+   output Iout1_d_d4_d0 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d11_d0 ;
+   output Iout2_d_d17_d1 ;
+   output Iout2_d_d18_d1 ;
+   output Iout1_d_d19_d1 ;
+   output Iout1_d_d18_d1 ;
+   output Iout1_d_d20_d0 ;
+   output Iout1_d_d19_d0 ;
+   wire Iout2_a_B_buf_out0 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d20_d0 ;
+   output Iout1_d_d23_d0 ;
+   wire Iin_d_d29_d1 ;
+   output Iout2_d_d29_d0 ;
+   wire Iin_d_d15_d1 ;
+   output Iout2_d_d2_d0 ;
+   wire Iin_d_d12_d0 ;
    output Iout1_d_d24_d0 ;
-   output Iout1_d_d14_d0 ;
    output Icond_v ;
    output Iout2_d_d13_d1 ;
-   wire Iin_d_d13_d1 ;
-   output Iout2_d_d23_d1 ;
+   output Iout2_d_d14_d1 ;
+   output Iout1_d_d26_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout2_d_d12_d1 ;
+   output Iout2_d_d27_d1 ;
+   output Iout2_d_d25_d0 ;
+   output Iout1_d_d28_d1 ;
+   output Iout1_d_d8_d1 ;
+   output Iout2_d_d7_d0 ;
+   wire Iin_d_d18_d0 ;
+   wire I_c_f_buf0 ;
+   output Iout2_d_d28_d0 ;
+   output Iout2_d_d20_d1 ;
+   output Iout1_d_d15_d0 ;
+   output Iout1_d_d0_d0 ;
+   output Iout2_d_d2_d1 ;
+   output Iout2_d_d26_d0 ;
+   output Iout2_d_d16_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire _en ;
+   output Iout2_d_d10_d1 ;
+   wire Iin_d_d22_d0 ;
+   output Iout1_d_d28_d0 ;
+   wire Iin_d_d28_d0 ;
+   wire Iout_en_buf_out0 ;
+   output Iout2_d_d4_d0 ;
+   output Iout1_d_d3_d1 ;
+   output Iout1_d_d5_d0 ;
+   wire Iout1_a_B_buf_out0 ;
+   wire Iin_d_d27_d0 ;
+   output Iout2_d_d8_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d26_d1 ;
+   wire Iout1_a ;
+   output Iout2_d_d8_d0 ;
+   output Iout1_d_d26_d1 ;
+   output Iout1_d_d1_d1 ;
+   output Iout2_d_d1_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d26_d0 ;
+   output Iout1_d_d8_d0 ;
+   wire Icond_d_d0_d0 ;
+   output Iout2_d_d0_d1 ;
+   output Iout1_d_d17_d1 ;
+   output Iout2_d_d29_d1 ;
+   wire Iin_d_d3_d0 ;
+   output Iout1_d_d12_d1 ;
+   output Iout1_d_d6_d1 ;
+   output Iout2_d_d4_d1 ;
+   output Iout2_d_d18_d0 ;
+   wire Iin_d_d23_d0 ;
+   output Iout2_d_d15_d1 ;
+   output Iout2_d_d24_d1 ;
+   wire Iin_d_d0_d0 ;
+   output Iout1_d_d13_d1 ;
+   wire Iin_d_d19_d0 ;
+   output Iout1_d_d9_d1 ;
+   output Iin_a ;
+   wire Iin_d_d1_d1 ;
+   wire _out1_a_B ;
+   wire I_c_t_buf0 ;
+   wire Iin_d_d12_d1 ;
+   output Iout1_d_d14_d0 ;
+   output Iout1_d_d10_d0 ;
+   output Iout1_d_d9_d0 ;
+   wire Iin_d_d14_d1 ;
+   output Iout1_d_d22_d0 ;
+   wire _reset_BX ;
+   wire Iin_d_d7_d1 ;
+   output Iout1_d_d21_d0 ;
+   wire Iout2_v ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d16_d0 ;
+   output Iout2_d_d22_d0 ;
+   output Iout2_d_d5_d1 ;
+   output Iout2_d_d28_d1 ;
+   output Iout1_d_d24_d1 ;
+   output Iout1_d_d12_d0 ;
+   output Iout2_d_d6_d0 ;
+   output Iout1_d_d15_d1 ;
+   wire Icond_d_d0_d1 ;
+   wire Iin_d_d2_d1 ;
+   output Iout2_d_d9_d1 ;
+   output Iout2_d_d16_d0 ;
+   wire reset_B;
+   wire Iin_d_d6_d1 ;
+   output Iout2_d_d5_d0 ;
+   wire Iin_d_d8_d0 ;
+   output Iout1_d_d25_d0 ;
+   output Iout2_d_d19_d1 ;
+   wire Iin_d_d28_d1 ;
    wire Iin_d_d1_d0 ;
    wire Iin_d_d2_d0 ;
-   output Iout1_d_d23_d1 ;
-   output Iout1_d_d6_d1 ;
-   wire Iin_d_d4_d1 ;
-   output Iout2_d_d16_d0 ;
-   output Iout2_d_d24_d0 ;
-   wire Iin_d_d12_d0 ;
-   output Iout2_d_d15_d0 ;
-   output Iout1_d_d13_d1 ;
-   output Iout2_d_d11_d1 ;
-   output Iout2_d_d26_d0 ;
-   output Iout1_d_d21_d0 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d0_d0 ;
-   output Iout1_d_d5_d0 ;
-   output Iout1_d_d3_d0 ;
-   wire Iout_en_buf_out0 ;
-   output Iout1_d_d7_d0 ;
-   wire Iin_d_d27_d0 ;
    wire Iin_d_d13_d0 ;
+   output Iout1_d_d25_d1 ;
+   wire Iin_d_d6_d0 ;
+   output Iout1_d_d0_d1 ;
+   wire I_reset_BXX0 ;
+   output Iout2_d_d3_d0 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d24_d1 ;
+   output Iout2_d_d12_d0 ;
+   output Iout2_d_d13_d0 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d25_d0 ;
+   output Iout1_d_d17_d0 ;
+   output Iout2_d_d1_d1 ;
+   output Iout1_d_d11_d0 ;
+   output Iout1_d_d11_d1 ;
+   output Iout1_d_d10_d1 ;
+   output Iin_v ;
+   output Iout2_d_d7_d1 ;
+   output Iout1_d_d13_d0 ;
+   output Iout2_d_d19_d0 ;
+   output Iout1_d_d5_d1 ;
+   output Iout1_d_d3_d0 ;
+   wire _out_v ;
+   output Iout2_d_d24_d0 ;
    output Iout1_d_d2_d1 ;
-   output Iout1_d_d25_d0 ;
-   output Iout1_d_d22_d0 ;
-   wire Iin_d_d28_d0 ;
-   output Iout1_d_d15_d1 ;
-   wire I_c_f_buf0 ;
-   wire Iin_d_d9_d1 ;
-   output Iout2_d_d22_d1 ;
+   output Iout2_d_d27_d0 ;
+   output Iout2_d_d3_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d10_d0 ;
+   output Iout2_d_d15_d0 ;
+   wire Iin_d_d17_d1 ;
+   output Iout2_d_d9_d0 ;
+   output Iout1_d_d29_d1 ;
+   output Iout1_d_d14_d1 ;
+   wire Iin_d_d4_d1 ;
+   output Iout2_d_d11_d1 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d23_d1 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0demux_331_4/netlist/verilog.v

@@ -199,215 +199,215 @@ module tmpl_0_0dataflow__neuro_0_0demux_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_
    
 
 // -- signals ---
-   wire Iin_d_d26_d0 ;
-   output Iout2_d_d11_d1 ;
-   output Iout2_d_d16_d0 ;
-   output Iout1_d_d9_d0 ;
    output Iout1_d_d1_d0 ;
-   wire Iin_d_d14_d0 ;
-   output Iout2_d_d8_d1 ;
-   wire _en ;
-   output Iout2_d_d9_d1 ;
-   output Iout2_d_d10_d1 ;
-   output Iout2_d_d25_d1 ;
-   output Iout2_d_d8_d0 ;
-   output Iout2_d_d9_d0 ;
-   output Iout1_d_d5_d0 ;
-   wire _in_v ;
-   output Icond_v ;
-   wire Iin_d_d8_d1 ;
-   wire Iin_d_d25_d1 ;
-   output Iout2_d_d12_d0 ;
-   wire Iin_d_d12_d1 ;
-   output Iout1_d_d18_d1 ;
-   output Iout2_d_d17_d0 ;
-   output Iout2_d_d21_d0 ;
-   output Iout2_d_d2_d1 ;
    wire Iin_d_d3_d1 ;
-   output Iout1_d_d30_d1 ;
-   wire Icond_d_d0_d1 ;
-   output Iout2_d_d20_d0 ;
-   output Iout2_d_d23_d0 ;
-   wire Iin_d_d5_d0 ;
-   output Iout1_d_d12_d1 ;
-   wire Iin_d_d17_d0 ;
-   output Iout1_d_d16_d1 ;
-   output Iout1_d_d15_d1 ;
-   output Iout1_d_d26_d0 ;
-   wire Iin_d_d13_d1 ;
-   output Iout2_d_d24_d1 ;
-   output Iout1_d_d0_d0 ;
-   wire I_reset_BXX0 ;
-   wire _out2_a_B ;
-   wire Iin_d_d9_d1 ;
-   wire _reset_BX ;
-   output Iout2_d_d26_d0 ;
-   output Iout2_d_d23_d1 ;
-   output Iout2_d_d5_d0 ;
-   wire Iin_d_d29_d0 ;
-   output Iout2_d_d27_d0 ;
-   wire reset_B;
-   wire Iin_d_d18_d1 ;
-   output Iout1_d_d11_d0 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d19_d0 ;
-   output Iout2_d_d30_d1 ;
-   output Iout1_d_d29_d1 ;
-   output Iout1_d_d27_d1 ;
-   output Iout1_d_d21_d1 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d23_d1 ;
-   wire Iin_d_d24_d1 ;
-   output Iout2_d_d19_d0 ;
-   output Iout1_d_d7_d0 ;
-   wire Iin_d_d27_d1 ;
-   output Iout2_d_d3_d0 ;
-   output Iout1_d_d2_d1 ;
-   output Iout1_d_d4_d0 ;
-   output Iout1_d_d19_d1 ;
-   output Iout1_d_d8_d0 ;
-   output Iout2_d_d22_d1 ;
-   output Iout1_d_d8_d1 ;
-   output Iout1_d_d7_d1 ;
-   output Iout2_d_d22_d0 ;
-   output Iout1_d_d5_d1 ;
-   output Iout1_d_d22_d0 ;
-   output Iout1_d_d16_d0 ;
-   wire Iin_d_d21_d1 ;
-   output Iout2_d_d18_d0 ;
-   wire Iin_d_d25_d0 ;
-   output Iout1_d_d18_d0 ;
-   wire Icond_d_d0_d0 ;
-   output Iout2_d_d6_d0 ;
-   output Iout1_d_d26_d1 ;
-   output Iout1_d_d9_d1 ;
-   output Iout1_d_d27_d0 ;
-   wire Iout1_a_B_buf_out0 ;
-   output Iout2_d_d29_d0 ;
-   output Iout2_d_d5_d1 ;
-   wire Iin_d_d13_d0 ;
-   output Iout2_d_d26_d1 ;
-   wire Iin_d_d30_d1 ;
-   wire Iin_d_d9_d0 ;
-   output Iout1_d_d2_d0 ;
-   wire Iout1_a ;
-   wire Iin_d_d10_d1 ;
-   output Iout1_d_d28_d1 ;
-   output Iout1_d_d0_d1 ;
-   wire I_c_f_buf0 ;
-   wire Iout_en_buf_out0 ;
-   wire Iin_d_d20_d1 ;
-   wire Iin_d_d6_d0 ;
-   output Iout1_d_d23_d1 ;
-   output Iout1_d_d13_d1 ;
-   output Iout2_d_d19_d1 ;
-   wire Iin_d_d28_d1 ;
-   wire Iin_d_d24_d0 ;
-   output Iout1_d_d14_d1 ;
-   output Iout1_d_d20_d0 ;
-   wire Iout2_a ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d16_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout1_d_d30_d0 ;
-   output Iout1_d_d19_d0 ;
-   output Iout1_d_d17_d0 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d16_d0 ;
-   output Iout1_d_d28_d0 ;
-   output Iout2_d_d3_d1 ;
-   output Iout2_d_d12_d1 ;
-   output Iout1_d_d6_d1 ;
-   output Iout1_d_d4_d1 ;
-   output Iout1_d_d25_d0 ;
-   output Iout1_d_d6_d0 ;
-   wire Iin_d_d23_d0 ;
-   wire Iin_d_d4_d1 ;
-   output Iout2_d_d14_d1 ;
-   wire Iin_d_d15_d0 ;
-   output Iout2_d_d20_d1 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d8_d0 ;
-   output Iout1_d_d29_d0 ;
-   output Iout1_d_d14_d0 ;
-   output Iout2_d_d10_d0 ;
-   output Iout1_d_d24_d1 ;
-   wire Iin_d_d30_d0 ;
-   output Iout2_d_d14_d0 ;
-   output Iout2_d_d21_d1 ;
-   output Iout2_d_d24_d0 ;
-   output Iout2_d_d25_d0 ;
-   output Iout2_d_d17_d1 ;
-   output Iout2_d_d18_d1 ;
-   wire Iin_d_d19_d1 ;
-   wire Iin_d_d22_d1 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d22_d0 ;
-   output Iout1_d_d21_d0 ;
-   output Iin_v ;
-   output Iout2_d_d1_d1 ;
-   wire Iin_d_d14_d1 ;
-   wire Iin_d_d15_d1 ;
-   wire Iin_d_d26_d1 ;
-   output Iout1_d_d1_d1 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d5_d1 ;
-   output Iout2_d_d13_d1 ;
-   output Iout1_d_d13_d0 ;
-   output Iout1_d_d20_d1 ;
-   output Iin_a ;
-   output Iout1_d_d22_d1 ;
-   output Iout2_d_d28_d0 ;
-   wire Iin_d_d21_d0 ;
-   output Iout1_d_d17_d1 ;
-   output Iout1_d_d3_d0 ;
-   wire Iout2_v ;
+   wire Iin_d_d17_d1 ;
    wire Iin_d_d2_d1 ;
-   output Iout2_d_d15_d1 ;
-   output Iout2_d_d27_d1 ;
-   wire Iin_d_d7_d0 ;
-   output Iout1_d_d11_d1 ;
-   wire _out1_a_B ;
-   wire _c_v ;
-   output Iout2_d_d28_d1 ;
-   output Iout2_d_d2_d0 ;
-   output Iout2_d_d13_d0 ;
+   output Iout2_d_d7_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d0_d0 ;
+   output Iout2_d_d1_d1 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d24_d1 ;
+   output Iout1_d_d10_d1 ;
+   output Iout1_d_d30_d0 ;
+   wire Iin_d_d9_d0 ;
+   wire Iout1_a_B_buf_out0 ;
+   output Iout2_d_d10_d0 ;
+   wire Iin_d_d13_d0 ;
+   output Iout2_d_d20_d0 ;
+   output Iout2_d_d21_d1 ;
    wire Iin_d_d29_d1 ;
-   output Iout2_d_d1_d0 ;
+   output Iout2_d_d18_d0 ;
+   output Iout1_d_d3_d1 ;
+   wire reset_B;
+   wire Iin_d_d7_d1 ;
+   output Iout2_d_d24_d0 ;
+   output Iout1_d_d27_d0 ;
+   output Iout1_d_d2_d0 ;
+   output Iout1_d_d15_d0 ;
+   output Iin_a ;
+   output Iout2_d_d27_d1 ;
+   wire Iin_d_d27_d1 ;
+   output Iout2_d_d6_d0 ;
+   output Iout2_d_d11_d0 ;
+   output Iout1_d_d0_d1 ;
+   wire Iin_d_d8_d1 ;
+   output Iout2_d_d13_d0 ;
+   output Iout1_d_d25_d1 ;
+   output Iout1_d_d7_d1 ;
+   output Iout2_d_d14_d0 ;
+   wire Iin_d_d23_d0 ;
+   output Iout1_d_d22_d1 ;
+   output Iout1_d_d17_d1 ;
+   wire Icond_d_d0_d1 ;
+   wire Iout2_a_B_buf_out0 ;
+   output Iout2_d_d16_d1 ;
+   output Iout2_d_d25_d1 ;
+   output Iout1_d_d12_d1 ;
+   output Iout1_d_d9_d1 ;
+   wire Iin_d_d15_d1 ;
+   output Iout2_d_d22_d0 ;
+   wire Iin_d_d25_d0 ;
+   output Iout1_d_d21_d1 ;
+   output Iout1_d_d8_d0 ;
+   output Iout2_d_d12_d1 ;
+   output Iout2_d_d25_d0 ;
+   output Icond_v ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d21_d0 ;
+   output Iout1_d_d27_d1 ;
+   wire _in_v ;
    wire Iin_d_d12_d0 ;
-   output Iout2_d_d30_d0 ;
-   wire Iin_d_d4_d0 ;
-   wire _out_v ;
-   wire Iout1_v ;
+   output Iout1_d_d15_d1 ;
+   wire Iin_d_d17_d0 ;
+   output Iout1_d_d29_d1 ;
+   output Iout1_d_d18_d1 ;
+   wire _out1_a_B ;
+   wire _reset_BX ;
+   wire Iin_d_d14_d1 ;
+   output Iout1_d_d30_d1 ;
+   output Iout1_d_d4_d0 ;
+   wire Iin_d_d13_d1 ;
+   output Iout2_d_d4_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d30_d1 ;
+   wire _en ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d16_d0 ;
+   output Iout2_d_d21_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d16_d1 ;
+   output Iout1_d_d1_d1 ;
+   wire Iout_en_buf_out0 ;
+   wire Iin_d_d26_d1 ;
+   output Iout2_d_d1_d0 ;
+   wire Iin_d_d19_d0 ;
+   output Iout1_d_d19_d0 ;
+   wire Iout2_a ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d22_d1 ;
+   output Iout1_d_d13_d1 ;
+   output Iout1_d_d18_d0 ;
+   output Iout2_d_d14_d1 ;
+   output Iout2_d_d9_d0 ;
+   wire I_reset_BXX0 ;
+   wire Iin_d_d8_d0 ;
+   output Iout1_d_d24_d1 ;
+   output Iout1_d_d0_d0 ;
+   output Iout2_d_d15_d1 ;
+   wire Iin_d_d22_d0 ;
+   output Iout1_d_d23_d1 ;
+   output Iout1_d_d5_d1 ;
+   output Iout2_d_d24_d1 ;
+   output Iout2_d_d3_d0 ;
+   output Iout1_d_d21_d0 ;
+   output Iout1_d_d9_d0 ;
+   wire Iin_d_d28_d0 ;
+   wire Iin_d_d26_d0 ;
+   output Iout2_d_d8_d1 ;
+   wire Iin_d_d18_d0 ;
+   output Iout1_d_d26_d1 ;
+   output Iout1_d_d12_d0 ;
+   output Iout2_d_d9_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d20_d1 ;
+   output Iout2_d_d30_d1 ;
+   output Iout1_d_d19_d1 ;
+   output Iout2_d_d0_d1 ;
+   output Iout2_d_d17_d0 ;
+   output Iout2_d_d11_d1 ;
+   output Iout1_d_d26_d0 ;
+   output Iout1_d_d22_d0 ;
    wire I_c_t_buf0 ;
-   wire Iin_d_d1_d1 ;
+   output Iout2_d_d17_d1 ;
+   wire Iin_d_d1_d0 ;
    wire Iin_d_d3_d0 ;
+   output Iout1_d_d11_d0 ;
+   output Iout1_d_d3_d0 ;
+   output Iout1_d_d25_d0 ;
+   output Iout2_d_d22_d1 ;
+   wire Iin_d_d4_d0 ;
+   output Iout2_d_d23_d0 ;
+   wire Iin_d_d30_d0 ;
+   output Iout1_d_d16_d1 ;
+   output Iout1_d_d5_d0 ;
+   output Iout2_d_d26_d0 ;
+   output Iout1_d_d20_d1 ;
+   output Iout2_d_d30_d0 ;
+   output Iout2_d_d0_d0 ;
+   output Iout2_d_d29_d0 ;
+   wire Iin_d_d25_d1 ;
+   output Iout1_d_d6_d1 ;
+   output Iout1_d_d24_d0 ;
+   wire _out2_a_B ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d2_d0 ;
+   output Iout1_d_d13_d0 ;
+   output Iout1_d_d10_d0 ;
+   output Iout2_d_d5_d1 ;
+   output Iout2_d_d23_d1 ;
+   output Iout2_d_d28_d1 ;
+   wire Iin_d_d14_d0 ;
+   output Iout2_d_d16_d0 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d20_d0 ;
+   output Iout1_d_d8_d1 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout2_d_d29_d1 ;
+   wire Iin_d_d5_d0 ;
+   output Iout1_d_d28_d0 ;
+   output Iout1_d_d14_d0 ;
+   output Iout2_d_d3_d1 ;
    output Iout2_d_d15_d0 ;
-   output Iout1_d_d23_d0 ;
+   wire Icond_d_d0_d0 ;
+   wire Iout2_v ;
+   wire Iin_d_d0_d1 ;
+   output Iout1_d_d14_d1 ;
+   output Iout1_d_d7_d0 ;
+   wire I_c_f_buf0 ;
+   wire Iout1_a ;
+   output Iout2_d_d27_d0 ;
+   output Iout1_d_d20_d0 ;
+   wire Iout1_v ;
+   output Iout2_d_d7_d0 ;
    wire Iin_d_d27_d0 ;
    output Iout2_d_d6_d1 ;
-   output Iout2_d_d29_d1 ;
-   output Iout1_d_d24_d0 ;
-   output Iout1_d_d10_d0 ;
-   output Iout2_d_d16_d1 ;
-   output Iout2_d_d4_d0 ;
-   output Iout1_d_d3_d1 ;
-   output Iout1_d_d15_d0 ;
-   output Iout1_d_d12_d0 ;
-   output Iout2_d_d0_d0 ;
-   wire Iin_d_d0_d0 ;
-   wire Iin_d_d2_d0 ;
-   output Iout2_d_d11_d0 ;
-   wire Iin_d_d18_d0 ;
-   wire Iout2_a_B_buf_out0 ;
+   wire Iin_d_d11_d0 ;
+   output Iout1_d_d6_d0 ;
+   wire Iin_d_d28_d1 ;
+   output Iout2_d_d2_d0 ;
+   output Iout2_d_d5_d0 ;
+   output Iout2_d_d8_d0 ;
+   output Iout1_d_d11_d1 ;
+   wire _c_v ;
+   output Iout2_d_d2_d1 ;
+   wire Iin_d_d4_d1 ;
+   output Iout2_d_d10_d1 ;
+   output Iout1_d_d4_d1 ;
+   output Iout2_d_d19_d0 ;
+   output Iout1_d_d16_d0 ;
    output Iout2_d_d4_d1 ;
-   wire Iin_d_d17_d1 ;
-   output Iout2_d_d7_d0 ;
-   output Iout1_d_d25_d1 ;
-   output Iout1_d_d10_d1 ;
-   output Iout2_d_d0_d1 ;
-   output Iout2_d_d7_d1 ;
+   wire Iin_d_d18_d1 ;
+   output Iout2_d_d20_d1 ;
+   output Iout2_d_d26_d1 ;
+   output Iout1_d_d28_d1 ;
+   output Iout1_d_d2_d1 ;
+   output Iout1_d_d17_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout2_d_d19_d1 ;
+   wire Iin_d_d6_d0 ;
+   output Iout1_d_d29_d0 ;
+   output Iin_v ;
+   wire _out_v ;
+   wire Iin_d_d23_d1 ;
+   output Iout2_d_d18_d1 ;
+   output Iout2_d_d12_d0 ;
+   output Iout1_d_d23_d0 ;
+   output Iout2_d_d28_d0 ;
+   output Iout2_d_d13_d1 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4/netlist/verilog.v

@@ -135,144 +135,144 @@ module tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4(Iin_d_d0_d0 , Iin_d_d
    input cond;
 
 // -- signals ---
-   output Iout_d_d26_d0 ;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d19_d1 ;
-   wire _drop ;
-   wire Iin_d_d15_d1 ;
-   output Iout_d_d23_d1 ;
-   wire Iin_d_d22_d0 ;
-   wire Iin_d_d31_d0 ;
-   output Iout_d_d15_d1 ;
-   output Iout_d_d25_d1 ;
-   wire Iin_d_d1_d0 ;
-   output Iout_d_d31_d0 ;
-   wire Iin_d_d10_d0 ;
-   wire Iin_d_d9_d1 ;
-   output Iout_d_d3_d0 ;
-   wire Iin_d_d7_d0 ;
-   output Iout_d_d5_d1 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d19_d0 ;
-   output Iout_d_d15_d0 ;
-   output Iout_d_d16_d0 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d17_d1 ;
-   wire Iin_d_d31_d1 ;
-   wire Iand_f31_b ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d24_d0 ;
-   wire Iin_d_d14_d1 ;
-   wire Iin_d_d5_d1 ;
-   output Iout_d_d10_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Iin_d_d30_d1 ;
-   output Iout_d_d6_d0 ;
+   output Iout_d_d11_d1 ;
    wire Iin_d_d4_d1 ;
-   output Iout_d_d13_d1 ;
-   output Iout_d_d5_d0 ;
-   output Iout_d_d12_d0 ;
-   wire Iin_d_d12_d0 ;
-   wire Iin_d_d26_d0 ;
    output Iout_d_d2_d0 ;
    output Iout_d_d0_d1 ;
-   output Iout_d_d14_d0 ;
-   output Iout_d_d4_d1 ;
-   output Iout_d_d23_d0 ;
-   output Iout_d_d27_d0 ;
-   output Iout_d_d28_d0 ;
-   output Iout_d_d11_d1 ;
-   wire Iin_d_d21_d1 ;
-   output Iout_d_d8_d1 ;
-   output Iout_d_d17_d0 ;
-   wire Iin_d_d23_d1 ;
-   wire cond;
-   wire Iin_d_d21_d0 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d5_d0 ;
-   output Iout_d_d13_d0 ;
-   output Iout_d_d24_d0 ;
-   output Iout_d_d22_d1 ;
-   output Iout_d_d9_d0 ;
-   output Iout_d_d19_d0 ;
-   output Iout_d_d20_d0 ;
-   wire Iin_d_d22_d1 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d1_d1 ;
-   output Iout_d_d3_d1 ;
-   wire Ivt_out ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d29_d0 ;
-   output Iout_d_d24_d1 ;
-   wire Iin_d_d8_d0 ;
-   wire Ior2_y ;
-   wire Iout_a ;
-   wire Iin_d_d13_d0 ;
-   wire Iin_d_d30_d0 ;
-   output Iout_d_d21_d1 ;
-   wire Iin_d_d27_d1 ;
+   output Iout_d_d9_d1 ;
    output Iout_d_d19_d1 ;
-   wire Iin_d_d12_d1 ;
-   output Iout_d_d12_d1 ;
-   output Iin_v ;
-   output Iout_d_d31_d1 ;
-   wire Iin_d_d28_d1 ;
-   output Iout_d_d0_d0 ;
-   output Iout_d_d1_d0 ;
-   wire Iin_d_d2_d0 ;
-   wire Iin_d_d17_d0 ;
-   output Iout_d_d29_d0 ;
-   wire Iin_d_d28_d0 ;
-   output Iout_d_d18_d1 ;
-   wire Iin_d_d9_d0 ;
+   wire Iin_d_d24_d1 ;
    output Iout_d_d30_d0 ;
-   wire Iin_d_d8_d1 ;
-   output Iout_d_d26_d1 ;
-   output Iout_d_d4_d0 ;
-   output Iout_d_d14_d1 ;
-   output Iout_d_d2_d1 ;
+   wire _drop ;
+   output Iout_d_d31_d0 ;
+   wire Iin_d_d31_d1 ;
+   output Iout_d_d23_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d10_d0 ;
    wire Iin_d_d26_d1 ;
-   wire Iin_d_d25_d0 ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d16_d1 ;
-   output Iout_d_d27_d1 ;
-   wire Iin_d_d0_d0 ;
-   output Iout_d_d6_d1 ;
-   wire Ior2_b ;
-   output Iout_d_d22_d0 ;
-   wire _in_vX ;
-   wire Iin_d_d13_d1 ;
-   output Iout_d_d1_d1 ;
-   output Iout_d_d18_d0 ;
-   wire Iin_d_d3_d1 ;
-   output Iout_d_d10_d0 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d27_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d1_d0 ;
    output Iout_d_d21_d0 ;
    wire Iin_d_d23_d0 ;
-   wire Iin_d_d2_d1 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d17_d1 ;
-   wire Iin_d_d20_d1 ;
-   wire Iin_d_d29_d1 ;
-   output Iout_d_d28_d1 ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d8_d0 ;
-   wire Iin_d_d18_d0 ;
-   output Iout_d_d30_d1 ;
-   output Iout_d_d11_d0 ;
-   wire Iin_d_d27_d0 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d16_d0 ;
-   output Iout_d_d20_d1 ;
-   wire Iin_d_d10_d1 ;
-   output Iout_d_d16_d1 ;
-   wire Iin_d_d25_d1 ;
-   output Iin_a ;
-   output Iout_d_d29_d1 ;
-   wire Iin_d_d15_d0 ;
+   wire Iin_d_d8_d1 ;
+   output Iout_d_d14_d1 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d17_d1 ;
+   output Iout_d_d22_d1 ;
    output Iout_d_d7_d0 ;
-   wire Iin_d_d20_d0 ;
+   output Iout_d_d12_d1 ;
+   wire Iin_d_d22_d0 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d22_d0 ;
+   output Iout_d_d23_d0 ;
+   wire Iout_a ;
+   wire Iin_d_d18_d1 ;
+   wire _in_vX ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d14_d0 ;
    output Iout_d_d25_d0 ;
+   output Iout_d_d6_d0 ;
+   wire Iin_d_d18_d0 ;
+   output Iout_d_d28_d1 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d7_d0 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d29_d0 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d15_d1 ;
+   output Iout_d_d20_d1 ;
+   wire Ior2_b ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d24_d0 ;
+   wire Iin_d_d25_d0 ;
+   output Iin_a ;
+   output Iout_d_d5_d1 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d28_d0 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d25_d1 ;
+   output Iout_d_d26_d1 ;
+   output Iout_d_d0_d0 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d11_d1 ;
+   output Iout_d_d27_d1 ;
+   output Iout_d_d30_d1 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d18_d0 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Iin_d_d0_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d18_d1 ;
+   wire Ivt_out ;
+   output Iin_v ;
+   output Iout_d_d4_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d28_d1 ;
+   output Iout_d_d16_d1 ;
+   wire Iin_d_d30_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire Ior2_y ;
+   wire Iin_d_d11_d0 ;
    output Iout_d_d7_d1 ;
+   output Iout_d_d13_d1 ;
+   wire Iin_d_d13_d0 ;
+   output Iout_d_d6_d1 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d6_d0 ;
+   output Iout_d_d24_d0 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d19_d0 ;
+   output Iout_d_d2_d1 ;
+   wire Iin_d_d27_d1 ;
+   output Iout_d_d31_d1 ;
+   wire Iin_d_d16_d0 ;
+   output Iout_d_d4_d1 ;
+   wire Iand_f31_b ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d10_d0 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d30_d1 ;
+   output Iout_d_d8_d1 ;
+   wire cond;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d9_d0 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d21_d1 ;
+   wire Iin_d_d3_d0 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d19_d0 ;
+   wire Iin_d_d29_d0 ;
+   wire Iin_d_d13_d1 ;
+   output Iout_d_d26_d0 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d9_d0 ;
+   output Iout_d_d24_d1 ;
+   output Iout_d_d16_d0 ;
+   output Iout_d_d17_d0 ;
+   wire Iin_d_d5_d1 ;
+   wire Iin_d_d16_d1 ;
+   wire Iin_d_d29_d1 ;
+   output Iout_d_d15_d0 ;
+   output Iout_d_d28_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d31_d0 ;
 
 // --- instances
 BUF_X4 Iin_v_buf  (.y(_in_vX), .a(Ivt_out ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4/netlist/verilog.v

@@ -16,28 +16,28 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4(Iin0 , Iin1 , Iin2 ,
    input Isupply_vss ;
 
 // -- signals ---
+   wire Isupply_vss ;
    wire I_inX3 ;
    wire I_inX1 ;
-   wire Iin2 ;
-   wire Iin4 ;
-   output Iout_d1_d1 ;
-   wire Iin1 ;
-   wire Itielo2_y ;
-   wire Itielo1_y ;
-   wire I_inX4 ;
    wire Iin5 ;
+   output Iout_d0_d1 ;
+   wire Iin0 ;
+   wire I_inX2 ;
+   wire I_inX4 ;
+   wire Iin4 ;
+   output Iout_d2_d0 ;
+   output Iout_d0_d0 ;
+   wire Itielo1_y ;
+   wire Itielo0_y ;
+   wire Iin1 ;
+   output Iout_d1_d1 ;
+   wire Iin3 ;
    wire I_inX0 ;
    output Iout_d2_d1 ;
-   output Iout_d2_d0 ;
-   output Iout_d1_d0 ;
-   output Iout_d0_d1 ;
-   wire Itielo0_y ;
    wire I_inX5 ;
-   output Iout_d0_d0 ;
-   wire I_inX2 ;
-   wire Iin0 ;
-   wire Isupply_vss ;
-   wire Iin3 ;
+   wire Iin2 ;
+   output Iout_d1_d0 ;
+   wire Itielo2_y ;
 
 // --- instances
 TIELO_X1 Itielo0  (.y(Itielo0_y ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4/netlist/verilog.v

@@ -27,49 +27,49 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4(Iin0 , Iin1 , Iin2
    input Isupply_vss ;
 
 // -- signals ---
-   wire Iin11 ;
    wire I_inX9 ;
-   wire Iin14 ;
-   output Iout_d2_d1 ;
-   output Iout_d1_d1 ;
-   wire Itielo2_y ;
-   wire I_inX6 ;
-   wire Iin10 ;
-   wire I_inX12 ;
-   wire I_inX4 ;
-   wire I_inX14 ;
-   wire Iin1 ;
-   wire Itielo3_y ;
-   wire Itielo0_y ;
-   wire I_inX1 ;
-   wire I_inX11 ;
-   wire I_inX3 ;
-   wire Iin7 ;
-   wire Iin6 ;
-   wire Iin9 ;
-   wire Iin4 ;
-   wire Iin2 ;
    wire I_inX7 ;
-   output Iout_d0_d1 ;
-   wire Itielo1_y ;
-   wire Iin3 ;
-   wire Iin0 ;
-   wire I_inX5 ;
-   wire I_inX2 ;
-   wire Iin8 ;
+   wire Itielo3_y ;
+   wire Iin14 ;
    output Iout_d1_d0 ;
-   wire Iin5 ;
-   wire I_inX13 ;
-   wire Iin13 ;
-   wire I_inX0 ;
-   wire Isupply_vss ;
-   output Iout_d3_d0 ;
-   output Iout_d3_d1 ;
-   wire I_inX10 ;
    wire I_inX8 ;
-   wire Iin12 ;
-   output Iout_d2_d0 ;
+   wire Itielo1_y ;
+   wire Iin11 ;
    output Iout_d0_d0 ;
+   wire I_inX0 ;
+   wire Iin7 ;
+   output Iout_d3_d0 ;
+   output Iout_d2_d0 ;
+   output Iout_d3_d1 ;
+   output Iout_d2_d1 ;
+   wire Itielo0_y ;
+   wire Iin10 ;
+   wire Iin3 ;
+   wire Iin4 ;
+   wire I_inX10 ;
+   wire Iin0 ;
+   wire I_inX1 ;
+   wire Iin8 ;
+   wire I_inX14 ;
+   wire Iin6 ;
+   wire Iin2 ;
+   wire Iin13 ;
+   output Iout_d0_d1 ;
+   wire Itielo2_y ;
+   wire I_inX13 ;
+   wire Iin1 ;
+   wire I_inX4 ;
+   wire I_inX6 ;
+   wire Iin9 ;
+   wire Iin5 ;
+   output Iout_d1_d1 ;
+   wire I_inX2 ;
+   wire I_inX5 ;
+   wire I_inX3 ;
+   wire I_inX12 ;
+   wire Isupply_vss ;
+   wire I_inX11 ;
+   wire Iin12 ;
 
 // --- instances
 TIELO_X1 Itielo0  (.y(Itielo0_y ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4/netlist/verilog.v

@@ -121,125 +121,125 @@ module tmpl_0_0dataflow__neuro_0_0dummy__neuron__block_358_4(Isynapses0_d_d0 , I
    input Ineuron_a ;
 
 // -- signals ---
-   output Isynapses53_a ;
-   wire Isynapses47_d_d0 ;
-   wire Isynapses42_d_d0 ;
-   wire Isynapses39_d_d0 ;
-   wire Isynapses30_d_d0 ;
-   output Isynapses42_a ;
-   output Isynapses35_a ;
-   output Isynapses3_a ;
-   output Isynapses49_a ;
-   wire Isynapses28_d_d0 ;
-   output Isynapses26_a ;
-   output Isynapses28_a ;
-   output Isynapses22_a ;
-   wire Isynapses0_d_d0 ;
-   wire Isynapses55_d_d0 ;
-   output Isynapses50_a ;
-   output Isynapses40_a ;
-   wire Isynapses26_d_d0 ;
-   wire Isynapses10_d_d0 ;
-   wire Isynapses5_d_d0 ;
-   wire Inrn_ack_buf_y ;
-   wire Isynapses38_d_d0 ;
-   output Isynapses20_a ;
-   output Isynapses1_a ;
-   output Isynapses52_a ;
-   wire Isynapses49_d_d0 ;
-   wire Isynapses43_d_d0 ;
-   output Isynapses41_a ;
-   output Isynapses31_a ;
-   output Isynapses14_a ;
-   output Isynapses36_a ;
-   output Isynapses15_a ;
-   wire Isynapses8_d_d0 ;
-   wire Isynapses1_d_d0 ;
-   wire Isynapses53_d_d0 ;
-   output Isynapses43_a ;
-   output Isynapses39_a ;
-   output Isynapses8_a ;
-   wire Isynapses54_d_d0 ;
-   wire Isynapses51_d_d0 ;
-   wire Isynapses4_d_d0 ;
-   output Isynapses55_a ;
-   output Isynapses51_a ;
-   output Isynapses44_a ;
-   wire Isynapses40_d_d0 ;
-   wire Isynapses36_d_d0 ;
-   wire Isynapses35_d_d0 ;
-   wire Isynapses41_d_d0 ;
-   wire Isynapses31_d_d0 ;
-   output Isynapses23_a ;
-   output Isynapses12_a ;
-   output Isynapses10_a ;
-   output Isynapses9_a ;
-   wire Isynapses7_d_d0 ;
-   wire Isynapses44_d_d0 ;
-   wire Isynapses29_d_d0 ;
-   output Isynapses18_a ;
-   wire Isynapses34_d_d0 ;
-   wire Isynapses16_d_d0 ;
-   wire Isynapses57_d_d0 ;
-   output Isynapses30_a ;
-   output Isynapses21_a ;
-   output Isynapses0_a ;
-   wire Isynapses25_d_d0 ;
-   wire Isynapses19_d_d0 ;
-   output Isynapses5_a ;
-   wire Isynapses48_d_d0 ;
-   output Isynapses47_a ;
-   wire Isynapses13_d_d0 ;
-   output Isynapses13_a ;
    output Isynapses46_a ;
-   wire Isynapses56_d_d0 ;
-   wire Isynapses17_d_d0 ;
-   wire Isynapses12_d_d0 ;
-   wire Isynapses24_d_d0 ;
-   wire Isynapses11_d_d0 ;
-   wire Isynapses9_d_d0 ;
-   output Isynapses7_a ;
-   output Isynapses45_a ;
-   wire Isynapses27_d_d0 ;
-   wire Isynapses20_d_d0 ;
-   wire Isynapses52_d_d0 ;
-   wire Isynapses45_d_d0 ;
    output Isynapses11_a ;
-   output Isynapses48_a ;
-   output Isynapses56_a ;
-   wire Isynapses46_d_d0 ;
-   output Isynapses32_a ;
-   output Isynapses2_a ;
-   output Isynapses38_a ;
-   wire Isynapses33_d_d0 ;
-   wire Isynapses32_d_d0 ;
-   wire Isynapses23_d_d0 ;
-   output Isynapses16_a ;
-   output Isynapses4_a ;
-   wire Ineuron_a ;
-   output Ineuron_d_d0 ;
-   output Isynapses27_a ;
-   output Isynapses24_a ;
-   wire Isynapses15_d_d0 ;
-   wire Isynapses14_d_d0 ;
-   wire Isynapses2_d_d0 ;
+   wire Isynapses53_d_d0 ;
+   output Isynapses30_a ;
+   output Isynapses12_a ;
+   output Isynapses41_a ;
+   wire Isynapses39_d_d0 ;
+   wire Isynapses31_d_d0 ;
+   wire Isynapses55_d_d0 ;
    wire Isynapses50_d_d0 ;
-   output Isynapses34_a ;
-   output Isynapses33_a ;
-   wire Isynapses21_d_d0 ;
-   output Isynapses19_a ;
-   output Isynapses6_a ;
-   output Isynapses54_a ;
-   output Isynapses25_a ;
-   output Isynapses37_a ;
-   wire Isynapses22_d_d0 ;
-   output Isynapses57_a ;
-   wire Isynapses37_d_d0 ;
-   output Isynapses29_a ;
-   wire Isynapses18_d_d0 ;
-   output Isynapses17_a ;
+   output Isynapses21_a ;
+   output Isynapses20_a ;
    wire Isynapses6_d_d0 ;
    wire Isynapses3_d_d0 ;
+   wire Isynapses41_d_d0 ;
+   output Isynapses40_a ;
+   output Isynapses37_a ;
+   output Isynapses35_a ;
+   output Isynapses3_a ;
+   output Isynapses53_a ;
+   output Isynapses45_a ;
+   output Isynapses44_a ;
+   wire Isynapses30_d_d0 ;
+   wire Isynapses19_d_d0 ;
+   wire Isynapses2_d_d0 ;
+   wire Isynapses47_d_d0 ;
+   wire Isynapses35_d_d0 ;
+   output Isynapses32_a ;
+   output Isynapses17_a ;
+   wire Isynapses8_d_d0 ;
+   output Isynapses0_a ;
+   wire Isynapses38_d_d0 ;
+   wire Isynapses26_d_d0 ;
+   output Isynapses50_a ;
+   wire Isynapses43_d_d0 ;
+   output Isynapses2_a ;
+   output Isynapses48_a ;
+   wire Isynapses21_d_d0 ;
+   wire Isynapses13_d_d0 ;
+   output Isynapses18_a ;
+   wire Isynapses4_d_d0 ;
+   wire Isynapses54_d_d0 ;
+   wire Isynapses52_d_d0 ;
+   wire Isynapses42_d_d0 ;
+   wire Isynapses5_d_d0 ;
+   output Isynapses14_a ;
+   output Isynapses55_a ;
+   output Isynapses43_a ;
+   wire Isynapses20_d_d0 ;
+   output Isynapses7_a ;
+   wire Isynapses44_d_d0 ;
+   output Isynapses49_a ;
+   output Isynapses42_a ;
+   wire Isynapses16_d_d0 ;
+   wire Isynapses10_d_d0 ;
+   output Isynapses29_a ;
+   wire Isynapses24_d_d0 ;
+   wire Isynapses56_d_d0 ;
+   wire Isynapses18_d_d0 ;
+   wire Isynapses14_d_d0 ;
+   wire Isynapses0_d_d0 ;
+   output Isynapses57_a ;
+   output Isynapses54_a ;
+   wire Isynapses28_d_d0 ;
+   wire Isynapses23_d_d0 ;
+   output Isynapses5_a ;
+   wire Isynapses48_d_d0 ;
+   wire Isynapses46_d_d0 ;
+   wire Isynapses33_d_d0 ;
+   output Isynapses19_a ;
+   wire Isynapses15_d_d0 ;
+   wire Isynapses1_d_d0 ;
+   output Isynapses47_a ;
+   wire Isynapses34_d_d0 ;
+   wire Isynapses17_d_d0 ;
+   output Isynapses15_a ;
+   output Isynapses1_a ;
+   output Isynapses34_a ;
+   wire Isynapses11_d_d0 ;
+   wire Isynapses32_d_d0 ;
+   wire Isynapses12_d_d0 ;
+   wire Isynapses7_d_d0 ;
+   wire Inrn_ack_buf_y ;
+   wire Isynapses45_d_d0 ;
+   output Isynapses38_a ;
+   output Isynapses33_a ;
+   wire Isynapses29_d_d0 ;
+   wire Isynapses25_d_d0 ;
+   wire Ineuron_a ;
+   wire Isynapses57_d_d0 ;
+   output Isynapses56_a ;
+   output Isynapses52_a ;
+   wire Isynapses36_d_d0 ;
+   output Isynapses23_a ;
+   output Isynapses6_a ;
+   output Isynapses4_a ;
+   wire Isynapses51_d_d0 ;
+   wire Isynapses49_d_d0 ;
+   output Isynapses39_a ;
+   wire Isynapses27_d_d0 ;
+   output Isynapses27_a ;
+   wire Isynapses22_d_d0 ;
+   output Isynapses36_a ;
+   output Isynapses22_a ;
+   output Isynapses13_a ;
+   output Isynapses8_a ;
+   output Isynapses31_a ;
+   output Isynapses25_a ;
+   output Isynapses24_a ;
+   output Isynapses16_a ;
+   output Isynapses26_a ;
+   output Isynapses10_a ;
+   output Isynapses9_a ;
+   output Ineuron_d_d0 ;
+   wire Isynapses40_d_d0 ;
+   wire Isynapses37_d_d0 ;
+   output Isynapses28_a ;
+   output Isynapses51_a ;
+   wire Isynapses9_d_d0 ;
 
 // --- instances
 BUF_X12 Inrn_ack_buf  (.y(Inrn_ack_buf_y ), .a(Ineuron_a ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4/netlist/verilog.v

@@ -106,174 +106,174 @@ module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4(Iinx0_d_d0
    input reset_B;
 
 // -- signals ---
-   wire Idly_x2_in ;
-   wire Ipd_x14_reset_B ;
-   wire Iout_v ;
-   output Ito_pd_x12_d_d0 ;
-   wire Idly_x1_out ;
-   wire Idly_x0_in ;
-   wire Idly_x3_in ;
-   wire Ia_x_Cel_c1 ;
-   output Iinx13_a ;
-   output Iinx14_a ;
-   wire IXenc_out_d3_d0 ;
-   wire Idly_x5_out ;
-   output Iinx11_a ;
-   wire IYenc_out_d0_d0 ;
-   wire Iinx6_d_d0 ;
-   wire Idly_x11_in ;
-   wire Idly_x14_in ;
-   output Iinx2_a ;
-   wire IXenc_out_d2_d0 ;
-   wire Idly_y3_out ;
-   wire Ito_pd_x13_a ;
-   output Iiny1_a ;
-   wire Ito_pd_y4_a ;
-   output Iinx5_a ;
-   wire Iinx12_d_d0 ;
-   wire Idly_x4_out ;
-   output Iout_d_d1_d1 ;
-   output Iinx8_a ;
-   output Iinx9_a ;
-   output Ito_pd_x5_d_d0 ;
-   wire Iinx14_d_d0 ;
-   wire Ito_pd_x8_a ;
-   wire Ito_pd_y0_a ;
-   wire Isupply_vdd ;
-   output Iiny4_a ;
-   wire IXenc_out_d1_d0 ;
-   output Ito_pd_y0_d_d0 ;
-   wire IYenc_out_d1_d1 ;
-   wire Idly_y0_out ;
-   wire Idly_y1_in ;
-   wire Ito_pd_x3_a ;
-   output Ito_pd_y4_d_d0 ;
-   wire Idly_x10_out ;
-   wire Idly_x13_in ;
-   wire Ito_pd_x4_a ;
-   wire Iinx3_d_d0 ;
-   wire reset_B;
-   output Iinx1_a ;
-   wire Ito_pd_x0_a ;
-   wire Ito_pd_y1_a ;
-   wire IYenc_out_d2_d0 ;
-   wire Ito_pd_x2_a ;
-   output Iout_d_d2_d1 ;
-   output Iout_d_d5_d0 ;
-   wire Idly_x7_in ;
-   wire Idly_y0_in ;
-   wire Idly_y2_in ;
-   wire Iinx2_d_d0 ;
-   output Iinx3_a ;
-   output Ito_pd_x9_d_d0 ;
-   wire Idly_y4_out ;
-   wire Ito_pd_y3_a ;
-   wire Ito_pd_x11_a ;
-   output Iout_d_d2_d0 ;
-   output Iinx12_a ;
-   wire Isupply_vss ;
-   output Ito_pd_x2_d_d0 ;
-   output Ito_pd_y2_d_d0 ;
-   wire Ito_pd_x12_a ;
-   wire Iinv_buf_a ;
-   output Iinx10_a ;
-   output Ito_pd_x8_d_d0 ;
-   output Ito_pd_x13_d_d0 ;
-   wire Idly_x0_out ;
-   wire IXenc_out_d2_d1 ;
-   output Ito_pd_x1_d_d0 ;
-   wire Iinx13_d_d0 ;
-   output Iinx4_a ;
-   wire Ito_pd_x5_a ;
-   wire IYenc_out_d1_d0 ;
-   wire IXenc_out_d3_d1 ;
-   wire Ito_pd_x1_a ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d6_d1 ;
-   wire IYenc_out_d0_d1 ;
-   wire Ito_pd_x6_a ;
-   wire Ipd_y5_reset_B ;
-   output Iout_d_d5_d1 ;
-   wire Idly_y4_in ;
-   output Iiny0_a ;
-   wire Iiny5_d_d0 ;
    wire Idly_x8_in ;
-   wire Idly_x6_out ;
+   wire Iinx9_d_d0 ;
+   wire Ito_pd_x11_a ;
+   wire Idly_x4_out ;
+   output Ito_pd_x1_d_d0 ;
+   wire Idly_x2_out ;
+   wire Ito_pd_x1_a ;
+   wire Ito_pd_x9_a ;
+   wire Ito_pd_x10_a ;
+   wire Ito_pd_x12_a ;
+   output Iout_d_d1_d0 ;
+   wire Iinx1_d_d0 ;
+   wire Idly_x9_in ;
+   wire IXenc_out_d3_d0 ;
+   wire Idly_y3_in ;
+   wire Ito_pd_y2_a ;
+   output Ito_pd_y5_d_d0 ;
+   wire Idly_y4_out ;
+   wire Iiny3_d_d0 ;
+   wire Iout_v ;
+   wire reset_B;
+   wire Idly_x12_out ;
+   wire Iinx10_d_d0 ;
+   output Iinx2_a ;
+   wire Idly_y0_out ;
    wire Idly_x14_out ;
-   wire Idly_x10_in ;
-   output Iout_d_d4_d0 ;
+   output Iiny3_a ;
    output Iout_d_d3_d0 ;
-   wire _r_x ;
+   wire IYenc_out_d1_d1 ;
+   wire Iinx7_d_d0 ;
+   wire IXenc_out_d1_d0 ;
+   wire Ito_pd_x4_a ;
+   wire Iinx8_d_d0 ;
+   wire Idly_y1_in ;
+   wire Ito_pd_x8_a ;
+   output Ito_pd_y2_d_d0 ;
+   wire Iinx0_d_d0 ;
+   wire Ia_x_Cel_c1 ;
+   wire IXenc_out_d2_d0 ;
+   wire Idly_x13_out ;
+   output Iiny5_a ;
+   output Iout_d_d1_d1 ;
+   wire Iinx5_d_d0 ;
+   wire Idly_x5_in ;
+   output Ito_pd_x5_d_d0 ;
+   output Ito_pd_x9_d_d0 ;
+   output Ito_pd_x14_d_d0 ;
+   output Ito_pd_y0_d_d0 ;
+   wire _a_x ;
+   wire Iinx11_d_d0 ;
+   output Iinx1_a ;
+   output Iinx12_a ;
+   wire Idly_y5_in ;
+   output Iout_d_d0_d1 ;
+   wire Iinx13_d_d0 ;
+   wire Iinv_buf_a ;
+   wire Idly_x8_out ;
+   wire Iinx14_d_d0 ;
+   wire IXenc_out_d0_d1 ;
    output Iinx0_a ;
    wire Idly_y1_out ;
-   wire Ito_pd_x10_a ;
-   wire Iiny1_d_d0 ;
-   wire Iinx11_d_d0 ;
-   wire Iiny2_d_d0 ;
-   wire Iinx8_d_d0 ;
-   wire Iinx1_d_d0 ;
-   wire Iinx7_d_d0 ;
-   wire Idly_x13_out ;
-   output Iiny2_a ;
-   wire IYenc_out_d2_d1 ;
-   wire Iinx9_d_d0 ;
-   output Ito_pd_x11_d_d0 ;
-   wire Idly_x6_in ;
-   output Ito_pd_x6_d_d0 ;
-   wire Idly_y5_out ;
-   wire IXenc_out_d1_d1 ;
-   wire Iout_a ;
-   output Iout_d_d4_d1 ;
-   wire _a_x ;
-   wire Ito_pd_x9_a ;
-   wire Ito_pd_y2_a ;
-   wire Iiny4_d_d0 ;
-   output Iout_d_d0_d1 ;
-   wire IXenc_out_d0_d0 ;
-   wire Idly_x5_in ;
-   output Ito_pd_x3_d_d0 ;
-   output Ito_pd_y3_d_d0 ;
-   wire Iinx10_d_d0 ;
-   output Iout_d_d0_d0 ;
-   wire Ito_pd_y5_a ;
-   wire Idly_x12_in ;
-   output Ito_pd_x14_d_d0 ;
-   wire Idly_x2_out ;
-   wire Idly_x3_out ;
-   output Iout_d_d1_d0 ;
-   wire _a_y ;
-   wire IXenc_out_d0_d1 ;
-   wire Ito_pd_x7_a ;
-   output Iout_d_d3_d1 ;
-   wire Idly_x4_in ;
-   output Iinx6_a ;
-   output Iinx7_a ;
-   output Ito_pd_x7_d_d0 ;
+   wire Ito_pd_x13_a ;
    wire Idly_y2_out ;
-   wire Idly_x12_out ;
-   wire Iinx5_d_d0 ;
-   wire _r_y ;
-   wire Iinx0_d_d0 ;
-   wire Iinx4_d_d0 ;
-   wire Idly_y3_in ;
-   wire Idly_x8_out ;
-   wire Idly_x9_in ;
-   output Iiny5_a ;
-   wire Idly_y5_in ;
-   output Ito_pd_x0_d_d0 ;
-   output Ito_pd_x10_d_d0 ;
-   wire Idly_x9_out ;
-   output Ito_pd_y1_d_d0 ;
-   wire Ibuf_in_v ;
-   output Ito_pd_y5_d_d0 ;
-   wire Idly_x11_out ;
    wire Ito_pd_x14_a ;
-   wire Iiny3_d_d0 ;
-   wire Iiny0_d_d0 ;
-   wire Idly_x1_in ;
-   output Iiny3_a ;
-   output Ito_pd_x4_d_d0 ;
+   wire Iinx3_d_d0 ;
+   wire Idly_x4_in ;
+   wire Idly_y4_in ;
+   output Ito_pd_y4_d_d0 ;
+   output Iinx14_a ;
+   output Iout_d_d2_d0 ;
+   wire Idly_x12_in ;
+   wire Idly_y0_in ;
    wire Idly_x7_out ;
+   output Ito_pd_x11_d_d0 ;
+   wire Ipd_x14_reset_B ;
+   output Iinx11_a ;
+   output Ito_pd_x8_d_d0 ;
+   wire Ito_pd_x7_a ;
+   wire IYenc_out_d1_d0 ;
+   output Ito_pd_x0_d_d0 ;
+   wire Ito_pd_y4_a ;
+   wire Iinx6_d_d0 ;
+   wire IXenc_out_d2_d1 ;
+   wire Iiny1_d_d0 ;
+   wire Idly_x0_in ;
+   output Iinx5_a ;
+   wire Isupply_vdd ;
+   output Iiny4_a ;
+   output Iinx10_a ;
+   wire Iinx12_d_d0 ;
+   wire _r_y ;
+   wire Idly_x3_out ;
+   wire Iiny0_d_d0 ;
+   wire IYenc_out_d2_d0 ;
+   wire Idly_x2_in ;
+   wire IXenc_out_d3_d1 ;
+   output Iout_d_d2_d1 ;
+   wire IYenc_out_d2_d1 ;
+   wire IYenc_out_d0_d1 ;
+   wire Idly_y3_out ;
+   output Iinx13_a ;
+   output Ito_pd_x3_d_d0 ;
+   output Iout_d_d4_d1 ;
+   output Iinx3_a ;
+   output Iinx8_a ;
+   wire Idly_x10_out ;
+   wire Idly_x11_out ;
+   wire Idly_x1_in ;
+   wire IXenc_out_d1_d1 ;
+   output Ito_pd_x7_d_d0 ;
+   output Ito_pd_x12_d_d0 ;
+   wire Idly_y5_out ;
+   wire Isupply_vss ;
+   wire Ito_pd_y0_a ;
+   output Iiny0_a ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d5_d0 ;
+   output Ito_pd_x4_d_d0 ;
+   wire Idly_x6_out ;
+   wire IYenc_out_d0_d0 ;
+   wire Idly_x11_in ;
+   wire Ito_pd_x2_a ;
+   wire Ito_pd_x5_a ;
+   output Iinx6_a ;
+   output Ito_pd_y3_d_d0 ;
+   wire Iiny5_d_d0 ;
+   output Iout_d_d3_d1 ;
+   wire Ibuf_in_v ;
+   output Ito_pd_y1_d_d0 ;
+   output Iout_d_d5_d1 ;
+   wire Iinx4_d_d0 ;
+   wire Iiny4_d_d0 ;
+   wire Idly_x7_in ;
+   wire Idly_x14_in ;
+   wire Idly_x1_out ;
+   wire Ito_pd_x0_a ;
+   wire Idly_y2_in ;
+   wire Ito_pd_y3_a ;
+   output Iiny1_a ;
+   output Iout_d_d6_d1 ;
+   output Iinx4_a ;
+   output Ito_pd_x10_d_d0 ;
+   output Iout_d_d0_d0 ;
+   output Iiny2_a ;
+   output Iinx7_a ;
+   wire Ipd_y5_reset_B ;
+   wire Ito_pd_y1_a ;
+   wire Idly_x6_in ;
+   wire Ito_pd_y5_a ;
+   wire Idly_x9_out ;
+   wire Idly_x5_out ;
+   wire Iiny2_d_d0 ;
+   wire Idly_x3_in ;
+   wire _r_x ;
+   wire Ito_pd_x6_a ;
+   output Iout_d_d4_d0 ;
+   wire Iinx2_d_d0 ;
+   wire Idly_x13_in ;
+   wire Idly_x0_out ;
+   wire Iout_a ;
+   output Iinx9_a ;
+   output Ito_pd_x6_d_d0 ;
+   output Ito_pd_x13_d_d0 ;
+   wire _a_y ;
+   wire IXenc_out_d0_d0 ;
+   output Ito_pd_x2_d_d0 ;
+   wire Idly_x10_in ;
+   wire Ito_pd_x3_a ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0arbtree_315_4 IXarb  (.Iin0_d_d0 (Iinx0_d_d0 ), .Iin0_a (Idly_x0_in ), .Iin1_d_d0 (Iinx1_d_d0 ), .Iin1_a (Idly_x1_in ), .Iin2_d_d0 (Iinx2_d_d0 ), .Iin2_a (Idly_x2_in ), .Iin3_d_d0 (Iinx3_d_d0 ), .Iin3_a (Idly_x3_in ), .Iin4_d_d0 (Iinx4_d_d0 ), .Iin4_a (Idly_x4_in ), .Iin5_d_d0 (Iinx5_d_d0 ), .Iin5_a (Idly_x5_in ), .Iin6_d_d0 (Iinx6_d_d0 ), .Iin6_a (Idly_x6_in ), .Iin7_d_d0 (Iinx7_d_d0 ), .Iin7_a (Idly_x7_in ), .Iin8_d_d0 (Iinx8_d_d0 ), .Iin8_a (Idly_x8_in ), .Iin9_d_d0 (Iinx9_d_d0 ), .Iin9_a (Idly_x9_in ), .Iin10_d_d0 (Iinx10_d_d0 ), .Iin10_a (Idly_x10_in ), .Iin11_d_d0 (Iinx11_d_d0 ), .Iin11_a (Idly_x11_in ), .Iin12_d_d0 (Iinx12_d_d0 ), .Iin12_a (Idly_x12_in ), .Iin13_d_d0 (Iinx13_d_d0 ), .Iin13_a (Idly_x13_in ), .Iin14_d_d0 (Iinx14_d_d0 ), .Iin14_a (Idly_x14_in ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_313_73_4/netlist/verilog.v

@@ -60,121 +60,121 @@ module tmpl_0_0dataflow__neuro_0_0fifo_313_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
    input reset_B;
 
 // -- signals ---
-   wire Ififo_element2_in_d_d8_d1 ;
-   output Iout_d_d4_d0 ;
-   output Iout_d_d3_d1 ;
-   wire Ififo_element1_in_v ;
-   wire Ififo_element1_in_d_d2_d1 ;
-   wire Iin_d_d9_d0 ;
-   output Iout_d_d5_d0 ;
-   wire Ififo_element2_in_d_d2_d0 ;
-   wire Iin_d_d6_d1 ;
-   wire Iout_v ;
-   output Iout_d_d7_d1 ;
-   output Iout_d_d5_d1 ;
-   wire Ififo_element2_in_d_d6_d0 ;
-   wire Ififo_element1_in_d_d5_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout_d_d7_d0 ;
-   output Iout_d_d4_d1 ;
-   wire Ififo_element2_in_d_d5_d1 ;
-   wire Ififo_element2_in_d_d11_d1 ;
-   wire Ififo_element2_in_d_d10_d1 ;
-   wire Ififo_element1_in_d_d3_d1 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d1_d0 ;
-   output Iout_d_d12_d1 ;
-   wire Ififo_element2_in_d_d8_d0 ;
-   output Iout_d_d2_d0 ;
-   output Iout_d_d1_d1 ;
-   wire Ififo_element2_in_d_d12_d1 ;
-   wire Ififo_element1_in_d_d1_d0 ;
-   wire Ififo_element1_in_d_d0_d0 ;
-   wire Iin_d_d4_d0 ;
-   wire Ififo_element2_in_d_d7_d1 ;
-   wire Ififo_element2_in_d_d2_d1 ;
-   wire Ififo_element1_in_d_d7_d0 ;
-   output Iin_v ;
-   output Iin_a ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d2_d0 ;
-   output Iout_d_d6_d0 ;
-   wire Iin_d_d5_d0 ;
-   wire Ififo_element2_in_d_d9_d1 ;
    wire Ififo_element2_in_d_d0_d0 ;
-   wire Ififo_element1_in_d_d11_d0 ;
-   wire Ififo_element1_in_d_d10_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Ififo_element2_in_v ;
+   wire Ififo_element1_in_d_d1_d0 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d11_d1 ;
    wire Ififo_element1_in_d_d9_d0 ;
-   wire Ififo_element1_in_d_d10_d1 ;
    wire Iin_d_d10_d1 ;
-   wire Ififo_element2_in_d_d4_d1 ;
-   wire Ififo_element1_in_d_d4_d0 ;
-   wire Iin_d_d8_d1 ;
-   output Iout_d_d11_d0 ;
    wire Iin_d_d12_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire Ififo_element2_in_d_d3_d1 ;
-   wire Ififo_element1_in_d_d4_d1 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d_d2_d1 ;
+   wire Ififo_element2_in_d_d4_d1 ;
+   wire Ififo_element1_in_d_d11_d0 ;
+   wire Iin_d_d2_d0 ;
+   output Iout_d_d11_d0 ;
+   wire Iin_d_d0_d0 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d3_d1 ;
    wire Ififo_element1_in_d_d3_d0 ;
    wire Ififo_element1_in_d_d2_d0 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d0_d1 ;
-   output Iout_d_d0_d0 ;
-   wire Ififo_element2_in_d_d1_d1 ;
-   wire Ififo_element2_in_d_d9_d0 ;
-   wire Ififo_element2_in_d_d6_d1 ;
-   output Iout_d_d9_d0 ;
-   output Iout_d_d3_d0 ;
-   wire Ififo_element1_in_d_d12_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire Ififo_element1_in_d_d12_d1 ;
+   output Iout_d_d12_d1 ;
    wire Iin_d_d1_d1 ;
-   wire Ififo_element2_in_d_d3_d0 ;
-   wire Ififo_element2_in_d_d0_d1 ;
-   wire Ififo_element1_in_d_d8_d0 ;
+   wire Iout_v ;
+   output Iout_d_d8_d1 ;
+   wire Ififo_element2_in_d_d11_d1 ;
+   wire Ififo_element1_in_d_d10_d1 ;
+   wire Ififo_element1_in_d_d5_d1 ;
+   wire Iin_d_d3_d0 ;
+   output Iout_d_d6_d0 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d0_d0 ;
+   wire Ififo_element2_in_a ;
+   wire Ififo_element2_in_d_d10_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Ififo_element2_in_d_d9_d1 ;
+   wire I_reset_BXX2 ;
+   output Iout_d_d7_d0 ;
+   output Iout_d_d4_d1 ;
+   wire Ififo_element2_in_d_d12_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d12_d0 ;
+   wire Ififo_element2_in_d_d4_d0 ;
+   wire Ififo_element2_in_d_d1_d0 ;
+   wire Ififo_element1_in_d_d0_d1 ;
+   output Iin_a ;
+   wire Ififo_element2_in_d_d9_d0 ;
+   wire Ififo_element1_in_d_d12_d0 ;
+   wire Ififo_element1_in_d_d10_d0 ;
+   wire Ififo_element2_in_d_d12_d1 ;
+   wire Ififo_element2_in_d_d10_d1 ;
+   wire Ififo_element1_in_v ;
+   wire Ififo_element1_in_d_d4_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Ififo_element1_in_a ;
+   wire Ififo_element1_in_d_d9_d1 ;
+   wire Ififo_element1_in_d_d5_d0 ;
+   wire Ififo_element1_in_d_d2_d1 ;
    wire _reset_BX ;
+   wire Ififo_element2_in_d_d0_d1 ;
+   wire Iout_a ;
+   output Iout_d_d2_d0 ;
    wire Iin_d_d11_d0 ;
    wire Iin_d_d9_d1 ;
-   wire Iin_d_d6_d0 ;
-   wire Ififo_element2_in_d_d7_d0 ;
-   wire Ififo_element1_in_d_d5_d0 ;
-   wire Iin_d_d8_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d2_d1 ;
-   output Iout_d_d8_d1 ;
-   output Iout_d_d1_d0 ;
+   wire Ififo_element2_in_d_d6_d1 ;
+   wire Iin_d_d10_d0 ;
+   output Iout_d_d8_d0 ;
+   wire Iin_d_d4_d1 ;
+   output Iout_d_d10_d1 ;
+   output Iout_d_d1_d1 ;
+   wire Ififo_element2_in_d_d8_d1 ;
+   wire Ififo_element1_in_d_d4_d0 ;
+   output Iout_d_d7_d1 ;
+   wire Ififo_element2_in_d_d5_d0 ;
+   wire Ififo_element2_in_d_d3_d0 ;
+   wire Ififo_element2_in_d_d2_d1 ;
+   wire Ififo_element2_in_d_d2_d0 ;
+   wire Ififo_element2_in_d_d1_d1 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d4_d0 ;
+   wire Ififo_element2_in_d_d3_d1 ;
+   wire Ififo_element1_in_d_d7_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Ififo_element1_in_d_d8_d1 ;
    wire Ififo_element1_in_d_d6_d1 ;
    wire Ififo_element1_in_d_d6_d0 ;
-   wire Iin_d_d12_d1 ;
-   wire Iin_d_d4_d1 ;
-   output Iout_d_d11_d1 ;
-   wire Ififo_element1_in_d_d0_d1 ;
-   output Iout_d_d10_d1 ;
-   wire Ififo_element2_in_d_d10_d0 ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d2_d1 ;
-   wire Ififo_element1_in_a ;
-   wire Iin_d_d7_d0 ;
-   wire Iin_d_d0_d1 ;
-   output Iout_d_d12_d0 ;
-   output Iout_d_d8_d0 ;
-   output Iout_d_d6_d1 ;
-   wire Ififo_element2_in_v ;
-   wire Ififo_element2_in_a ;
-   wire Ififo_element2_in_d_d5_d0 ;
-   wire Ififo_element2_in_d_d4_d0 ;
-   output Iout_d_d10_d0 ;
-   wire Ififo_element2_in_d_d12_d0 ;
-   wire Ififo_element1_in_d_d9_d1 ;
-   wire Ififo_element1_in_d_d8_d1 ;
-   wire Ififo_element2_in_d_d11_d0 ;
-   wire Ififo_element1_in_d_d12_d1 ;
-   wire Ififo_element1_in_d_d11_d1 ;
-   wire Iout_a ;
-   wire Ififo_element2_in_d_d1_d0 ;
-   wire Ififo_element1_in_d_d7_d1 ;
    wire Ififo_element1_in_d_d1_d1 ;
-   wire Iin_d_d0_d0 ;
+   wire Ififo_element1_in_d_d0_d0 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d0_d1 ;
+   wire Ififo_element2_in_d_d7_d1 ;
+   wire Ififo_element2_in_d_d7_d0 ;
+   wire Ififo_element2_in_d_d6_d0 ;
+   output Iout_d_d10_d0 ;
+   output Iout_d_d5_d0 ;
+   wire Ififo_element1_in_d_d11_d1 ;
+   output Iin_v ;
+   output Iout_d_d9_d1 ;
+   wire Ififo_element2_in_d_d11_d0 ;
+   wire Ififo_element2_in_d_d8_d0 ;
+   wire Ififo_element2_in_d_d5_d1 ;
+   output Iout_d_d5_d1 ;
+   wire Ififo_element1_in_d_d8_d0 ;
+   wire Ififo_element1_in_d_d3_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Ififo_element1_in_d_d7_d0 ;
+   wire Iin_d_d12_d1 ;
+   wire Iin_d_d6_d0 ;
    wire reset_B;
-   wire I_reset_BXX2 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_331_73_4/netlist/verilog.v

@@ -132,265 +132,265 @@ module tmpl_0_0dataflow__neuro_0_0fifo_331_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
    input reset_B;
 
 // -- signals ---
+   wire Iin_d_d18_d1 ;
+   wire Ififo_element2_in_d_d30_d0 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d16_d1 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d27_d0 ;
+   wire Ififo_element2_in_d_d0_d0 ;
+   output Iout_d_d17_d0 ;
+   wire Ififo_element2_in_d_d10_d1 ;
+   wire Ififo_element2_in_d_d5_d0 ;
+   wire Ififo_element2_in_d_d12_d1 ;
+   wire Ififo_element1_in_d_d13_d1 ;
+   wire Ififo_element2_in_d_d27_d0 ;
+   wire Ififo_element1_in_d_d20_d0 ;
+   wire Ififo_element2_in_d_d3_d0 ;
+   wire Ififo_element2_in_d_d15_d0 ;
+   output Iout_d_d2_d0 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_d_d6_d1 ;
+   output Iout_d_d7_d1 ;
+   wire Ififo_element1_in_d_d22_d1 ;
+   wire Ififo_element1_in_d_d27_d0 ;
+   wire Ififo_element1_in_d_d26_d0 ;
+   wire Ififo_element1_in_d_d16_d0 ;
+   wire Ififo_element2_in_d_d14_d1 ;
+   wire Ififo_element1_in_d_d7_d0 ;
+   wire Iin_d_d11_d1 ;
+   output Iout_d_d3_d0 ;
+   wire Ififo_element1_in_d_d28_d0 ;
+   wire Ififo_element1_in_d_d12_d1 ;
+   wire Ififo_element1_in_d_d11_d1 ;
+   output Iout_d_d21_d1 ;
+   wire Ififo_element1_in_d_d10_d0 ;
+   wire Ififo_element1_in_d_d0_d0 ;
+   wire _reset_BX ;
+   wire Ififo_element1_in_d_d8_d1 ;
+   wire Ififo_element2_in_d_d11_d0 ;
+   wire Ififo_element1_in_d_d30_d1 ;
+   wire Ififo_element1_in_d_d21_d0 ;
+   wire Iin_d_d5_d1 ;
+   wire Ififo_element2_in_d_d13_d1 ;
+   output Iout_d_d27_d1 ;
+   wire Iin_d_d8_d0 ;
+   wire Ififo_element2_in_d_d13_d0 ;
+   wire Ififo_element2_in_d_d24_d1 ;
+   wire Iin_d_d13_d1 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d28_d0 ;
+   wire Ififo_element2_in_d_d25_d0 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d10_d1 ;
+   output Iout_d_d26_d0 ;
+   wire Iin_d_d4_d1 ;
+   wire Ififo_element2_in_d_d18_d1 ;
+   wire Iout_a ;
+   wire Iin_d_d29_d1 ;
+   wire Ififo_element2_in_d_d30_d1 ;
+   wire Ififo_element1_in_d_d29_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Ififo_element2_in_d_d27_d1 ;
+   output Iout_d_d15_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Ififo_element2_in_d_d11_d1 ;
+   output Iout_d_d0_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d8_d1 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d10_d0 ;
+   wire Ififo_element1_in_d_d5_d1 ;
+   wire Iin_d_d3_d1 ;
+   wire reset_B;
+   wire Ififo_element2_in_d_d28_d0 ;
+   wire Ififo_element1_in_d_d2_d1 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Ififo_element2_in_d_d3_d1 ;
+   output Iout_d_d3_d1 ;
+   output Iout_d_d23_d1 ;
+   wire Ififo_element1_in_d_d24_d0 ;
+   wire Ififo_element2_in_d_d9_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d22_d0 ;
+   wire Ififo_element2_in_d_d21_d1 ;
+   wire Ififo_element1_in_d_d26_d1 ;
+   wire Iin_d_d26_d0 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d20_d0 ;
+   wire Ififo_element1_in_d_d21_d1 ;
+   wire Ififo_element2_in_d_d8_d1 ;
+   wire Ififo_element2_in_d_d29_d1 ;
+   wire Iin_d_d17_d1 ;
+   wire Ififo_element2_in_d_d10_d0 ;
+   wire Ififo_element2_in_d_d22_d1 ;
+   output Iout_d_d15_d0 ;
+   wire Ififo_element1_in_d_d9_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Ififo_element1_in_d_d25_d1 ;
+   wire Ififo_element1_in_d_d19_d1 ;
+   wire Iin_d_d18_d0 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d11_d1 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d16_d0 ;
+   wire I_reset_BXX2 ;
+   output Iout_d_d20_d1 ;
+   wire Iin_d_d26_d1 ;
+   wire Ififo_element1_in_d_d13_d0 ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d14_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Ififo_element2_in_d_d25_d1 ;
+   wire Ififo_element2_in_d_d26_d0 ;
+   wire Ififo_element2_in_d_d8_d0 ;
+   wire Ififo_element2_in_d_d29_d0 ;
+   output Iout_d_d25_d0 ;
+   wire Ififo_element1_in_d_d17_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d13_d1 ;
+   wire Ififo_element1_in_d_d9_d1 ;
+   output Iout_d_d18_d0 ;
+   wire Ififo_element2_in_d_d18_d0 ;
+   wire Ififo_element1_in_d_d28_d1 ;
+   wire Ififo_element1_in_d_d12_d0 ;
+   wire Ififo_element2_in_d_d20_d0 ;
+   wire Iin_d_d15_d0 ;
+   wire Ififo_element2_in_d_d6_d1 ;
+   wire Ififo_element2_in_d_d15_d1 ;
+   wire Ififo_element2_in_d_d9_d1 ;
+   wire Ififo_element2_in_d_d16_d1 ;
+   output Iout_d_d11_d0 ;
+   wire Ififo_element2_in_d_d1_d1 ;
+   output Iout_d_d6_d0 ;
+   wire Ififo_element1_in_d_d6_d0 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d_d25_d1 ;
+   output Iout_d_d8_d1 ;
    wire Ififo_element1_in_d_d15_d1 ;
    wire Iin_d_d27_d1 ;
-   wire Ififo_element2_in_d_d6_d0 ;
-   output Iout_d_d24_d1 ;
-   wire Iin_d_d23_d0 ;
-   wire Ififo_element2_in_d_d1_d1 ;
-   output Iout_d_d3_d1 ;
-   output Iout_d_d5_d0 ;
-   wire Ififo_element1_in_d_d22_d0 ;
-   wire Iin_d_d4_d0 ;
-   wire Ififo_element2_in_d_d4_d1 ;
-   output Iout_d_d12_d0 ;
-   output Iout_d_d16_d1 ;
-   wire Ififo_element2_in_d_d21_d0 ;
-   output Iout_d_d2_d0 ;
-   wire Ififo_element1_in_d_d7_d0 ;
-   wire Ififo_element2_in_d_d11_d1 ;
-   wire Iin_d_d30_d0 ;
-   wire Iin_d_d29_d1 ;
-   wire Iin_d_d29_d0 ;
-   wire Ififo_element1_in_d_d19_d1 ;
-   wire Iin_d_d4_d1 ;
-   output Iout_d_d25_d1 ;
-   wire Iin_d_d15_d0 ;
-   wire Iin_d_d9_d1 ;
-   wire Iin_d_d26_d1 ;
-   wire Ififo_element1_in_d_d28_d1 ;
-   wire Ififo_element1_in_d_d23_d1 ;
-   wire Iin_d_d22_d0 ;
-   wire Ififo_element2_in_d_d1_d0 ;
-   wire Iin_d_d24_d1 ;
-   wire Ififo_element2_in_d_d12_d1 ;
-   wire Ififo_element2_in_d_d13_d1 ;
-   output Iout_d_d22_d1 ;
-   output Iin_a ;
-   wire Ififo_element2_in_d_d19_d0 ;
-   wire Ififo_element1_in_d_d13_d1 ;
-   wire Ififo_element1_in_d_d7_d1 ;
-   wire Ififo_element1_in_v ;
-   wire Ififo_element2_in_d_d16_d0 ;
-   wire Ififo_element1_in_d_d17_d1 ;
-   output Iout_d_d0_d0 ;
-   output Iout_d_d6_d1 ;
-   wire Iin_d_d18_d0 ;
-   wire Ififo_element1_in_d_d27_d0 ;
-   output Iout_d_d17_d0 ;
-   wire Ififo_element2_in_d_d9_d1 ;
-   wire Ififo_element1_in_d_d11_d1 ;
-   wire Iin_d_d6_d0 ;
-   output Iout_d_d20_d1 ;
-   output Iout_d_d28_d1 ;
-   wire Iin_d_d14_d0 ;
-   wire Ififo_element2_in_a ;
-   wire Iin_d_d12_d1 ;
-   output Iout_d_d27_d1 ;
-   wire Ififo_element1_in_d_d11_d0 ;
-   wire Ififo_element2_in_d_d10_d1 ;
-   wire Ififo_element2_in_d_d0_d1 ;
-   wire Ififo_element2_in_d_d28_d0 ;
-   wire Ififo_element1_in_d_d5_d0 ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d8_d1 ;
-   wire Ififo_element1_in_d_d6_d0 ;
-   wire Iin_d_d13_d1 ;
-   wire Ififo_element1_in_d_d9_d1 ;
-   wire Iin_d_d12_d0 ;
-   wire Ififo_element2_in_d_d0_d0 ;
-   wire Ififo_element2_in_d_d7_d0 ;
-   wire Ififo_element2_in_d_d19_d1 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d7_d0 ;
-   output Iout_d_d0_d1 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d1_d1 ;
-   output Iout_d_d1_d1 ;
-   output Iout_d_d12_d1 ;
-   wire Iout_a ;
-   wire Iin_d_d5_d1 ;
-   wire Ififo_element1_in_d_d3_d0 ;
-   wire Ififo_element1_in_a ;
-   wire Iin_d_d25_d0 ;
-   wire Ififo_element2_in_d_d5_d1 ;
-   wire Iin_d_d16_d1 ;
-   wire Ififo_element2_in_d_d29_d0 ;
-   output Iout_d_d26_d1 ;
-   wire Iin_d_d24_d0 ;
-   wire Ififo_element2_in_d_d26_d1 ;
-   output Iout_d_d25_d0 ;
-   wire Ififo_element1_in_d_d25_d0 ;
-   wire Ififo_element2_in_v ;
-   output Iout_d_d18_d1 ;
-   output Iout_d_d19_d1 ;
-   wire Ififo_element2_in_d_d2_d0 ;
-   wire Ififo_element1_in_d_d30_d0 ;
-   output Iin_v ;
-   wire Ififo_element2_in_d_d25_d1 ;
-   wire reset_B;
-   wire Ififo_element2_in_d_d6_d1 ;
-   wire Ififo_element2_in_d_d17_d0 ;
-   output Iout_d_d21_d0 ;
-   wire Ififo_element1_in_d_d14_d1 ;
-   wire Ififo_element1_in_d_d2_d0 ;
-   wire Ififo_element1_in_d_d9_d0 ;
-   output Iout_d_d8_d0 ;
-   wire Iin_d_d16_d0 ;
-   wire Ififo_element2_in_d_d5_d0 ;
-   wire Ififo_element1_in_d_d12_d1 ;
-   wire Iin_d_d25_d1 ;
-   wire Ififo_element2_in_d_d9_d0 ;
-   wire Ififo_element1_in_d_d19_d0 ;
-   wire Ififo_element2_in_d_d2_d1 ;
-   wire Ififo_element1_in_d_d2_d1 ;
-   wire Iin_d_d1_d0 ;
-   wire Ififo_element2_in_d_d14_d1 ;
-   wire Ififo_element2_in_d_d27_d0 ;
-   wire Ififo_element1_in_d_d28_d0 ;
-   wire Ififo_element1_in_d_d0_d1 ;
-   wire Ififo_element1_in_d_d30_d1 ;
-   wire Ififo_element2_in_d_d23_d0 ;
-   wire Ififo_element2_in_d_d3_d1 ;
-   wire Iin_d_d28_d1 ;
-   wire Ififo_element2_in_d_d22_d1 ;
-   wire Ififo_element2_in_d_d29_d1 ;
-   output Iout_d_d27_d0 ;
-   wire Iin_d_d17_d1 ;
-   wire Iin_d_d11_d0 ;
-   output Iout_d_d4_d0 ;
-   wire Ififo_element1_in_d_d1_d0 ;
-   wire Ififo_element2_in_d_d18_d1 ;
-   wire Ififo_element2_in_d_d28_d1 ;
-   output Iout_d_d1_d0 ;
-   wire Iin_d_d26_d0 ;
-   wire Ififo_element1_in_d_d20_d0 ;
-   wire Ififo_element1_in_d_d14_d0 ;
-   wire Ififo_element1_in_d_d10_d1 ;
-   wire Ififo_element1_in_d_d18_d1 ;
-   wire Ififo_element2_in_d_d20_d1 ;
-   wire Ififo_element2_in_d_d21_d1 ;
-   wire Ififo_element1_in_d_d29_d1 ;
-   wire _reset_BX ;
-   output Iout_d_d15_d1 ;
-   wire Iin_d_d19_d0 ;
-   output Iout_d_d4_d1 ;
-   output Iout_d_d10_d1 ;
-   output Iout_d_d11_d1 ;
-   wire Ififo_element1_in_d_d27_d1 ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d16_d0 ;
-   wire Ififo_element2_in_d_d24_d0 ;
-   wire Ififo_element2_in_d_d17_d1 ;
-   output Iout_d_d21_d1 ;
-   wire Ififo_element1_in_d_d26_d0 ;
-   wire Iin_d_d21_d0 ;
-   output Iout_d_d13_d1 ;
-   wire Iin_d_d30_d1 ;
-   output Iout_d_d29_d1 ;
-   output Iout_d_d30_d1 ;
-   wire Ififo_element1_in_d_d12_d0 ;
-   wire Ififo_element1_in_d_d6_d1 ;
-   wire Iin_d_d23_d1 ;
-   wire Iin_d_d19_d1 ;
-   wire Ififo_element2_in_d_d18_d0 ;
-   wire Ififo_element1_in_d_d8_d1 ;
-   wire Ififo_element1_in_d_d21_d1 ;
-   wire Ififo_element1_in_d_d8_d0 ;
-   wire Iin_d_d22_d1 ;
-   wire Iin_d_d10_d0 ;
-   output Iout_d_d7_d1 ;
-   wire Ififo_element1_in_d_d1_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Ififo_element2_in_d_d15_d0 ;
-   wire Ififo_element1_in_d_d25_d1 ;
-   wire Ififo_element1_in_d_d0_d0 ;
-   wire Ififo_element2_in_d_d10_d0 ;
-   wire Ififo_element2_in_d_d16_d1 ;
-   output Iout_d_d3_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire I_reset_BXX2 ;
-   wire Ififo_element2_in_d_d8_d0 ;
-   output Iout_d_d17_d1 ;
-   wire Iin_d_d20_d1 ;
-   output Iout_d_d14_d0 ;
-   wire Ififo_element1_in_d_d16_d1 ;
-   wire Ififo_element2_in_d_d15_d1 ;
-   wire Ififo_element2_in_d_d30_d1 ;
-   output Iout_d_d15_d0 ;
-   wire Ififo_element1_in_d_d17_d0 ;
-   wire Ififo_element1_in_d_d24_d1 ;
-   wire Ififo_element1_in_d_d4_d0 ;
-   wire Iin_d_d27_d0 ;
-   wire Iin_d_d10_d1 ;
-   wire Ififo_element2_in_d_d26_d0 ;
-   wire Ififo_element1_in_d_d29_d0 ;
-   wire Iin_d_d13_d0 ;
-   output Iout_d_d2_d1 ;
-   wire Ififo_element1_in_d_d4_d1 ;
-   wire Iin_d_d6_d1 ;
-   wire Ififo_element2_in_d_d3_d0 ;
-   wire Ififo_element2_in_d_d4_d0 ;
-   output Iout_d_d23_d0 ;
-   output Iout_d_d28_d0 ;
-   wire Ififo_element1_in_d_d21_d0 ;
-   wire Ififo_element2_in_d_d30_d0 ;
-   wire Ififo_element1_in_d_d24_d0 ;
-   wire Ififo_element1_in_d_d23_d0 ;
-   wire Ififo_element1_in_d_d5_d1 ;
-   wire Iin_d_d15_d1 ;
-   output Iout_d_d11_d0 ;
-   wire Iout_v ;
-   wire Iin_d_d8_d0 ;
-   wire Ififo_element1_in_d_d3_d1 ;
-   wire Ififo_element2_in_d_d7_d1 ;
-   output Iout_d_d5_d1 ;
-   wire Ififo_element2_in_d_d27_d1 ;
-   output Iout_d_d20_d0 ;
-   wire Ififo_element2_in_d_d22_d0 ;
-   wire Ififo_element1_in_d_d22_d1 ;
-   wire Ififo_element1_in_d_d10_d0 ;
-   wire Iin_d_d14_d1 ;
-   wire Ififo_element2_in_d_d13_d0 ;
-   output Iout_d_d22_d0 ;
-   wire Iin_d_d0_d0 ;
-   wire Ififo_element2_in_d_d20_d0 ;
-   wire Ififo_element2_in_d_d25_d0 ;
-   wire Ififo_element1_in_d_d16_d0 ;
-   wire Iin_d_d18_d1 ;
-   output Iout_d_d18_d0 ;
-   wire Ififo_element2_in_d_d24_d1 ;
-   wire Ififo_element1_in_d_d15_d0 ;
-   wire Iin_d_d17_d0 ;
-   wire Ififo_element1_in_d_d18_d0 ;
-   output Iout_d_d13_d0 ;
-   output Iout_d_d24_d0 ;
-   wire Ififo_element1_in_d_d20_d1 ;
-   wire Ififo_element2_in_d_d23_d1 ;
-   wire Iin_d_d11_d1 ;
-   output Iout_d_d7_d0 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d23_d1 ;
-   output Iout_d_d26_d0 ;
    output Iout_d_d30_d0 ;
-   wire Iin_d_d28_d0 ;
-   wire Ififo_element2_in_d_d8_d1 ;
-   output Iout_d_d14_d1 ;
-   output Iout_d_d29_d0 ;
-   wire Iin_d_d7_d1 ;
-   output Iout_d_d19_d0 ;
-   wire Iin_d_d5_d0 ;
-   wire Ififo_element2_in_d_d11_d0 ;
+   wire Ififo_element1_in_d_d17_d0 ;
+   wire Ififo_element1_in_d_d16_d1 ;
+   wire Iout_v ;
+   wire Ififo_element2_in_d_d17_d1 ;
+   output Iout_d_d24_d1 ;
+   output Iin_v ;
+   wire Ififo_element2_in_d_d2_d1 ;
    wire Ififo_element2_in_d_d12_d0 ;
-   wire Ififo_element1_in_d_d13_d0 ;
-   output Iout_d_d8_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Ififo_element2_in_d_d4_d1 ;
+   wire Ififo_element1_in_d_d24_d1 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d4_d1 ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d1_d1 ;
+   wire Ififo_element1_in_d_d23_d1 ;
+   wire Iin_d_d24_d0 ;
+   wire Ififo_element2_in_d_d4_d0 ;
    wire Ififo_element2_in_d_d14_d0 ;
-   output Iout_d_d9_d0 ;
-   output Iout_d_d10_d0 ;
-   wire Ififo_element1_in_d_d26_d1 ;
+   wire Ififo_element2_in_d_d17_d0 ;
+   output Iout_d_d17_d1 ;
+   wire Ififo_element1_in_d_d14_d0 ;
+   wire Ififo_element1_in_d_d14_d1 ;
+   wire Ififo_element1_in_d_d11_d0 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d12_d1 ;
+   wire Ififo_element1_in_d_d18_d0 ;
+   wire Iin_d_d19_d0 ;
+   wire Ififo_element2_in_d_d26_d1 ;
+   wire Ififo_element2_in_d_d28_d1 ;
+   wire Ififo_element1_in_d_d4_d1 ;
+   wire Ififo_element1_in_d_d3_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d_d8_d0 ;
+   wire Iin_d_d22_d1 ;
+   wire Ififo_element2_in_d_d0_d1 ;
+   output Iout_d_d19_d1 ;
+   wire Ififo_element1_in_d_d10_d1 ;
+   wire Ififo_element2_in_d_d7_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Ififo_element1_in_d_d1_d0 ;
+   wire Iin_d_d28_d0 ;
+   output Iout_d_d22_d0 ;
+   wire Iin_d_d13_d0 ;
+   output Iout_d_d7_d0 ;
+   wire Ififo_element1_in_d_d25_d0 ;
+   wire Ififo_element1_in_d_d1_d1 ;
+   wire Iin_d_d27_d0 ;
+   wire Iin_d_d7_d0 ;
+   wire Ififo_element1_in_d_d15_d0 ;
+   wire Ififo_element2_in_d_d7_d1 ;
+   wire Ififo_element2_in_d_d23_d1 ;
+   wire Ififo_element1_in_d_d0_d1 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d0_d0 ;
+   output Iout_d_d10_d1 ;
+   wire Ififo_element1_in_a ;
+   wire Ififo_element1_in_d_d30_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire Ififo_element1_in_d_d22_d0 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d_d5_d0 ;
+   wire Ififo_element2_in_d_d20_d1 ;
+   output Iout_d_d26_d1 ;
+   wire Iin_d_d30_d0 ;
+   wire Ififo_element2_in_d_d19_d0 ;
+   wire Ififo_element1_in_d_d8_d0 ;
+   wire Ififo_element2_in_d_d24_d0 ;
+   output Iout_d_d20_d0 ;
+   wire Iin_d_d25_d0 ;
+   wire Ififo_element2_in_d_d21_d0 ;
+   wire Ififo_element2_in_a ;
+   wire Ififo_element1_in_d_d19_d0 ;
+   wire Ififo_element1_in_d_d6_d1 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d16_d0 ;
+   wire Ififo_element1_in_d_d29_d1 ;
+   wire Ififo_element2_in_d_d2_d0 ;
+   wire Ififo_element2_in_d_d6_d0 ;
+   output Iout_d_d23_d0 ;
+   output Iout_d_d19_d0 ;
+   wire Ififo_element1_in_d_d4_d0 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d23_d0 ;
+   wire Ififo_element2_in_v ;
+   output Iin_a ;
+   wire Ififo_element2_in_d_d1_d0 ;
+   output Iout_d_d29_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Ififo_element2_in_d_d16_d0 ;
+   output Iout_d_d2_d1 ;
+   wire Ififo_element1_in_d_d23_d0 ;
+   wire Ififo_element1_in_d_d3_d0 ;
+   wire Ififo_element1_in_d_d2_d0 ;
+   wire Ififo_element1_in_d_d18_d1 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Ififo_element2_in_d_d19_d1 ;
+   wire Ififo_element1_in_d_d20_d1 ;
+   wire Ififo_element1_in_d_d5_d0 ;
+   wire Ififo_element1_in_v ;
+   output Iout_d_d21_d0 ;
+   wire Ififo_element1_in_d_d27_d1 ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d30_d1 ;
+   wire Iin_d_d29_d0 ;
+   output Iout_d_d16_d1 ;
+   output Iout_d_d28_d1 ;
+   wire Ififo_element2_in_d_d22_d0 ;
+   wire Ififo_element1_in_d_d7_d1 ;
    wire Iin_d_d21_d1 ;
-   wire Iin_d_d2_d0 ;
+   wire Ififo_element2_in_d_d5_d1 ;
+   wire Ififo_element2_in_d_d23_d0 ;
+   output Iout_d_d9_d0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_332_73_4/netlist/verilog.v

@@ -136,273 +136,273 @@ module tmpl_0_0dataflow__neuro_0_0fifo_332_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_
    input reset_B;
 
 // -- signals ---
-   wire Ififo_element2_in_d_d19_d1 ;
-   wire Iout_v ;
-   wire Ififo_element1_in_d_d31_d0 ;
-   wire Ififo_element1_in_d_d18_d0 ;
-   wire Ififo_element2_in_d_d13_d0 ;
-   wire Ififo_element2_in_d_d24_d0 ;
-   output Iout_d_d21_d0 ;
-   output Iout_d_d28_d1 ;
-   output Iout_d_d3_d1 ;
-   output Iout_d_d14_d1 ;
-   wire Ififo_element2_in_d_d16_d1 ;
-   output Iout_d_d10_d1 ;
-   output Iout_d_d26_d1 ;
-   output Iin_v ;
-   wire Iin_d_d26_d0 ;
-   wire Iin_d_d25_d0 ;
+   wire Ififo_element1_in_d_d28_d0 ;
    wire Ififo_element2_in_d_d11_d0 ;
-   wire Ififo_element1_in_d_d9_d0 ;
-   output Iout_d_d4_d0 ;
-   wire Ififo_element2_in_d_d30_d0 ;
-   output Iout_d_d19_d0 ;
-   output Iout_d_d22_d1 ;
-   wire Iin_d_d17_d1 ;
-   wire Ififo_element2_in_d_d1_d1 ;
-   output Iout_d_d6_d1 ;
-   output Iout_d_d8_d0 ;
-   wire Ififo_element1_in_d_d2_d0 ;
-   wire Ififo_element2_in_d_d11_d1 ;
-   wire Ififo_element2_in_d_d13_d1 ;
-   output Iout_d_d20_d0 ;
-   wire Ififo_element1_in_d_d26_d1 ;
-   wire Iin_d_d9_d0 ;
-   wire Ififo_element2_in_d_d17_d1 ;
-   output Iout_d_d31_d0 ;
-   output Iout_d_d30_d1 ;
-   wire Ififo_element1_in_d_d10_d1 ;
-   wire Ififo_element2_in_d_d27_d1 ;
-   output Iout_d_d5_d0 ;
-   wire Iin_d_d25_d1 ;
-   wire Ififo_element2_in_d_d17_d0 ;
-   wire Ififo_element2_in_d_d23_d1 ;
-   wire Ififo_element1_in_d_d0_d0 ;
-   wire Iin_d_d23_d0 ;
-   wire Ififo_element1_in_d_d19_d0 ;
-   wire Ififo_element1_in_d_d18_d1 ;
-   wire Iin_d_d9_d1 ;
-   wire Ififo_element1_in_d_d1_d0 ;
-   wire Iin_d_d28_d1 ;
-   wire Iin_d_d8_d0 ;
-   wire Ififo_element2_in_d_d14_d0 ;
-   output Iout_d_d27_d0 ;
-   wire Ififo_element1_in_d_d27_d1 ;
-   wire Ififo_element1_in_d_d13_d1 ;
-   output Iout_d_d29_d0 ;
-   wire Ififo_element2_in_d_d30_d1 ;
-   wire Ififo_element1_in_d_d22_d1 ;
-   wire Ififo_element2_in_d_d9_d1 ;
-   output Iout_d_d22_d0 ;
-   wire Ififo_element2_in_d_d15_d1 ;
-   wire Iin_d_d30_d0 ;
-   wire Ififo_element1_in_d_d20_d0 ;
-   wire Iin_d_d22_d0 ;
-   output Iout_d_d0_d1 ;
-   wire Ififo_element1_in_d_d21_d1 ;
-   wire Ififo_element1_in_d_d9_d1 ;
-   output Iout_d_d9_d0 ;
-   wire Ififo_element2_in_d_d2_d1 ;
-   wire Ififo_element2_in_d_d18_d0 ;
-   wire Ififo_element2_in_d_d29_d1 ;
-   output Iout_d_d2_d0 ;
-   wire Ififo_element1_in_d_d22_d0 ;
-   output Iout_d_d15_d1 ;
-   wire Ififo_element1_in_d_d14_d0 ;
-   output Iout_d_d23_d0 ;
-   wire Ififo_element1_in_d_d12_d1 ;
-   wire Ififo_element1_in_d_d5_d0 ;
-   wire Iin_d_d23_d1 ;
-   wire I_reset_BXX2 ;
-   wire Ififo_element2_in_d_d5_d0 ;
-   wire Ififo_element2_in_d_d26_d0 ;
-   output Iout_d_d5_d1 ;
-   wire Ififo_element1_in_d_d25_d1 ;
-   wire Ififo_element1_in_d_d13_d0 ;
-   wire Ififo_element1_in_d_d4_d1 ;
-   wire Ififo_element2_in_d_d9_d0 ;
-   wire Ififo_element2_in_d_d6_d0 ;
-   wire Ififo_element1_in_d_d17_d0 ;
-   wire Iin_d_d30_d1 ;
-   wire Ififo_element2_in_d_d10_d0 ;
-   wire Ififo_element2_in_d_d3_d0 ;
-   output Iout_d_d25_d0 ;
-   wire Ififo_element1_in_d_d11_d0 ;
-   wire Iin_d_d2_d1 ;
-   wire Ififo_element2_in_d_d25_d0 ;
-   output Iout_d_d8_d1 ;
-   wire Iin_d_d10_d1 ;
-   wire Ififo_element1_in_v ;
-   output Iout_d_d18_d1 ;
-   wire Ififo_element1_in_d_d15_d1 ;
-   wire Iin_d_d18_d0 ;
-   output Iout_d_d7_d0 ;
-   wire Ififo_element1_in_d_d25_d0 ;
-   wire Iin_d_d20_d1 ;
-   wire Ififo_element2_in_a ;
-   output Iout_d_d23_d1 ;
-   wire Iin_d_d1_d0 ;
-   wire Ififo_element2_in_d_d16_d0 ;
-   wire Ififo_element2_in_d_d27_d0 ;
-   output Iout_d_d13_d1 ;
-   wire Iin_d_d16_d1 ;
-   wire Iin_d_d6_d0 ;
-   wire reset_B;
-   wire Ififo_element1_in_a ;
-   output Iout_d_d1_d0 ;
-   wire Ififo_element1_in_d_d21_d0 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d2_d0 ;
-   wire Iin_d_d29_d1 ;
-   output Iout_d_d28_d0 ;
-   wire Ififo_element1_in_d_d20_d1 ;
-   wire Ififo_element1_in_d_d7_d1 ;
-   wire Ififo_element1_in_d_d7_d0 ;
-   wire Iin_d_d17_d0 ;
-   wire Ififo_element2_in_d_d15_d0 ;
-   wire Ififo_element1_in_d_d24_d0 ;
-   wire Iin_d_d5_d0 ;
-   wire Ififo_element2_in_d_d4_d1 ;
-   wire Iin_d_d7_d0 ;
-   wire Ififo_element1_in_d_d8_d1 ;
-   wire Iin_d_d0_d0 ;
-   wire Ififo_element2_in_d_d3_d1 ;
-   output Iout_d_d27_d1 ;
-   wire Ififo_element1_in_d_d6_d0 ;
-   wire Iin_d_d29_d0 ;
-   output Iout_d_d16_d1 ;
-   wire Ififo_element2_in_v ;
-   output Iout_d_d4_d1 ;
-   output Iout_d_d10_d0 ;
-   wire Ififo_element1_in_d_d16_d1 ;
-   wire Iin_d_d26_d1 ;
-   output Iout_d_d31_d1 ;
-   output Iout_d_d29_d1 ;
-   wire Ififo_element2_in_d_d0_d0 ;
-   output Iout_d_d12_d1 ;
-   wire Ififo_element1_in_d_d29_d1 ;
-   wire Iin_d_d7_d1 ;
-   wire Ififo_element2_in_d_d20_d0 ;
-   wire Iin_d_d4_d0 ;
-   wire Ififo_element2_in_d_d18_d1 ;
-   wire Ififo_element1_in_d_d6_d1 ;
-   wire Ififo_element2_in_d_d5_d1 ;
-   wire Ififo_element2_in_d_d26_d1 ;
-   output Iout_d_d17_d0 ;
-   output Iout_d_d26_d0 ;
-   wire Ififo_element2_in_d_d25_d1 ;
-   output Iout_d_d11_d1 ;
-   wire Iin_d_d14_d1 ;
-   output Iout_d_d18_d0 ;
-   wire Iin_d_d12_d0 ;
-   wire Ififo_element2_in_d_d7_d1 ;
-   output Iout_d_d3_d0 ;
-   wire Iin_d_d27_d1 ;
-   wire Ififo_element2_in_d_d23_d0 ;
-   wire Iin_d_d19_d1 ;
-   wire Ififo_element1_in_d_d4_d0 ;
-   wire Ififo_element2_in_d_d2_d0 ;
-   wire Ififo_element2_in_d_d29_d0 ;
-   wire Ififo_element2_in_d_d8_d0 ;
-   wire Iin_d_d11_d1 ;
-   wire Ififo_element2_in_d_d10_d1 ;
-   output Iout_d_d9_d1 ;
    output Iout_d_d20_d1 ;
    wire Ififo_element1_in_d_d29_d0 ;
-   wire Ififo_element1_in_d_d27_d0 ;
-   wire Ififo_element1_in_d_d24_d1 ;
-   wire Ififo_element1_in_d_d3_d1 ;
-   wire Iin_d_d21_d1 ;
-   wire Iin_d_d13_d1 ;
-   wire Ififo_element2_in_d_d31_d0 ;
-   wire Iin_d_d16_d0 ;
-   wire Ififo_element2_in_d_d22_d1 ;
-   output Iout_d_d30_d0 ;
-   wire Ififo_element2_in_d_d7_d0 ;
-   wire Ififo_element2_in_d_d28_d1 ;
-   wire Ififo_element1_in_d_d17_d1 ;
-   wire Iin_d_d24_d0 ;
-   wire Iin_d_d0_d1 ;
-   output Iout_d_d13_d0 ;
-   wire Ififo_element1_in_d_d19_d1 ;
-   wire Iin_d_d19_d0 ;
-   wire Ififo_element2_in_d_d31_d1 ;
-   wire Iin_d_d10_d0 ;
-   wire Ififo_element2_in_d_d22_d0 ;
-   wire Iin_d_d31_d1 ;
-   wire Iin_d_d21_d0 ;
-   wire Iin_d_d3_d0 ;
-   wire Ififo_element2_in_d_d19_d0 ;
-   wire Iin_d_d31_d0 ;
-   wire Ififo_element1_in_d_d31_d1 ;
-   wire Ififo_element2_in_d_d20_d1 ;
-   wire Ififo_element1_in_d_d16_d0 ;
-   wire Ififo_element1_in_d_d2_d1 ;
-   wire Iin_d_d22_d1 ;
-   wire Ififo_element1_in_d_d12_d0 ;
-   wire Iin_d_d8_d1 ;
-   wire Ififo_element2_in_d_d0_d1 ;
-   wire Ififo_element1_in_d_d5_d1 ;
-   wire Iin_d_d11_d0 ;
-   output Iout_d_d14_d0 ;
-   output Iout_d_d24_d0 ;
    wire Ififo_element1_in_d_d10_d0 ;
-   wire Iin_d_d13_d0 ;
-   wire Ififo_element1_in_d_d0_d1 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d27_d0 ;
-   wire Iin_d_d4_d1 ;
-   wire _reset_BX ;
-   wire Ififo_element1_in_d_d23_d1 ;
-   wire Iin_d_d15_d0 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d15_d1 ;
-   wire Ififo_element2_in_d_d12_d1 ;
-   output Iout_d_d11_d0 ;
-   wire Ififo_element2_in_d_d8_d1 ;
-   output Iout_d_d2_d1 ;
-   wire Ififo_element1_in_d_d11_d1 ;
-   wire Ififo_element2_in_d_d6_d1 ;
-   wire Ififo_element2_in_d_d21_d1 ;
-   output Iout_d_d1_d1 ;
-   output Iout_d_d21_d1 ;
-   wire Ififo_element1_in_d_d23_d0 ;
-   wire Ififo_element1_in_d_d30_d1 ;
-   wire Ififo_element1_in_d_d14_d1 ;
-   wire Ififo_element1_in_d_d3_d0 ;
-   wire Ififo_element2_in_d_d4_d0 ;
-   wire Ififo_element1_in_d_d15_d0 ;
-   wire Iin_d_d18_d1 ;
-   wire Iin_d_d12_d1 ;
-   wire Ififo_element2_in_d_d21_d0 ;
-   output Iout_d_d7_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Ififo_element2_in_d_d1_d1 ;
+   wire Ififo_element2_in_d_d16_d0 ;
+   output Iout_d_d21_d0 ;
+   wire Ififo_element1_in_d_d16_d1 ;
+   wire Ififo_element1_in_d_d9_d0 ;
    wire Ififo_element1_in_d_d28_d1 ;
-   wire Ififo_element1_in_d_d1_d1 ;
-   wire Ififo_element2_in_d_d12_d0 ;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d6_d1 ;
-   wire Ififo_element1_in_d_d26_d0 ;
-   output Iin_a ;
-   wire Ififo_element2_in_d_d14_d1 ;
-   output Iout_d_d6_d0 ;
-   wire Ififo_element1_in_d_d30_d0 ;
-   output Iout_d_d0_d0 ;
-   output Iout_d_d12_d0 ;
-   output Iout_d_d24_d1 ;
-   wire Ififo_element1_in_d_d28_d0 ;
-   output Iout_d_d17_d1 ;
-   output Iout_d_d25_d1 ;
-   output Iout_d_d15_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire Iout_a ;
-   wire Iin_d_d1_d1 ;
-   wire Ififo_element2_in_d_d1_d0 ;
-   wire Ififo_element2_in_d_d24_d1 ;
-   output Iout_d_d16_d0 ;
+   wire reset_B;
+   wire Ififo_element2_in_d_d17_d0 ;
+   wire Ififo_element2_in_d_d19_d0 ;
+   output Iout_d_d27_d0 ;
+   wire Iout_v ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d14_d0 ;
+   wire Ififo_element2_in_d_d6_d0 ;
+   output Iout_d_d11_d1 ;
+   wire Ififo_element1_in_d_d13_d0 ;
+   wire Ififo_element1_in_d_d12_d1 ;
+   wire Ififo_element1_in_d_d15_d0 ;
+   output Iout_d_d8_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d21_d1 ;
+   wire Ififo_element2_in_d_d11_d1 ;
+   wire Ififo_element2_in_d_d28_d1 ;
    output Iout_d_d19_d1 ;
+   wire Ififo_element2_in_d_d5_d1 ;
+   wire Ififo_element1_in_d_d11_d0 ;
+   output Iout_d_d25_d1 ;
+   wire Iin_d_d0_d1 ;
+   wire Ififo_element2_in_d_d19_d1 ;
+   wire Ififo_element2_in_d_d23_d0 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d8_d0 ;
+   output Iout_d_d11_d0 ;
+   output Iout_d_d19_d0 ;
+   wire Ififo_element2_in_d_d25_d0 ;
+   wire Ififo_element1_in_d_d23_d0 ;
+   wire Ififo_element1_in_d_d22_d0 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d22_d1 ;
+   wire Ififo_element2_in_d_d24_d0 ;
+   wire Iin_d_d25_d0 ;
+   wire Ififo_element2_in_d_d4_d1 ;
+   wire Ififo_element2_in_d_d31_d1 ;
+   wire Ififo_element1_in_d_d29_d1 ;
+   wire Ififo_element2_in_d_d12_d1 ;
+   wire Ififo_element2_in_d_d27_d1 ;
+   wire Iin_d_d6_d0 ;
+   wire Ififo_element1_in_d_d18_d0 ;
+   wire Iin_d_d29_d1 ;
+   wire Ififo_element2_in_d_d15_d0 ;
+   wire Ififo_element1_in_d_d16_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire Ififo_element2_in_d_d9_d1 ;
+   wire Ififo_element2_in_d_d10_d1 ;
+   wire Ififo_element2_in_d_d26_d0 ;
+   wire Iin_d_d3_d1 ;
+   wire Ififo_element1_in_d_d19_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d4_d1 ;
+   wire Ififo_element1_in_d_d21_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d1_d1 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d_d0_d0 ;
+   wire Ififo_element1_in_d_d2_d1 ;
+   wire Ififo_element1_in_d_d12_d0 ;
+   wire Ififo_element1_in_d_d0_d1 ;
+   wire Ififo_element2_in_d_d4_d0 ;
+   wire Ififo_element1_in_d_d25_d0 ;
+   wire Ififo_element1_in_d_d10_d1 ;
+   wire Iin_d_d21_d0 ;
+   wire Ififo_element2_in_d_d29_d1 ;
+   output Iout_d_d17_d1 ;
+   output Iout_d_d18_d1 ;
+   output Iout_d_d28_d1 ;
+   output Iin_v ;
+   wire Iin_d_d29_d0 ;
+   wire Ififo_element2_in_a ;
+   wire Ififo_element2_in_d_d13_d1 ;
+   wire Ififo_element1_in_d_d17_d1 ;
+   wire Iin_d_d1_d0 ;
+   output Iout_d_d15_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Ififo_element1_in_d_d30_d1 ;
+   wire Ififo_element1_in_d_d24_d0 ;
+   wire Ififo_element2_in_d_d24_d1 ;
+   wire Ififo_element1_in_d_d11_d1 ;
    wire Ififo_element1_in_d_d8_d0 ;
+   wire Iin_d_d19_d0 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d9_d0 ;
+   output Iout_d_d30_d1 ;
+   wire Ififo_element2_in_d_d6_d1 ;
+   output Iout_d_d27_d1 ;
+   wire Ififo_element2_in_d_d2_d1 ;
+   wire Ififo_element1_in_d_d27_d0 ;
+   wire Iin_d_d2_d0 ;
+   wire Ififo_element2_in_d_d30_d0 ;
+   wire Ififo_element2_in_v ;
+   wire Iin_d_d11_d0 ;
+   output Iout_d_d16_d0 ;
+   wire Ififo_element1_in_d_d2_d0 ;
+   output Iout_d_d26_d0 ;
+   wire Ififo_element1_in_d_d4_d1 ;
+   wire Iin_d_d8_d1 ;
+   output Iout_d_d4_d0 ;
+   wire Ififo_element1_in_d_d31_d1 ;
+   wire Ififo_element1_in_d_d3_d0 ;
+   output Iout_d_d6_d1 ;
+   wire Ififo_element2_in_d_d8_d1 ;
+   wire Ififo_element1_in_d_d4_d0 ;
+   output Iout_d_d21_d1 ;
+   wire Ififo_element1_in_d_d5_d1 ;
+   wire Iin_d_d5_d0 ;
+   wire Ififo_element2_in_d_d27_d0 ;
+   wire Iin_d_d31_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Ififo_element2_in_d_d2_d0 ;
+   output Iout_d_d13_d0 ;
+   wire Ififo_element2_in_d_d21_d1 ;
+   output Iout_d_d12_d1 ;
+   wire Ififo_element2_in_d_d12_d0 ;
+   wire Ififo_element2_in_d_d14_d1 ;
+   wire Iin_d_d10_d0 ;
+   output Iout_d_d13_d1 ;
+   output Iout_d_d28_d0 ;
+   wire Iin_d_d24_d0 ;
+   wire Ififo_element2_in_d_d15_d1 ;
+   wire Ififo_element2_in_d_d25_d1 ;
+   output Iout_d_d18_d0 ;
+   wire Ififo_element2_in_d_d13_d0 ;
+   wire Ififo_element1_in_d_d3_d1 ;
+   wire Ififo_element2_in_d_d0_d0 ;
+   wire Ififo_element2_in_d_d1_d0 ;
+   output Iout_d_d2_d0 ;
+   wire Ififo_element1_in_d_d20_d1 ;
+   wire Ififo_element2_in_d_d22_d1 ;
+   output Iout_d_d2_d1 ;
+   wire Ififo_element1_in_d_d9_d1 ;
+   wire Iin_d_d11_d1 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d14_d0 ;
+   output Iout_d_d17_d0 ;
+   wire Ififo_element1_in_d_d1_d1 ;
+   output Iout_d_d23_d1 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d30_d0 ;
+   wire Ififo_element2_in_d_d22_d0 ;
+   wire Ififo_element1_in_d_d21_d1 ;
+   wire Iin_d_d15_d1 ;
+   wire I_reset_BXX2 ;
+   output Iout_d_d3_d1 ;
+   wire Ififo_element1_in_d_d14_d0 ;
+   wire Ififo_element2_in_d_d21_d0 ;
+   output Iout_d_d12_d0 ;
+   wire Iout_a ;
+   wire Iin_d_d27_d0 ;
+   wire Ififo_element2_in_d_d16_d1 ;
+   output Iout_d_d0_d1 ;
+   wire Ififo_element2_in_d_d0_d1 ;
+   wire Iin_d_d18_d0 ;
+   output Iout_d_d6_d0 ;
+   wire Ififo_element1_in_v ;
+   wire Ififo_element2_in_d_d20_d1 ;
+   wire Ififo_element1_in_d_d14_d1 ;
+   wire Ififo_element1_in_d_d26_d0 ;
+   wire Ififo_element1_in_d_d24_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Ififo_element1_in_d_d19_d1 ;
+   output Iout_d_d22_d0 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d_d24_d1 ;
+   wire Iin_d_d16_d1 ;
+   wire Ififo_element1_in_d_d6_d1 ;
+   output Iout_d_d1_d1 ;
+   output Iout_d_d20_d0 ;
+   output Iout_d_d22_d1 ;
+   output Iout_d_d23_d0 ;
+   wire Ififo_element1_in_d_d1_d0 ;
+   output Iin_a ;
+   wire Ififo_element2_in_d_d20_d0 ;
+   output Iout_d_d31_d0 ;
+   wire Ififo_element1_in_d_d15_d1 ;
+   wire Iin_d_d5_d1 ;
+   output Iout_d_d3_d0 ;
+   output Iout_d_d31_d1 ;
+   wire Ififo_element2_in_d_d23_d1 ;
+   output Iout_d_d16_d1 ;
+   wire Ififo_element2_in_d_d3_d0 ;
+   wire Ififo_element1_in_d_d20_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d9_d1 ;
+   output Iout_d_d25_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d17_d1 ;
+   wire Ififo_element1_in_a ;
+   wire Ififo_element2_in_d_d17_d1 ;
+   wire Ififo_element2_in_d_d18_d1 ;
+   wire Ififo_element1_in_d_d22_d1 ;
+   output Iout_d_d14_d1 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d20_d0 ;
+   wire _reset_BX ;
+   wire Ififo_element2_in_d_d14_d0 ;
+   output Iout_d_d7_d0 ;
+   wire Ififo_element2_in_d_d7_d1 ;
+   wire Ififo_element1_in_d_d23_d1 ;
+   wire Ififo_element2_in_d_d18_d0 ;
+   output Iout_d_d29_d0 ;
+   wire Iin_d_d3_d0 ;
    wire Ififo_element2_in_d_d28_d0 ;
+   wire Ififo_element1_in_d_d30_d0 ;
+   wire Ififo_element1_in_d_d31_d0 ;
+   wire Ififo_element2_in_d_d30_d1 ;
+   wire Ififo_element2_in_d_d31_d0 ;
+   wire Ififo_element1_in_d_d25_d1 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d_d7_d1 ;
+   wire Ififo_element2_in_d_d29_d0 ;
+   wire Ififo_element2_in_d_d5_d0 ;
+   wire Ififo_element2_in_d_d3_d1 ;
+   wire Ififo_element1_in_d_d17_d0 ;
+   wire Iin_d_d20_d1 ;
+   output Iout_d_d5_d0 ;
+   output Iout_d_d15_d1 ;
+   wire Ififo_element1_in_d_d13_d1 ;
+   wire Ififo_element1_in_d_d8_d1 ;
+   wire Ififo_element1_in_d_d7_d1 ;
+   wire Ififo_element1_in_d_d27_d1 ;
+   wire Ififo_element1_in_d_d18_d1 ;
+   wire Iin_d_d0_d0 ;
+   output Iout_d_d4_d1 ;
+   wire Ififo_element1_in_d_d0_d0 ;
+   wire Iin_d_d28_d0 ;
+   output Iout_d_d26_d1 ;
+   wire Ififo_element2_in_d_d7_d0 ;
+   wire Iin_d_d27_d1 ;
+   wire Ififo_element2_in_d_d8_d0 ;
+   wire Ififo_element2_in_d_d9_d0 ;
+   wire Iin_d_d26_d0 ;
+   output Iout_d_d9_d1 ;
+   output Iout_d_d10_d1 ;
+   wire Ififo_element1_in_d_d7_d0 ;
+   output Iout_d_d30_d0 ;
+   wire Iin_d_d24_d1 ;
+   output Iout_d_d24_d0 ;
+   wire Ififo_element1_in_d_d26_d1 ;
+   wire Iin_d_d31_d0 ;
+   wire Iin_d_d26_d1 ;
+   output Iout_d_d10_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Ififo_element2_in_d_d10_d0 ;
+   wire Ififo_element2_in_d_d26_d1 ;
+   wire Ififo_element1_in_d_d6_d0 ;
+   wire Ififo_element1_in_d_d5_d0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0fifo_37_73_4/netlist/verilog.v

@@ -36,73 +36,73 @@ module tmpl_0_0dataflow__neuro_0_0fifo_37_73_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d
    input reset_B;
 
 // -- signals ---
-   output Iout_d_d3_d0 ;
-   wire Ififo_element1_in_d_d6_d0 ;
-   output Iout_d_d2_d0 ;
-   output Iout_d_d1_d0 ;
-   wire Ififo_element1_in_d_d6_d1 ;
-   wire Ififo_element1_in_d_d0_d0 ;
-   wire Iin_d_d2_d0 ;
-   wire reset_B;
-   wire I_reset_BXX2 ;
-   wire Iin_d_d0_d1 ;
-   wire Ififo_element1_in_d_d3_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Ififo_element2_in_d_d5_d1 ;
-   wire Ififo_element2_in_d_d4_d1 ;
-   wire Iin_d_d5_d0 ;
-   wire Ififo_element2_in_d_d6_d1 ;
-   wire Ififo_element1_in_d_d2_d1 ;
-   wire Ififo_element1_in_d_d2_d0 ;
-   wire Ififo_element1_in_d_d0_d1 ;
    wire Ififo_element1_in_d_d5_d1 ;
-   wire Iin_d_d6_d1 ;
-   wire Iout_v ;
-   wire Ififo_element2_in_v ;
-   wire Ififo_element2_in_d_d0_d1 ;
-   wire Ififo_element1_in_v ;
-   wire Ififo_element1_in_d_d4_d0 ;
-   wire Iin_d_d1_d1 ;
-   output Iout_d_d1_d1 ;
-   wire Iin_d_d4_d1 ;
-   output Iout_d_d2_d1 ;
-   wire Ififo_element2_in_a ;
-   wire Ififo_element2_in_d_d2_d0 ;
+   wire Ififo_element1_in_d_d2_d1 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d5_d0 ;
+   output Iout_d_d2_d0 ;
    wire Ififo_element2_in_d_d1_d0 ;
+   wire Ififo_element1_in_d_d4_d1 ;
    wire Iin_d_d3_d1 ;
+   wire Iin_d_d3_d0 ;
+   wire Ififo_element2_in_d_d3_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire I_reset_BXX2 ;
+   wire Iout_a ;
+   wire Iout_v ;
+   wire Ififo_element2_in_d_d1_d1 ;
+   output Iout_d_d2_d1 ;
+   wire Ififo_element2_in_d_d4_d1 ;
    wire Ififo_element2_in_d_d2_d1 ;
    wire Ififo_element1_in_d_d3_d0 ;
-   wire Ififo_element1_in_d_d1_d0 ;
-   output Iin_a ;
-   wire Iin_d_d3_d0 ;
-   output Iout_d_d6_d1 ;
-   wire Ififo_element2_in_d_d1_d1 ;
-   wire Ififo_element2_in_d_d3_d0 ;
-   wire Iin_d_d5_d1 ;
    output Iout_d_d6_d0 ;
-   wire Ififo_element1_in_d_d5_d0 ;
-   wire Ififo_element2_in_d_d4_d0 ;
+   wire Ififo_element1_in_d_d0_d0 ;
+   output Iin_a ;
+   wire Iin_d_d1_d1 ;
    output Iin_v ;
-   output Iout_d_d3_d1 ;
-   output Iout_d_d0_d1 ;
-   wire Ififo_element2_in_d_d6_d0 ;
-   wire Ififo_element2_in_d_d5_d0 ;
-   output Iout_d_d5_d1 ;
-   output Iout_d_d4_d0 ;
-   wire Ififo_element1_in_d_d1_d1 ;
+   wire Iin_d_d0_d1 ;
    wire _reset_BX ;
-   wire Ififo_element2_in_d_d3_d1 ;
-   wire Ififo_element1_in_d_d4_d1 ;
+   wire Ififo_element2_in_v ;
+   wire Ififo_element1_in_d_d5_d0 ;
+   wire Ififo_element1_in_d_d3_d1 ;
+   wire Iin_d_d5_d1 ;
    output Iout_d_d4_d1 ;
+   output Iout_d_d0_d1 ;
+   wire Ififo_element2_in_a ;
+   wire Ififo_element2_in_d_d2_d0 ;
+   wire Ififo_element2_in_d_d6_d1 ;
+   output Iout_d_d6_d1 ;
    output Iout_d_d0_d0 ;
-   wire Iout_a ;
    wire Ififo_element2_in_d_d0_d0 ;
-   wire Iin_d_d6_d0 ;
+   wire Iin_d_d4_d1 ;
+   wire Ififo_element2_in_d_d6_d0 ;
+   wire Ififo_element2_in_d_d5_d1 ;
+   output Iout_d_d3_d1 ;
+   wire Ififo_element2_in_d_d0_d1 ;
    wire Ififo_element1_in_a ;
-   wire Iin_d_d0_d0 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d_d3_d0 ;
+   wire Ififo_element1_in_d_d1_d0 ;
+   wire reset_B;
+   wire Ififo_element1_in_d_d4_d0 ;
+   wire Ififo_element2_in_d_d5_d0 ;
+   wire Ififo_element1_in_d_d2_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire Ififo_element1_in_v ;
+   wire Ififo_element1_in_d_d0_d1 ;
+   wire Ififo_element2_in_d_d3_d1 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d1_d0 ;
+   wire Ififo_element2_in_d_d4_d0 ;
+   wire Iin_d_d6_d0 ;
    output Iout_d_d5_d0 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d2_d1 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d1_d1 ;
+   wire Ififo_element1_in_d_d6_d1 ;
+   wire Ififo_element1_in_d_d6_d0 ;
+   wire Ififo_element1_in_d_d1_d1 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_33_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX2 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0fork_332_4/netlist/verilog.v

@@ -202,215 +202,215 @@ module tmpl_0_0dataflow__neuro_0_0fork_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d
    input reset_B;
 
 // -- signals ---
-   wire Iout1_v ;
-   wire Iout2_v ;
-   output Iout2_d_d16_d1 ;
-   output Iout2_d_d3_d1 ;
-   wire Iin_d_d26_d1 ;
-   wire Iin_d_d29_d0 ;
-   output Iout1_d_d28_d0 ;
-   output Iout1_d_d5_d1 ;
-   output Iout1_d_d0_d0 ;
-   output Iout1_d_d3_d0 ;
-   output Iout2_d_d6_d1 ;
-   output Iout1_d_d15_d1 ;
-   output Iout2_d_d28_d1 ;
-   wire Iin_d_d21_d0 ;
-   wire Iout1_a_B_buf_out0 ;
-   output Iout1_d_d6_d0 ;
-   wire Iout1_a ;
-   wire Iin_d_d18_d1 ;
-   output Iout1_d_d29_d1 ;
-   wire Iin_d_d23_d1 ;
-   output Iout1_d_d12_d1 ;
-   output Iout1_d_d20_d1 ;
-   wire Iin_d_d29_d1 ;
-   output Iout2_d_d26_d0 ;
-   wire _out1_a_B ;
-   wire Iin_d_d24_d0 ;
-   wire Iin_d_d31_d0 ;
-   output Iout2_d_d31_d0 ;
-   output Iout2_d_d10_d0 ;
-   output Iout2_d_d11_d1 ;
-   wire reset_B;
-   output Iout1_d_d2_d1 ;
-   output Iout2_d_d24_d0 ;
-   wire Iin_d_d1_d0 ;
-   wire Iin_d_d15_d1 ;
-   wire Iin_d_d7_d0 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d27_d1 ;
-   wire Iin_d_d2_d0 ;
-   output Iout1_d_d1_d0 ;
-   output Iout1_d_d16_d1 ;
-   output Iout2_d_d22_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire Iin_d_d16_d1 ;
-   output Iout1_d_d13_d0 ;
-   output Iout2_d_d20_d0 ;
-   output Iout2_d_d19_d1 ;
-   output Iout1_d_d20_d0 ;
-   output Iout2_d_d25_d1 ;
-   output Iout2_d_d24_d1 ;
-   wire Iin_d_d14_d0 ;
-   output Iout2_d_d20_d1 ;
-   wire Iin_d_d12_d1 ;
-   wire Iout2_a ;
-   output Iout1_d_d19_d0 ;
-   output Iout2_d_d30_d0 ;
-   output Iout2_d_d29_d0 ;
-   output Iout2_d_d19_d0 ;
-   output Iout2_d_d8_d0 ;
-   output Iout2_d_d2_d1 ;
-   wire Iin_d_d1_d1 ;
-   wire Iin_d_d23_d0 ;
-   output Iout1_d_d6_d1 ;
-   wire _in_v ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d17_d0 ;
-   output Iout2_d_d9_d1 ;
-   output Iout2_d_d5_d1 ;
-   output Iout1_d_d31_d1 ;
-   wire Iin_d_d16_d0 ;
-   output Iout1_d_d24_d0 ;
-   output Iout2_d_d7_d0 ;
-   output Iout2_d_d4_d0 ;
-   output Iout1_d_d18_d1 ;
-   output Iout1_d_d30_d0 ;
-   output Iout1_d_d4_d1 ;
-   output Iout2_d_d13_d1 ;
-   wire I_reset_BXX0 ;
-   output Iout1_d_d2_d0 ;
-   output Iout1_d_d4_d0 ;
-   output Iout1_d_d17_d0 ;
-   output Iout2_d_d29_d1 ;
-   output Iout1_d_d19_d1 ;
-   wire Iin_d_d5_d0 ;
-   wire Iin_d_d17_d1 ;
-   output Iout1_d_d16_d0 ;
-   output Iout1_d_d22_d1 ;
-   wire Iin_d_d31_d1 ;
-   output Iout1_d_d11_d0 ;
-   output Iout2_d_d5_d0 ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d21_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d12_d0 ;
-   output Iout2_d_d16_d0 ;
-   output Iout2_d_d17_d1 ;
-   output Iin_v ;
-   wire Iin_d_d11_d1 ;
-   output Iout2_d_d15_d0 ;
-   output Iout2_d_d12_d0 ;
-   output Iout2_d_d1_d0 ;
-   output Iout1_d_d28_d1 ;
-   output Iout1_d_d17_d1 ;
-   output Iout2_d_d9_d0 ;
-   output Iout2_d_d26_d1 ;
-   wire Iin_d_d26_d0 ;
-   wire Iin_d_d27_d0 ;
-   wire Iin_d_d28_d0 ;
-   output Iout2_d_d14_d0 ;
-   output Iout2_d_d11_d0 ;
-   output Iout2_d_d7_d1 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d13_d1 ;
-   output Iout1_d_d0_d1 ;
-   output Iout2_d_d21_d1 ;
-   wire Iout2_a_B_buf_out0 ;
    wire _en ;
-   wire Iout1_en_buf_out0 ;
-   wire Iin_d_d4_d1 ;
    wire Iin_d_d8_d1 ;
-   wire _out2_a_B ;
-   output Iout1_d_d30_d1 ;
-   wire _reset_BX ;
-   wire Iin_d_d4_d0 ;
-   output Iout1_d_d31_d0 ;
-   output Iout1_d_d14_d1 ;
-   output Iout1_d_d7_d0 ;
-   output Iout1_d_d13_d1 ;
-   output Iout2_d_d18_d0 ;
-   wire Iin_d_d9_d1 ;
-   wire Iin_d_d19_d0 ;
-   output Iout2_d_d23_d0 ;
-   output Iout2_d_d30_d1 ;
-   wire Iin_d_d0_d0 ;
-   wire Iin_d_d0_d1 ;
-   output Iout2_d_d25_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d8_d0 ;
-   wire Iin_d_d18_d0 ;
-   output Iout2_d_d28_d0 ;
-   output Iout1_d_d22_d0 ;
-   output Iout1_d_d3_d1 ;
-   wire Iin_d_d3_d0 ;
-   wire Iin_d_d25_d1 ;
-   wire Iin_d_d30_d0 ;
-   output Iout1_d_d15_d0 ;
-   output Iout1_d_d1_d1 ;
-   wire Iin_d_d28_d1 ;
-   output Iout1_d_d14_d0 ;
-   output Iout2_d_d0_d0 ;
-   output Iout1_d_d27_d1 ;
-   output Iout1_d_d21_d0 ;
-   wire Iin_d_d10_d1 ;
-   output Iout2_d_d3_d0 ;
-   output Iout2_d_d15_d1 ;
+   output Iout1_d_d2_d0 ;
    output Iout2_d_d14_d1 ;
-   wire Iin_d_d22_d1 ;
-   output Iout2_d_d27_d1 ;
-   output Iout1_d_d18_d0 ;
-   output Iout2_d_d2_d0 ;
-   wire Iin_d_d15_d0 ;
-   wire Iin_d_d24_d1 ;
-   output Iout2_d_d18_d1 ;
-   wire Iin_d_d19_d1 ;
-   output Iout1_d_d9_d0 ;
-   output Iout1_d_d10_d0 ;
-   output Iout2_d_d17_d0 ;
-   output Iout2_d_d12_d1 ;
-   output Iout2_d_d8_d1 ;
-   wire Iin_d_d14_d1 ;
-   output Iout1_d_d25_d0 ;
-   output Iout1_d_d8_d1 ;
-   output Iout2_d_d27_d0 ;
-   output Iout2_d_d23_d1 ;
-   wire Iin_d_d10_d0 ;
-   wire Iin_d_d20_d1 ;
-   output Iout2_d_d0_d1 ;
-   output Iout1_d_d12_d0 ;
-   output Iout1_d_d21_d1 ;
-   output Iout1_d_d11_d1 ;
-   output Iout2_d_d21_d0 ;
-   output Iout1_d_d8_d0 ;
-   output Iout1_d_d23_d0 ;
-   output Iout1_d_d7_d1 ;
-   output Iout1_d_d10_d1 ;
-   output Iout1_d_d27_d0 ;
-   output Iout2_d_d4_d1 ;
-   wire Iin_d_d22_d0 ;
+   output Iout1_d_d24_d1 ;
+   wire Iin_d_d14_d0 ;
    output Iout1_d_d5_d0 ;
-   output Iout1_d_d29_d0 ;
+   output Iout2_d_d24_d0 ;
+   output Iout1_d_d14_d1 ;
+   output Iout2_d_d12_d1 ;
+   output Iout2_d_d14_d0 ;
+   output Iout2_d_d0_d1 ;
+   output Iout1_d_d16_d0 ;
+   wire _in_v ;
+   wire Iin_d_d9_d1 ;
+   wire Iin_d_d19_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d31_d0 ;
+   output Iout1_d_d19_d0 ;
+   output Iout2_d_d26_d1 ;
+   wire Iin_d_d10_d1 ;
+   output Iout1_d_d1_d0 ;
+   output Iout1_d_d21_d0 ;
+   output Iout1_d_d3_d1 ;
+   output Iout2_d_d15_d0 ;
+   output Iout2_d_d3_d1 ;
+   output Iout2_d_d2_d1 ;
+   wire reset_B;
+   output Iout1_d_d15_d1 ;
+   output Iout2_d_d24_d1 ;
+   wire _out1_a_B ;
+   wire Iin_d_d4_d1 ;
+   output Iout2_d_d27_d0 ;
+   wire Iin_d_d28_d0 ;
+   output Iout1_d_d7_d1 ;
+   output Iout2_d_d0_d0 ;
+   output Iout2_d_d19_d1 ;
+   wire Iin_d_d16_d0 ;
+   output Iout1_d_d12_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d12_d1 ;
+   output Iout1_d_d11_d1 ;
+   output Iout2_d_d21_d1 ;
+   wire Iin_d_d16_d1 ;
+   output Iout2_d_d19_d0 ;
+   output Iout2_d_d30_d1 ;
+   output Iout1_d_d3_d0 ;
+   output Iout2_d_d3_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d9_d0 ;
+   output Iout1_d_d6_d1 ;
+   output Iout2_d_d6_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d19_d0 ;
+   output Iout1_d_d28_d0 ;
+   output Iin_a ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d21_d1 ;
+   output Iout2_d_d5_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iout1_v ;
+   output Iout1_d_d20_d1 ;
+   wire Iin_d_d2_d1 ;
+   wire Iin_d_d27_d0 ;
+   output Iout2_d_d18_d0 ;
    output Iout2_d_d13_d0 ;
    output Iout2_d_d31_d1 ;
-   output Iout2_d_d1_d1 ;
+   output Iout2_d_d29_d1 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d14_d1 ;
+   output Iout1_d_d7_d0 ;
+   output Iout1_d_d18_d0 ;
+   output Iout1_d_d31_d0 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d27_d1 ;
+   wire Iin_d_d28_d1 ;
+   output Iout2_d_d29_d0 ;
    output Iout1_d_d26_d1 ;
-   output Iout1_d_d25_d1 ;
-   wire Iout2_en_buf_out0 ;
-   output Iout1_d_d26_d0 ;
-   output Iout1_d_d9_d1 ;
-   wire Iin_d_d7_d1 ;
-   wire Iin_d_d30_d1 ;
-   output Iout2_d_d22_d1 ;
-   output Iout1_d_d24_d1 ;
-   output Iout1_d_d23_d1 ;
-   output Iout2_d_d6_d0 ;
-   output Iout2_d_d10_d1 ;
-   output Iin_a ;
+   wire Iin_d_d15_d0 ;
+   output Iout1_d_d29_d0 ;
+   output Iout1_d_d12_d1 ;
+   output Iout2_d_d17_d1 ;
+   output Iout2_d_d1_d1 ;
+   output Iout1_d_d22_d1 ;
    wire Iin_d_d13_d0 ;
+   wire Iout2_en_buf_out0 ;
+   output Iout1_d_d6_d0 ;
+   output Iout2_d_d10_d0 ;
+   output Iout2_d_d25_d1 ;
+   output Iout2_d_d22_d1 ;
+   wire Iin_d_d20_d0 ;
+   output Iout1_d_d25_d1 ;
+   output Iout2_d_d11_d1 ;
+   output Iout2_d_d10_d1 ;
+   output Iout1_d_d23_d0 ;
+   output Iout2_d_d9_d1 ;
+   output Iout2_d_d4_d1 ;
+   wire Iin_d_d7_d0 ;
+   output Iout2_d_d4_d0 ;
+   wire Iin_d_d4_d0 ;
    wire Iin_d_d25_d0 ;
+   wire Iin_d_d26_d0 ;
+   output Iout1_d_d11_d0 ;
+   output Iout1_d_d17_d0 ;
+   wire Iin_d_d15_d1 ;
+   output Iout1_d_d9_d1 ;
+   output Iout2_d_d9_d0 ;
+   output Iout1_d_d28_d1 ;
+   output Iout1_d_d21_d1 ;
+   wire Iout2_v ;
+   output Iout1_d_d1_d1 ;
+   output Iout2_d_d5_d1 ;
+   output Iout1_d_d0_d0 ;
+   output Iout1_d_d13_d1 ;
+   output Iout1_d_d17_d1 ;
+   wire Iin_d_d31_d1 ;
+   wire Iin_d_d0_d0 ;
+   wire Iout2_a ;
+   output Iout1_d_d0_d1 ;
+   output Iout1_d_d19_d1 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d29_d1 ;
+   output Iout1_d_d4_d0 ;
+   output Iout1_d_d13_d0 ;
+   output Iout1_d_d15_d0 ;
+   output Iout2_d_d16_d0 ;
+   output Iout2_d_d20_d1 ;
+   wire Iout1_a ;
+   wire Iin_d_d6_d0 ;
+   output Iout2_d_d21_d0 ;
+   output Iin_v ;
+   output Iout1_d_d22_d0 ;
+   wire _reset_BX ;
+   wire Iin_d_d25_d1 ;
+   wire Iin_d_d30_d1 ;
+   output Iout1_d_d20_d0 ;
+   output Iout2_d_d28_d0 ;
+   output Iout2_d_d26_d0 ;
+   output Iout2_d_d28_d1 ;
+   output Iout1_d_d30_d1 ;
+   output Iout1_d_d27_d1 ;
+   wire Iin_d_d26_d1 ;
+   output Iout2_d_d15_d1 ;
+   wire Iin_d_d22_d0 ;
+   wire Iout1_a_B_buf_out0 ;
+   output Iout1_d_d14_d0 ;
+   output Iout2_d_d31_d0 ;
+   output Iout2_d_d25_d0 ;
+   output Iout2_d_d16_d1 ;
+   output Iout1_d_d10_d1 ;
+   output Iout1_d_d29_d1 ;
+   wire Iin_d_d7_d1 ;
+   wire Iin_d_d13_d1 ;
+   wire Iout1_en_buf_out0 ;
+   output Iout1_d_d16_d1 ;
+   output Iout2_d_d12_d0 ;
+   output Iout2_d_d27_d1 ;
+   output Iout1_d_d18_d1 ;
+   output Iout1_d_d8_d0 ;
+   output Iout2_d_d2_d0 ;
+   output Iout2_d_d1_d0 ;
+   output Iout1_d_d23_d1 ;
+   wire Iin_d_d2_d0 ;
+   wire Iin_d_d24_d1 ;
+   wire Iin_d_d30_d0 ;
+   wire _out2_a_B ;
+   output Iout1_d_d2_d1 ;
+   wire Iin_d_d17_d0 ;
+   output Iout1_d_d26_d0 ;
+   wire Iin_d_d1_d1 ;
+   output Iout1_d_d30_d0 ;
+   output Iout2_d_d23_d0 ;
+   output Iout2_d_d23_d1 ;
+   output Iout2_d_d7_d1 ;
+   output Iout1_d_d9_d0 ;
+   output Iout2_d_d30_d0 ;
+   output Iout2_d_d6_d0 ;
+   wire Iin_d_d5_d1 ;
+   output Iout2_d_d7_d0 ;
+   wire Iin_d_d12_d0 ;
+   wire Iin_d_d21_d0 ;
+   output Iout2_d_d18_d1 ;
+   output Iout1_d_d31_d1 ;
+   wire Iin_d_d18_d1 ;
+   output Iout2_d_d20_d0 ;
+   output Iout2_d_d8_d0 ;
+   wire Iin_d_d3_d1 ;
+   output Iout2_d_d17_d0 ;
+   wire Iin_d_d23_d0 ;
+   wire Iin_d_d24_d0 ;
+   output Iout1_d_d10_d0 ;
+   output Iout1_d_d27_d0 ;
+   output Iout2_d_d22_d0 ;
+   wire Iout2_a_B_buf_out0 ;
+   output Iout1_d_d4_d1 ;
+   output Iout1_d_d5_d1 ;
+   output Iout2_d_d11_d0 ;
+   wire Iin_d_d6_d1 ;
+   wire Iin_d_d23_d1 ;
+   wire Iin_d_d29_d0 ;
+   output Iout1_d_d24_d0 ;
+   output Iout2_d_d13_d1 ;
+   output Iout2_d_d8_d1 ;
+   wire I_reset_BXX0 ;
+   output Iout1_d_d25_d0 ;
+   output Iout1_d_d8_d1 ;
 
 // --- instances
 A_4C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout1_v ), .c4(Iout2_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0merge_332_4/netlist/verilog.v

@@ -202,220 +202,220 @@ module tmpl_0_0dataflow__neuro_0_0merge_332_4(Iin1_d_d0_d0 , Iin1_d_d0_d1 , Iin1
    input reset_B;
 
 // -- signals ---
-   wire Iin2_d_d16_d1 ;
-   output Iout_d_d28_d0 ;
-   wire I_out_temp_d_d0 ;
-   output Iout_d_d6_d0 ;
-   output Iout_d_d7_d0 ;
-   output Iout_d_d17_d0 ;
-   wire _in1_a_B ;
-   wire Iin1_d_d28_d1 ;
-   wire Iin1_d_d4_d0 ;
-   output Iout_d_d19_d1 ;
-   wire Iin2_d_d4_d1 ;
-   wire Iin2_d_d2_d0 ;
-   wire Iin1_d_d16_d0 ;
-   wire Iin2_d_d20_d0 ;
-   output Iout_d_d21_d0 ;
-   wire Iin1_d_d26_d0 ;
-   wire _out_a_B ;
-   output Iout_d_d26_d1 ;
-   output Iout_d_d9_d1 ;
-   output Iout_d_d14_d0 ;
-   wire Iin1_d_d14_d0 ;
-   wire Iin1_d_d8_d1 ;
-   wire Iin2_d_d28_d1 ;
-   output Iout_d_d0_d0 ;
-   wire _in2_arb ;
-   output Iout_d_d20_d0 ;
-   wire Iin1_d_d28_d0 ;
-   wire Iin2_d_d4_d0 ;
-   output Iin2_a ;
-   wire Iin2_d_d9_d1 ;
-   wire Iin2_d_d17_d1 ;
-   output Iout_d_d17_d1 ;
-   output Iout_d_d14_d1 ;
-   output Iout_d_d2_d1 ;
-   wire Iin2_d_d3_d0 ;
-   wire Iin2_d_d12_d0 ;
-   wire Iin2_d_d17_d0 ;
-   wire Iin2_d_d18_d0 ;
-   wire Iin2_d_d21_d0 ;
-   wire Iin1_d_d7_d1 ;
-   output Iout_d_d11_d0 ;
-   wire Iin1_d_d11_d0 ;
-   output Iout_d_d30_d1 ;
-   wire Iin1_d_d18_d0 ;
-   wire Iin2_d_d13_d1 ;
-   wire Iin2_d_d12_d1 ;
-   output Iout_d_d5_d0 ;
-   output Iout_d_d13_d0 ;
-   wire Iin2_d_d23_d1 ;
-   output Iout_d_d6_d1 ;
-   wire Iin1_d_d2_d0 ;
+   wire Iin1_d_d7_d0 ;
+   wire Iin1_d_d10_d0 ;
+   wire Iin2_d_d30_d0 ;
+   wire Iin2_d_d15_d1 ;
+   wire Iin2_d_d5_d0 ;
    wire _reset_BX ;
-   output Iout_d_d29_d1 ;
-   output Iout_d_d23_d1 ;
-   output Iout_d_d22_d1 ;
-   output Iout_d_d8_d1 ;
-   wire Iin1_d_d14_d1 ;
-   wire Iin1_d_d0_d0 ;
-   wire Iin2_d_d31_d0 ;
+   wire _in1_a_B ;
+   wire Iout_a ;
+   output Iout_d_d24_d0 ;
+   output Iout_d_d30_d0 ;
+   output Iout_d_d25_d1 ;
+   wire Iin2_d_d22_d1 ;
+   output Iout_d_d19_d1 ;
+   output Iout_d_d12_d0 ;
+   output Iout_d_d27_d0 ;
+   wire Iin2_d_d17_d0 ;
+   wire Iin1_d_d12_d1 ;
+   output Iout_d_d0_d0 ;
+   wire Iin2_d_d6_d0 ;
+   output Iin2_v ;
+   wire Iin1_d_d5_d0 ;
+   output Iout_d_d28_d0 ;
+   wire Iin1_d_d3_d1 ;
+   output Iout_d_d3_d1 ;
+   wire Iin1_d_d22_d1 ;
    output Iout_d_d1_d0 ;
+   wire Iin1_d_d17_d0 ;
+   wire Iin2_d_d14_d1 ;
+   wire Iin2_d_d2_d0 ;
+   wire Iin1_d_d13_d1 ;
+   output Iout_d_d0_d1 ;
+   wire Iin1_d_d28_d1 ;
+   wire Iin1_d_d25_d1 ;
+   output Iout_d_d11_d0 ;
+   wire _in2_arb ;
+   wire Iin1_d_d15_d1 ;
+   wire _in2_a_B ;
+   wire Iin1_d_d12_d0 ;
+   wire Iin1_d_d14_d1 ;
+   wire I_out_temp_d_d0 ;
+   output Iin1_a ;
+   output Iout_d_d9_d0 ;
+   wire Iin2_d_d18_d0 ;
+   wire Iin1_d_d20_d0 ;
+   wire _in1_arb_temp ;
+   output Iout_d_d9_d1 ;
+   wire Iin2_d_d13_d0 ;
+   output Iout_d_d2_d0 ;
+   wire Iin2_d_d19_d0 ;
+   wire Iin2_d_d28_d0 ;
+   output Iout_d_d29_d1 ;
+   wire Iin2_d_d12_d1 ;
+   wire Iin1_d_d21_d0 ;
+   output Iout_d_d23_d1 ;
+   output Iout_d_d14_d0 ;
+   wire Iin1_d_d23_d0 ;
+   wire Iin2_d_d30_d1 ;
+   wire Iin2_d_d0_d1 ;
+   wire Iin1_d_d31_d0 ;
+   output Iin1_v ;
+   wire Iin2_d_d1_d0 ;
+   output Iout_d_d13_d0 ;
+   output Iout_d_d25_d0 ;
+   wire Iin1_d_d18_d0 ;
+   wire Iin1_d_d7_d1 ;
+   wire Iin2_d_d13_d1 ;
+   wire Iin1_d_d24_d0 ;
    wire _in1_arb ;
    wire Iin1_d_d1_d1 ;
-   wire I_in2_arb_X0 ;
-   wire Iin2_d_d0_d0 ;
-   output Iout_d_d18_d0 ;
-   output Iout_d_d25_d0 ;
-   wire Iin2_d_d26_d0 ;
-   output Iout_d_d27_d0 ;
-   output Iout_d_d11_d1 ;
-   output Iout_d_d2_d0 ;
-   wire Iin2_d_d5_d0 ;
-   wire Iin1_d_d7_d0 ;
-   wire Iout_v ;
-   wire Iin2_d_d25_d1 ;
-   output Iout_d_d16_d1 ;
-   output Iout_d_d15_d0 ;
-   wire Iin2_d_d27_d0 ;
-   wire Iin2_d_d28_d0 ;
-   wire Iin1_d_d13_d1 ;
-   output Iout_d_d28_d1 ;
-   wire Iin2_d_d27_d1 ;
-   wire Iin2_d_d1_d1 ;
-   wire Iin1_d_d0_d1 ;
-   wire Iin2_d_d21_d1 ;
-   wire Iin1_d_d21_d0 ;
-   output Iin2_v ;
-   wire Iin2_d_d29_d1 ;
-   wire Iin2_d_d22_d1 ;
-   wire Iin2_d_d6_d1 ;
-   output Iout_d_d1_d1 ;
-   wire Iin1_d_d20_d0 ;
-   wire Iin2_d_d11_d1 ;
-   output Iin1_v ;
-   wire Iin1_d_d26_d1 ;
-   wire Iin1_d_d12_d0 ;
-   wire Iin2_d_d13_d0 ;
-   wire _in1_arb_temp ;
-   wire Iin1_d_d16_d1 ;
    output Iout_d_d12_d1 ;
-   wire Iin1_d_d4_d1 ;
-   output Iout_d_d4_d1 ;
-   wire I_out_a_BX0 ;
-   wire Iin1_d_d5_d0 ;
-   wire Iin2_d_d18_d1 ;
-   wire Iin1_d_d3_d0 ;
-   output Iout_d_d29_d0 ;
-   wire _in2_a_B ;
-   output Iout_d_d0_d1 ;
-   wire I_in1_arb_X0 ;
-   wire Iin1_d_d8_d0 ;
-   output Iout_d_d30_d0 ;
-   wire Iin1_d_d21_d1 ;
-   wire Iin1_d_d19_d1 ;
-   output Iout_d_d23_d0 ;
-   wire Iin2_d_d24_d0 ;
+   wire Iin1_d_d2_d0 ;
    wire Iin1_d_d18_d1 ;
-   wire Iin2_d_d14_d0 ;
-   output Iout_d_d10_d1 ;
-   wire Iin2_d_d23_d0 ;
-   wire Iin1_d_d30_d0 ;
-   output Iout_d_d15_d1 ;
-   wire Iin1_d_d25_d1 ;
-   output Iout_d_d8_d0 ;
-   output Iout_d_d12_d0 ;
    output Iout_d_d24_d1 ;
-   output Iout_d_d21_d1 ;
-   wire Iin2_d_d30_d0 ;
-   wire Iin1_d_d23_d0 ;
-   wire Iin1_d_d25_d0 ;
-   output Iout_d_d31_d1 ;
-   wire Iin1_d_d9_d0 ;
-   wire Iin1_d_d10_d0 ;
-   output Iout_d_d25_d1 ;
-   wire I_reset_BXX0 ;
-   output Iout_d_d7_d1 ;
-   wire Iin2_d_d10_d0 ;
-   output Iout_d_d19_d0 ;
-   wire Iin1_d_d6_d1 ;
-   output Iout_d_d4_d0 ;
-   wire Iin1_d_d3_d1 ;
-   wire Iin1_d_d23_d1 ;
-   wire Iin2_d_d24_d1 ;
-   wire Iin2_d_d3_d1 ;
-   wire Iin2_d_d8_d0 ;
-   wire Iin2_d_d9_d0 ;
-   output Iout_d_d22_d0 ;
-   wire Iin1_d_d10_d1 ;
-   wire Iin1_d_d11_d1 ;
-   wire Iin2_d_d19_d1 ;
-   output Iout_d_d16_d0 ;
-   wire Iin2_d_d16_d0 ;
-   wire Iin2_d_d15_d1 ;
-   wire Iin2_d_d14_d1 ;
-   output Iout_d_d3_d1 ;
-   wire Iin1_d_d19_d0 ;
-   wire Iin1_d_d31_d0 ;
-   wire Iin2_d_d20_d1 ;
-   wire Iin2_d_d8_d1 ;
-   wire Iin1_d_d1_d0 ;
-   wire _in2_arb_temp ;
-   output Iout_d_d27_d1 ;
-   wire Iin2_d_d5_d1 ;
-   wire Iin1_d_d20_d1 ;
-   wire Iin1_d_d27_d0 ;
-   wire Iin1_d_d31_d1 ;
-   wire _en ;
-   wire reset_B;
-   output Iout_d_d18_d1 ;
-   wire Iin1_d_d6_d0 ;
-   output Iout_d_d10_d0 ;
-   wire Iin2_d_d0_d1 ;
-   wire Iin1_d_d22_d1 ;
-   wire Iin2_d_d11_d0 ;
-   wire Iin1_d_d5_d1 ;
-   wire Iin2_d_d26_d1 ;
-   wire Iin1_d_d30_d1 ;
-   wire Iin2_d_d22_d0 ;
-   wire Iin1_d_d12_d1 ;
-   wire Iin2_d_d10_d1 ;
-   output Iout_d_d5_d1 ;
+   output Iout_d_d10_d1 ;
+   wire Iin2_d_d27_d1 ;
    wire Iin1_d_d27_d1 ;
-   wire Iin2_d_d1_d0 ;
-   wire Iin2_d_d29_d0 ;
+   output Iout_d_d8_d0 ;
+   output Iout_d_d23_d0 ;
+   output Iout_d_d29_d0 ;
    wire Iin1_d_d2_d1 ;
-   wire Iout_a ;
+   wire Iin2_d_d20_d1 ;
+   wire Iin2_d_d11_d0 ;
+   wire I_out_a_BX0 ;
+   wire Iin2_d_d23_d0 ;
+   wire Iin1_d_d27_d0 ;
    wire Iin2_d_d7_d1 ;
    output Iout_d_d3_d0 ;
-   wire Iin2_d_d7_d0 ;
-   wire Iin1_d_d22_d0 ;
-   wire Iin2_d_d25_d0 ;
-   output Iin1_a ;
-   wire Iin2_d_d15_d0 ;
-   wire Iin1_d_d17_d0 ;
-   output Iout_d_d26_d0 ;
-   wire Iin2_d_d31_d1 ;
-   wire Iin2_d_d30_d1 ;
-   wire Iin1_d_d24_d1 ;
-   wire Iin2_d_d6_d0 ;
-   wire Iin1_d_d13_d0 ;
-   output Iout_d_d31_d0 ;
+   wire reset_B;
+   wire Iin2_d_d26_d1 ;
+   output Iout_d_d4_d1 ;
+   output Iout_d_d2_d1 ;
+   output Iout_d_d22_d0 ;
    wire Iin1_d_d9_d1 ;
-   output Iout_d_d24_d0 ;
-   output Iout_d_d20_d1 ;
-   wire Iin1_d_d29_d1 ;
-   wire Iin1_d_d15_d1 ;
-   wire I_en_X0 ;
-   output Iout_d_d9_d0 ;
-   wire Iin1_d_d15_d0 ;
+   output Iout_d_d15_d1 ;
+   wire Iin2_d_d10_d1 ;
+   wire Iin1_d_d22_d0 ;
+   wire Iin2_d_d26_d0 ;
+   wire Iin2_d_d29_d1 ;
+   output Iout_d_d18_d1 ;
+   wire Iin2_d_d3_d1 ;
+   wire Iin2_d_d12_d0 ;
+   wire Iout_v ;
+   wire Iin2_d_d1_d1 ;
+   output Iout_d_d11_d1 ;
+   wire I_in1_arb_X0 ;
+   wire Iin1_d_d1_d0 ;
+   output Iout_d_d20_d0 ;
+   output Iout_d_d21_d1 ;
+   output Iout_d_d8_d1 ;
+   output Iout_d_d10_d0 ;
+   wire Iin2_d_d23_d1 ;
+   wire Iin2_d_d19_d1 ;
+   wire Iin1_d_d26_d1 ;
+   wire Iin1_d_d20_d1 ;
+   wire Iin1_d_d3_d0 ;
+   wire _in2_arb_temp ;
+   wire Iin1_d_d11_d0 ;
+   wire Iin2_d_d21_d0 ;
+   wire Iin2_d_d31_d1 ;
+   output Iout_d_d31_d1 ;
+   wire Iin1_d_d31_d1 ;
+   wire Iin1_d_d16_d0 ;
+   wire Iin1_d_d26_d0 ;
+   output Iout_d_d30_d1 ;
+   output Iout_d_d27_d1 ;
+   wire Iin2_d_d15_d0 ;
+   wire Iin2_d_d16_d0 ;
+   wire Iin2_d_d21_d1 ;
+   wire Iin2_d_d0_d0 ;
+   wire Iin1_d_d5_d1 ;
+   wire Iin1_d_d11_d1 ;
+   wire Iin1_d_d4_d0 ;
+   wire Iin2_d_d7_d0 ;
+   wire Iin2_d_d8_d0 ;
+   output Iout_d_d22_d1 ;
+   wire Iin2_d_d11_d1 ;
+   wire Iin2_d_d3_d0 ;
+   wire Iin2_d_d24_d0 ;
+   output Iout_d_d31_d0 ;
    output Iout_d_d13_d1 ;
-   wire Iin2_d_d2_d1 ;
-   wire Iin2_d_d19_d0 ;
-   wire Iin1_d_d24_d0 ;
    wire Iin1_d_d29_d0 ;
+   wire _en ;
+   wire Iin1_d_d6_d1 ;
+   output Iout_d_d28_d1 ;
+   wire Iin2_d_d5_d1 ;
+   output Iout_d_d19_d0 ;
+   output Iout_d_d26_d0 ;
+   output Iin2_a ;
+   output Iout_d_d21_d0 ;
+   wire _out_a_B ;
+   wire Iin2_d_d18_d1 ;
+   output Iout_d_d6_d1 ;
+   wire I_in2_arb_X0 ;
+   wire Iin1_d_d30_d1 ;
+   wire Iin1_d_d29_d1 ;
+   wire I_en_X0 ;
+   wire Iin2_d_d14_d0 ;
+   wire Iin1_d_d16_d1 ;
+   wire Iin2_d_d25_d0 ;
+   wire Iin2_d_d31_d0 ;
+   wire Iin2_d_d28_d1 ;
+   output Iout_d_d16_d1 ;
+   output Iout_d_d7_d0 ;
+   wire Iin1_d_d28_d0 ;
    wire Iin1_d_d17_d1 ;
+   wire Iin1_d_d19_d1 ;
+   wire Iin1_d_d21_d1 ;
+   wire Iin1_d_d0_d1 ;
+   output Iout_d_d5_d1 ;
+   output Iout_d_d1_d1 ;
+   wire Iin1_d_d8_d0 ;
+   wire Iin2_d_d20_d0 ;
+   wire Iin1_d_d4_d1 ;
+   wire Iin2_d_d25_d1 ;
+   wire Iin2_d_d24_d1 ;
+   output Iout_d_d7_d1 ;
+   wire Iin2_d_d2_d1 ;
+   wire Iin1_d_d13_d0 ;
+   output Iout_d_d14_d1 ;
+   wire Iin2_d_d6_d1 ;
+   wire Iin2_d_d17_d1 ;
+   wire Iin2_d_d16_d1 ;
+   wire Iin1_d_d23_d1 ;
+   wire Iin2_d_d22_d0 ;
+   wire Iin1_d_d19_d0 ;
+   output Iout_d_d5_d0 ;
+   wire Iin2_d_d4_d0 ;
+   wire Iin1_d_d9_d0 ;
+   output Iout_d_d18_d0 ;
+   wire Iin2_d_d8_d1 ;
+   wire Iin1_d_d0_d0 ;
+   output Iout_d_d6_d0 ;
+   wire Iin1_d_d6_d0 ;
+   output Iout_d_d15_d0 ;
+   wire Iin1_d_d25_d0 ;
+   output Iout_d_d17_d1 ;
+   wire Iin1_d_d15_d0 ;
+   output Iout_d_d17_d0 ;
+   wire Iin1_d_d8_d1 ;
+   output Iout_d_d26_d1 ;
+   wire Iin2_d_d9_d1 ;
+   output Iout_d_d4_d0 ;
+   output Iout_d_d16_d0 ;
+   wire Iin2_d_d4_d1 ;
+   wire Iin1_d_d24_d1 ;
+   wire Iin2_d_d9_d0 ;
+   wire Iin2_d_d10_d0 ;
+   wire Iin1_d_d14_d0 ;
+   wire Iin2_d_d27_d0 ;
+   wire Iin2_d_d29_d0 ;
+   wire Iin1_d_d10_d1 ;
+   output Iout_d_d20_d1 ;
+   wire I_reset_BXX0 ;
+   wire Iin1_d_d30_d0 ;
 
 // --- instances
 A_2C2N2N_RB_X1 Imerge_func_f0  (.y(Iout_d_d0_d0 ), .c1(I_en_X0 ), .c2(I_out_a_BX0 ), .na1(I_in1_arb_X0 ), .na2(Iin1_d_d0_d0 ), .nb1(I_in2_arb_X0 ), .nb2(Iin2_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__hs__2d/netlist/verilog.v

@@ -10,19 +10,19 @@ module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(Iin_d_d0 , Iin_a , Ioutx_d_d0 , Io
    input reset_B;
 
 // -- signals ---
-   output Ioutx_d_d0 ;
+   wire _en ;
    wire _y_a_B ;
+   wire _req ;
+   wire Iin_d_d0 ;
    wire Ioutx_a ;
-   wire _reqB ;
-   wire _reset_BX ;
+   output Iouty_d_d0 ;
+   wire Iouty_a ;
+   output Ioutx_d_d0 ;
    wire reset_B;
    output Iin_a ;
-   wire Iouty_a ;
-   wire Iin_d_d0 ;
-   wire _en ;
-   wire _req ;
    wire _x_a_B ;
-   output Iouty_d_d0 ;
+   wire _reqB ;
+   wire _reset_BX ;
 
 // --- instances
 INV_X1 Ireq_inv  (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4/netlist/verilog.v

@@ -268,278 +268,278 @@ module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d__array_315_76_4(Iin0_d_d0 , Iin0_a
    input reset_B;
 
 // -- signals ---
-   output Ioutx7_d_d0 ;
-   output Iin42_a ;
-   wire Iin52_d_d0 ;
-   wire Iin29_d_d0 ;
-   output Ioutx2_d_d0 ;
-   wire Iin70_d_d0 ;
-   wire Iin77_d_d0 ;
-   wire Ioutx6_a ;
-   wire Ioutx14_a ;
-   wire Iin0_d_d0 ;
-   output Ito_pd_x2_a ;
-   output Iin9_a ;
-   output Iin3_a ;
-   wire Iin84_d_d0 ;
-   output Iin43_a ;
-   wire Iin11_d_d0 ;
-   output Ioutx10_d_d0 ;
-   wire Iin69_d_d0 ;
-   output Iouty5_d_d0 ;
-   output Ito_pd_x5_d_d0 ;
-   output Iin50_a ;
-   wire Ioutx9_a ;
-   output Iin23_a ;
-   wire Iin13_d_d0 ;
-   wire Iin37_d_d0 ;
-   output Iin66_a ;
-   output Iin86_a ;
-   wire Iin32_d_d0 ;
-   output Ito_pd_x7_d_d0 ;
-   output Ito_pd_y4_d_d0 ;
-   wire Iin22_d_d0 ;
-   output Iin30_a ;
-   output Iin67_a ;
-   output Iin18_a ;
-   output Ito_pd_x1_d_d0 ;
-   wire Iin43_d_d0 ;
-   output Ito_pd_x14_a ;
-   wire Iin2_d_d0 ;
-   output Ito_pd_x12_d_d0 ;
-   wire Ineurons89_reset_B ;
-   output Iin5_a ;
-   wire Iin44_d_d0 ;
-   output Iin29_a ;
-   output Iin56_a ;
-   output Iin61_a ;
-   wire Iin80_d_d0 ;
-   wire Iin1_d_d0 ;
-   output Iin33_a ;
-   output Iin49_a ;
-   wire Iin36_d_d0 ;
-   output Iin51_a ;
-   output Iin62_a ;
-   wire Iin17_d_d0 ;
-   output Ito_pd_x10_a ;
-   output Iin4_a ;
-   output Iin76_a ;
-   output Ito_pd_x4_a ;
-   output Ito_pd_x8_d_d0 ;
-   output Iin78_a ;
-   output Iin17_a ;
-   output Iin7_a ;
-   output Ito_pd_x1_a ;
-   wire Iouty0_a ;
-   output Iin48_a ;
-   wire Iin72_d_d0 ;
-   output Ito_pd_x11_d_d0 ;
-   output Ito_pd_x9_d_d0 ;
-   output Iin52_a ;
-   output Iin20_a ;
-   wire Ineurons29_reset_B ;
-   output Iin44_a ;
-   output Iin88_a ;
-   output Iin28_a ;
-   wire Iin38_d_d0 ;
-   output Iin57_a ;
-   wire Iin60_d_d0 ;
-   output Iouty4_d_d0 ;
-   wire Iin9_d_d0 ;
-   output Iin72_a ;
-   output Ito_pd_y2_a ;
-   output Iin79_a ;
-   wire Iin88_d_d0 ;
-   output Ito_pd_y1_d_d0 ;
-   output Ioutx4_d_d0 ;
-   wire Iin71_d_d0 ;
-   output Iin1_a ;
-   output Ito_pd_y1_a ;
-   output Iin65_a ;
-   wire Iin89_d_d0 ;
-   wire Ioutx5_a ;
-   output Iin26_a ;
-   wire Iin12_d_d0 ;
-   wire Iin41_d_d0 ;
-   output Iin16_a ;
-   output Ito_pd_x3_a ;
-   output Iouty3_d_d0 ;
-   wire Iin16_d_d0 ;
-   wire Iin49_d_d0 ;
-   wire Iin57_d_d0 ;
-   output Ito_pd_y5_d_d0 ;
-   wire Ioutx2_a ;
-   wire Iin5_d_d0 ;
-   output Iin59_a ;
-   output Ito_pd_y0_a ;
-   wire Iin42_d_d0 ;
-   wire Ioutx13_a ;
-   output Iin27_a ;
-   wire Iin34_d_d0 ;
-   wire Iin26_d_d0 ;
-   output Iin36_a ;
-   wire Iin68_d_d0 ;
-   output Ito_pd_y0_d_d0 ;
-   output Iin55_a ;
-   output Ioutx8_d_d0 ;
-   wire Iin40_d_d0 ;
-   wire Iin67_d_d0 ;
-   output Ito_pd_x12_a ;
-   output Iin11_a ;
-   output Ito_pd_y3_a ;
-   output Ioutx0_d_d0 ;
    wire Iin75_d_d0 ;
-   output Ioutx13_d_d0 ;
-   wire Iin58_d_d0 ;
-   output Iin58_a ;
-   output Iin74_a ;
-   wire reset_B;
-   output Ito_pd_x14_d_d0 ;
-   wire Iin55_d_d0 ;
-   wire Ioutx0_a ;
-   wire Iin81_d_d0 ;
-   wire Iouty5_a ;
-   output Ioutx14_d_d0 ;
-   wire Iin65_d_d0 ;
-   output Iin87_a ;
-   output Iin0_a ;
-   output Ioutx3_d_d0 ;
-   wire Iin48_d_d0 ;
-   output Iin64_a ;
-   wire Iin45_d_d0 ;
-   wire Iin53_d_d0 ;
-   wire Iin33_d_d0 ;
-   wire Iin62_d_d0 ;
-   output Ioutx5_d_d0 ;
-   wire Iin50_d_d0 ;
-   wire Iin8_d_d0 ;
-   output Ito_pd_x5_a ;
-   output Iin39_a ;
-   wire Iin47_d_d0 ;
-   output Iin53_a ;
-   output Iin41_a ;
-   wire Iin14_d_d0 ;
-   output Ito_pd_x6_a ;
-   wire Iin4_d_d0 ;
-   output Ioutx12_d_d0 ;
-   wire Iin63_d_d0 ;
-   wire Iouty1_a ;
-   output Ito_pd_x2_d_d0 ;
-   wire Iin21_d_d0 ;
-   output Iin45_a ;
-   wire Iin7_d_d0 ;
-   output Iin31_a ;
-   output Iin47_a ;
-   output Iin80_a ;
-   output Ito_pd_x13_a ;
-   output Iin10_a ;
-   wire Iin3_d_d0 ;
-   output Iin32_a ;
-   wire Iin25_d_d0 ;
-   output Ito_pd_x13_d_d0 ;
-   wire Iin30_d_d0 ;
-   output Iin12_a ;
-   wire Ineurons14_reset_B ;
-   output Iin63_a ;
-   wire Ioutx10_a ;
-   wire Iin19_d_d0 ;
-   output Ito_pd_x9_a ;
-   output Ioutx6_d_d0 ;
-   wire Iin73_d_d0 ;
-   wire Iin18_d_d0 ;
-   output Iin8_a ;
-   output Iin75_a ;
-   output Iin83_a ;
-   output Ito_pd_x0_d_d0 ;
-   output Ito_pd_x7_a ;
-   wire Iin39_d_d0 ;
-   wire Iin6_d_d0 ;
-   wire Iin66_d_d0 ;
-   output Ito_pd_x11_a ;
-   output Iin71_a ;
-   wire Iin76_d_d0 ;
-   output Ioutx11_d_d0 ;
-   wire Iin56_d_d0 ;
-   wire Irsb5_in ;
-   wire Iouty4_a ;
-   wire Ineurons59_reset_B ;
-   output Iin54_a ;
-   output Iin19_a ;
-   wire Iin35_d_d0 ;
-   output Iin40_a ;
-   output Ito_pd_y2_d_d0 ;
-   output Iin15_a ;
-   output Iin60_a ;
-   output Iin6_a ;
-   wire Iin51_d_d0 ;
-   wire Iin59_d_d0 ;
-   output Iouty0_d_d0 ;
-   wire Ioutx4_a ;
    wire Iin23_d_d0 ;
-   output Iin35_a ;
-   wire Iin15_d_d0 ;
-   output Ito_pd_x4_d_d0 ;
-   output Iin69_a ;
-   wire Ineurons44_reset_B ;
-   output Ito_pd_x3_d_d0 ;
-   output Iin70_a ;
-   wire Iin28_d_d0 ;
-   output Ito_pd_y5_a ;
-   output Iin73_a ;
-   wire Iouty3_a ;
-   output Iin37_a ;
-   output Ito_pd_y3_d_d0 ;
-   output Iin21_a ;
-   wire Iin83_d_d0 ;
-   wire Ioutx1_a ;
-   output Ioutx9_d_d0 ;
-   wire Iin54_d_d0 ;
-   wire Ioutx8_a ;
-   output Iin38_a ;
-   wire Iin27_d_d0 ;
-   output Ito_pd_x8_a ;
-   output Iin25_a ;
-   output Iin13_a ;
-   wire Iouty2_a ;
+   wire Iin85_d_d0 ;
+   wire Iin6_d_d0 ;
+   output Iin75_a ;
    output Iin77_a ;
-   output Ito_pd_x6_d_d0 ;
-   wire Ioutx3_a ;
-   wire Iin31_d_d0 ;
-   output Ito_pd_y4_a ;
-   wire Iin61_d_d0 ;
+   output Iin49_a ;
+   output Iin83_a ;
+   output Iin23_a ;
    output Iouty2_d_d0 ;
-   wire Iin74_d_d0 ;
-   wire Iin87_d_d0 ;
+   wire Iouty0_a ;
+   wire Iin60_d_d0 ;
+   wire Ioutx2_a ;
+   output Iin68_a ;
+   output Ito_pd_x0_d_d0 ;
+   output Ito_pd_x1_d_d0 ;
+   wire Iin56_d_d0 ;
+   output Ioutx14_d_d0 ;
+   output Iin37_a ;
+   wire Iin31_d_d0 ;
+   output Iin34_a ;
+   wire Iin1_d_d0 ;
+   output Ito_pd_y4_a ;
+   wire Iin49_d_d0 ;
+   wire Iin86_d_d0 ;
+   wire Iin18_d_d0 ;
+   wire Ineurons29_reset_B ;
+   output Iin42_a ;
+   output Iin65_a ;
+   output Ito_pd_x3_a ;
+   output Ioutx10_d_d0 ;
+   output Iin35_a ;
+   output Iin52_a ;
+   wire reset_B;
+   wire Iin32_d_d0 ;
+   output Iin39_a ;
+   output Iin62_a ;
+   output Iouty1_d_d0 ;
+   wire Iin11_d_d0 ;
+   output Ioutx2_d_d0 ;
+   output Iin40_a ;
+   wire Ioutx9_a ;
+   output Ioutx8_d_d0 ;
+   output Iin57_a ;
+   output Iin73_a ;
+   output Iin1_a ;
+   wire Iouty2_a ;
+   output Ito_pd_x10_d_d0 ;
+   wire Iin22_d_d0 ;
+   output Iin17_a ;
+   output Iin5_a ;
+   output Ito_pd_y5_a ;
+   wire Iin39_d_d0 ;
+   output Iin22_a ;
+   output Ito_pd_x2_a ;
+   wire Iin34_d_d0 ;
+   output Ito_pd_x11_d_d0 ;
+   output Ito_pd_x7_d_d0 ;
+   wire Iin42_d_d0 ;
+   wire Iin46_d_d0 ;
+   wire Iin15_d_d0 ;
+   wire Iin36_d_d0 ;
+   output Iin72_a ;
+   output Ito_pd_x4_a ;
+   wire Ioutx11_a ;
+   output Ito_pd_x12_a ;
+   output Iin16_a ;
+   wire Ineurons14_reset_B ;
+   wire Ioutx4_a ;
+   wire Iin27_d_d0 ;
+   output Ito_pd_x6_a ;
+   wire Iin83_d_d0 ;
+   output Iin29_a ;
+   output Ioutx13_d_d0 ;
+   wire Iin55_d_d0 ;
+   output Ioutx1_d_d0 ;
+   output Ito_pd_y0_d_d0 ;
+   wire Iin79_d_d0 ;
+   wire Iin81_d_d0 ;
+   output Iin38_a ;
+   output Iouty4_d_d0 ;
+   wire Iin41_d_d0 ;
+   output Iin30_a ;
+   output Ito_pd_x8_d_d0 ;
    output Iin89_a ;
+   wire Iin71_d_d0 ;
+   output Iin28_a ;
+   output Iin60_a ;
+   output Iin63_a ;
+   wire Iin78_d_d0 ;
+   output Iin55_a ;
+   wire Iin76_d_d0 ;
+   wire Ioutx8_a ;
+   output Ito_pd_y1_d_d0 ;
+   wire Iin37_d_d0 ;
+   output Iin4_a ;
+   wire Iin59_d_d0 ;
    wire Iin20_d_d0 ;
-   output Iin14_a ;
+   output Ito_pd_y2_a ;
+   wire Iin33_d_d0 ;
+   wire Ineurons44_reset_B ;
+   wire Iin87_d_d0 ;
+   wire Iin24_d_d0 ;
+   output Ito_pd_x11_a ;
+   output Ito_pd_y1_a ;
+   output Ioutx0_d_d0 ;
+   wire Iin69_d_d0 ;
+   output Iin24_a ;
+   output Iin8_a ;
+   wire Iin68_d_d0 ;
+   wire Ineurons89_reset_B ;
+   output Iin43_a ;
+   wire Iin29_d_d0 ;
+   output Iin12_a ;
+   output Iin10_a ;
+   output Iin84_a ;
+   output Ito_pd_x4_d_d0 ;
+   output Iin61_a ;
+   output Ito_pd_x7_a ;
+   output Ito_pd_x13_d_d0 ;
+   wire Iin44_d_d0 ;
+   output Iin58_a ;
+   wire Iin74_d_d0 ;
+   output Iin76_a ;
+   wire Iin77_d_d0 ;
+   wire Iin10_d_d0 ;
+   output Iin54_a ;
+   output Iin51_a ;
+   wire Iin58_d_d0 ;
+   output Ito_pd_y5_d_d0 ;
+   output Iin87_a ;
+   output Iin21_a ;
+   output Iin13_a ;
+   output Iin79_a ;
+   output Iouty0_d_d0 ;
+   wire Ioutx13_a ;
+   output Iin26_a ;
+   output Iin88_a ;
+   output Ito_pd_x5_a ;
+   wire Iin80_d_d0 ;
+   output Iin66_a ;
+   wire Iin73_d_d0 ;
+   wire Ioutx7_a ;
+   output Iin2_a ;
+   output Ito_pd_x12_d_d0 ;
+   wire Iin67_d_d0 ;
+   wire Irsb5_in ;
+   wire Ineurons59_reset_B ;
+   wire Ioutx10_a ;
+   wire Iin8_d_d0 ;
    output Iin46_a ;
    wire Iin64_d_d0 ;
-   output Ioutx1_d_d0 ;
-   wire Iin46_d_d0 ;
-   output Iin68_a ;
-   output Iin81_a ;
-   wire Ioutx12_a ;
-   output Iin22_a ;
-   output Ito_pd_x10_d_d0 ;
-   wire Ineurons74_reset_B ;
-   wire Ioutx7_a ;
-   wire Iin85_d_d0 ;
+   wire Iin19_d_d0 ;
+   wire Iin66_d_d0 ;
+   output Ioutx6_d_d0 ;
+   wire Iin0_d_d0 ;
+   output Ito_pd_y3_a ;
+   output Iin3_a ;
+   wire Iin65_d_d0 ;
+   wire Ioutx0_a ;
+   output Ito_pd_x1_a ;
+   output Ito_pd_y0_a ;
+   wire Iin88_d_d0 ;
+   output Ito_pd_x5_d_d0 ;
+   wire Iin47_d_d0 ;
+   wire Iin52_d_d0 ;
+   output Iin53_a ;
+   output Ito_pd_x2_d_d0 ;
+   wire Iin45_d_d0 ;
+   output Iin74_a ;
+   wire Ioutx5_a ;
    output Iin85_a ;
-   output Iin84_a ;
-   output Iin82_a ;
-   output Iin24_a ;
-   wire Iin78_d_d0 ;
+   output Ito_pd_x14_d_d0 ;
+   output Ito_pd_y4_d_d0 ;
+   wire Iin70_d_d0 ;
+   output Iin70_a ;
+   output Iin18_a ;
+   wire Iin84_d_d0 ;
+   wire Iin2_d_d0 ;
+   output Ito_pd_x9_a ;
+   output Ioutx12_d_d0 ;
+   output Iin59_a ;
+   output Iin14_a ;
+   wire Iin26_d_d0 ;
+   output Iin20_a ;
+   wire Ioutx3_a ;
+   wire Ioutx1_a ;
+   wire Iouty4_a ;
+   wire Iin40_d_d0 ;
+   output Ito_pd_y3_d_d0 ;
+   output Iin48_a ;
+   wire Iin21_d_d0 ;
+   output Iin50_a ;
+   wire Iin38_d_d0 ;
+   output Iin6_a ;
+   output Ioutx3_d_d0 ;
+   output Iin19_a ;
+   output Ioutx7_d_d0 ;
+   wire Iin63_d_d0 ;
+   wire Iin5_d_d0 ;
+   output Ito_pd_x9_d_d0 ;
+   wire Iin48_d_d0 ;
+   wire Iin13_d_d0 ;
+   output Iin11_a ;
+   output Ioutx9_d_d0 ;
+   output Iouty5_d_d0 ;
+   output Iin78_a ;
+   output Iin36_a ;
+   wire Iin62_d_d0 ;
+   output Iin64_a ;
+   wire Iouty1_a ;
    wire Iin82_d_d0 ;
-   output Iouty1_d_d0 ;
-   wire Iin10_d_d0 ;
-   output Iin34_a ;
-   wire Ioutx11_a ;
-   wire Iin24_d_d0 ;
-   output Iin2_a ;
+   output Iin86_a ;
+   wire Iin14_d_d0 ;
+   output Iin44_a ;
+   wire Iin4_d_d0 ;
+   output Ito_pd_y2_d_d0 ;
+   output Iin0_a ;
+   output Ioutx5_d_d0 ;
+   output Iin45_a ;
+   output Iin71_a ;
+   output Iin81_a ;
+   wire Iin53_d_d0 ;
+   wire Iin17_d_d0 ;
+   output Iin67_a ;
+   output Ioutx11_d_d0 ;
+   output Iouty3_d_d0 ;
+   output Ito_pd_x10_a ;
+   output Iin41_a ;
+   wire Ioutx6_a ;
+   output Ito_pd_x3_d_d0 ;
+   output Iin33_a ;
+   wire Iin50_d_d0 ;
+   output Iin69_a ;
+   wire Iouty3_a ;
+   output Iin31_a ;
+   wire Iin16_d_d0 ;
+   output Iin15_a ;
+   wire Iin89_d_d0 ;
+   output Iin27_a ;
+   output Ito_pd_x6_d_d0 ;
+   output Iin7_a ;
+   output Iin47_a ;
+   wire Iin51_d_d0 ;
+   wire Iin57_d_d0 ;
+   wire Ioutx12_a ;
+   output Iin56_a ;
+   output Ito_pd_x14_a ;
+   wire Iin61_d_d0 ;
+   output Ito_pd_x13_a ;
+   output Ito_pd_x8_a ;
+   wire Ioutx14_a ;
+   wire Iin54_d_d0 ;
+   wire Iin72_d_d0 ;
+   output Ioutx4_d_d0 ;
+   wire Iin25_d_d0 ;
+   wire Iin43_d_d0 ;
+   wire Ineurons74_reset_B ;
+   wire Iin12_d_d0 ;
+   wire Iin3_d_d0 ;
+   wire Iin28_d_d0 ;
+   output Iin9_a ;
+   output Iin82_a ;
+   output Iin32_a ;
+   wire Iin9_d_d0 ;
+   wire Iouty5_a ;
+   output Iin80_a ;
+   output Iin25_a ;
+   wire Iin35_d_d0 ;
+   wire Iin30_d_d0 ;
+   wire Iin7_d_d0 ;
    output Ito_pd_x0_a ;
-   wire Iin79_d_d0 ;
-   wire Iin86_d_d0 ;
 
 // --- instances
 BUF_X4 Iout_req_buf_x0  (.y(Ioutx0_d_d0 ), .a(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down/netlist/verilog.v

@@ -7,12 +7,12 @@ module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, Isuppl
    output out;
 
 // -- signals ---
-   wire Itiehi_y ;
-   wire Iinv_y ;
-   wire in;
    wire reset_B;
-   wire Isupply_vdd ;
+   wire in;
    wire out ;
+   wire Isupply_vdd ;
+   wire Iinv_y ;
+   wire Itiehi_y ;
 
 // --- instances
 A_2N_U_X4 Ipull_down  (.n1(in), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_315_4/netlist/verilog.v

@@ -20,30 +20,30 @@ module tmpl_0_0dataflow__neuro_0_0ortree_315_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
 
 // -- signals ---
    wire Iin4 ;
-   wire Itmp24 ;
-   wire Itmp18 ;
-   wire Iin0 ;
+   wire Iin7 ;
+   wire Iin13 ;
+   wire Itmp17 ;
+   wire Iin2 ;
+   wire Itmp20 ;
+   wire Iin8 ;
+   wire Itmp15 ;
    wire Itmp16 ;
-   wire Itmp21 ;
-   wire Iin6 ;
-   wire Iin3 ;
+   wire Iin5 ;
    wire out ;
    wire Iin9 ;
-   wire Iin5 ;
-   wire Iin1 ;
-   wire Iin8 ;
-   wire Itmp17 ;
-   wire Itmp22 ;
-   wire Iin11 ;
-   wire Iin2 ;
-   wire Itmp23 ;
+   wire Itmp18 ;
    wire Iin10 ;
-   wire Itmp20 ;
+   wire Iin3 ;
+   wire Iin6 ;
+   wire Itmp23 ;
    wire Itmp19 ;
-   wire Iin7 ;
+   wire Itmp21 ;
+   wire Itmp22 ;
+   wire Iin1 ;
+   wire Itmp24 ;
    wire Iin14 ;
-   wire Iin13 ;
-   wire Itmp15 ;
+   wire Iin11 ;
+   wire Iin0 ;
    wire Iin12 ;
 
 // --- instances

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_34_4/netlist/verilog.v

@@ -8,13 +8,13 @@ module tmpl_0_0dataflow__neuro_0_0ortree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, v
    output out;
 
 // -- signals ---
-   wire Iin2 ;
-   wire Itmp4 ;
-   wire out ;
-   wire Itmp5 ;
    wire Iin1 ;
+   wire Iin2 ;
+   wire out ;
    wire Iin3 ;
+   wire Itmp4 ;
    wire Iin0 ;
+   wire Itmp5 ;
 
 // --- instances
 OR2_X1 Ior2s0  (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_358_4/netlist/verilog.v

@@ -62,118 +62,118 @@ module tmpl_0_0dataflow__neuro_0_0ortree_358_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
    output out;
 
 // -- signals ---
-   wire Iin51 ;
-   wire Iin28 ;
-   wire Itmp99 ;
-   wire Iin9 ;
-   wire Itmp59 ;
-   wire Iin53 ;
-   wire Iin46 ;
-   wire Itmp67 ;
-   wire Iin12 ;
-   wire Itmp85 ;
-   wire Itmp98 ;
-   wire Iin25 ;
-   wire Itmp105 ;
-   wire Iin39 ;
-   wire Iin10 ;
-   wire Itmp107 ;
-   wire Iin49 ;
-   wire Itmp69 ;
-   wire Itmp63 ;
-   wire Iin50 ;
-   wire Itmp80 ;
-   wire Itmp79 ;
-   wire Iin24 ;
-   wire Itmp66 ;
-   wire Itmp100 ;
-   wire Itmp94 ;
-   wire Iin56 ;
-   wire Iin40 ;
-   wire Itmp77 ;
-   wire Iin31 ;
-   wire Itmp110 ;
-   wire Itmp95 ;
-   wire Iin18 ;
-   wire Itmp62 ;
-   wire Itmp97 ;
-   wire Iin44 ;
-   wire Itmp60 ;
-   wire Iin1 ;
-   wire Iin34 ;
-   wire Itmp70 ;
-   wire Itmp92 ;
-   wire Itmp90 ;
-   wire Itmp89 ;
-   wire Iin54 ;
-   wire Itmp76 ;
-   wire Itmp73 ;
-   wire Iin7 ;
-   wire Iin41 ;
-   wire Itmp78 ;
    wire Itmp72 ;
-   wire Itmp68 ;
-   wire Iin55 ;
-   wire Iin32 ;
-   wire Iin26 ;
-   wire Iin23 ;
-   wire Iin20 ;
-   wire Itmp65 ;
-   wire Itmp96 ;
-   wire Iin0 ;
-   wire Itmp101 ;
-   wire Iin17 ;
-   wire Iin2 ;
-   wire Iin37 ;
-   wire Itmp91 ;
    wire Iin57 ;
-   wire Itmp75 ;
-   wire Iin43 ;
-   wire Iin33 ;
-   wire Iin4 ;
-   wire Itmp102 ;
-   wire Itmp87 ;
-   wire Iin45 ;
-   wire Iin16 ;
-   wire Itmp58 ;
-   wire Iin36 ;
-   wire Itmp108 ;
-   wire Itmp81 ;
+   wire Itmp62 ;
+   wire Iin1 ;
+   wire Itmp103 ;
+   wire Itmp63 ;
+   wire Iin0 ;
+   wire Iin47 ;
    wire Iin38 ;
+   wire Itmp75 ;
+   wire Itmp70 ;
+   wire Iin17 ;
+   wire Iin6 ;
+   wire Itmp83 ;
+   wire Iin15 ;
+   wire Iin9 ;
+   wire Itmp100 ;
+   wire Itmp97 ;
+   wire Itmp89 ;
+   wire Iin52 ;
+   wire Itmp81 ;
+   wire Iin31 ;
+   wire Iin28 ;
    wire Iin13 ;
+   wire Itmp61 ;
+   wire Itmp94 ;
+   wire Itmp80 ;
+   wire Iin32 ;
+   wire Iin16 ;
+   wire Itmp78 ;
+   wire Iin22 ;
+   wire Iin5 ;
+   wire Itmp108 ;
+   wire Iin44 ;
+   wire Iin21 ;
+   wire Itmp84 ;
+   wire Iin55 ;
+   wire Iin49 ;
+   wire Iin27 ;
+   wire Itmp69 ;
+   wire Itmp68 ;
+   wire Iin53 ;
+   wire Itmp79 ;
+   wire Iin39 ;
+   wire Iin26 ;
+   wire Iin12 ;
+   wire out ;
+   wire Iin51 ;
+   wire Iin23 ;
+   wire Iin18 ;
+   wire Iin11 ;
+   wire Itmp98 ;
+   wire Itmp96 ;
+   wire Itmp74 ;
+   wire Iin48 ;
+   wire Iin42 ;
+   wire Iin37 ;
+   wire Iin35 ;
+   wire Itmp67 ;
+   wire Itmp104 ;
+   wire Itmp99 ;
+   wire Itmp76 ;
+   wire Itmp102 ;
+   wire Itmp90 ;
+   wire Iin40 ;
+   wire Itmp71 ;
+   wire Iin36 ;
+   wire Iin25 ;
+   wire Iin19 ;
+   wire Itmp95 ;
+   wire Itmp91 ;
+   wire Itmp59 ;
+   wire Itmp101 ;
+   wire Itmp88 ;
+   wire Iin8 ;
+   wire Itmp85 ;
+   wire Itmp93 ;
+   wire Iin4 ;
+   wire Iin33 ;
+   wire Iin14 ;
+   wire Itmp64 ;
+   wire Iin41 ;
+   wire Itmp105 ;
+   wire Itmp77 ;
+   wire Itmp73 ;
+   wire Iin24 ;
+   wire Iin10 ;
    wire Iin3 ;
    wire Itmp109 ;
-   wire Itmp103 ;
-   wire Iin30 ;
-   wire Iin19 ;
-   wire Iin15 ;
-   wire Itmp61 ;
-   wire Itmp106 ;
-   wire Itmp93 ;
-   wire Iin47 ;
-   wire Itmp74 ;
-   wire Itmp64 ;
-   wire Itmp88 ;
-   wire Iin52 ;
-   wire Itmp84 ;
-   wire Itmp71 ;
-   wire Itmp83 ;
-   wire Itmp82 ;
-   wire Itmp104 ;
-   wire Iin48 ;
-   wire Iin11 ;
-   wire out ;
-   wire Iin35 ;
-   wire Iin21 ;
-   wire Iin14 ;
-   wire Iin8 ;
-   wire Iin6 ;
-   wire Iin5 ;
-   wire Iin29 ;
-   wire Iin22 ;
-   wire Iin42 ;
-   wire Iin27 ;
    wire Itmp86 ;
+   wire Iin46 ;
+   wire Itmp65 ;
+   wire Itmp107 ;
+   wire Itmp92 ;
+   wire Iin56 ;
+   wire Iin45 ;
+   wire Iin29 ;
+   wire Iin20 ;
+   wire Itmp66 ;
+   wire Iin2 ;
+   wire Itmp106 ;
+   wire Iin7 ;
+   wire Itmp110 ;
+   wire Iin54 ;
+   wire Iin50 ;
+   wire Iin43 ;
+   wire Itmp60 ;
+   wire Itmp87 ;
+   wire Itmp82 ;
+   wire Iin34 ;
+   wire Iin30 ;
+   wire Itmp58 ;
 
 // --- instances
 OR3_X1 Ior3s0  (.y(Itmp100 ), .a(Itmp84 ), .b(Itmp85 ), .c(Itmp86 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_364_4/netlist/verilog.v

@@ -68,133 +68,133 @@ module tmpl_0_0dataflow__neuro_0_0ortree_364_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4
    output out;
 
 // -- signals ---
-   wire Itmp117 ;
-   wire Itmp109 ;
-   wire Itmp106 ;
-   wire Iin60 ;
-   wire Itmp86 ;
-   wire Iin37 ;
-   wire Iin5 ;
-   wire Iin36 ;
-   wire Itmp69 ;
-   wire Iin27 ;
-   wire Iin21 ;
-   wire Itmp74 ;
-   wire Iin4 ;
-   wire Itmp66 ;
-   wire Iin48 ;
-   wire Itmp79 ;
-   wire Itmp72 ;
-   wire Iin1 ;
-   wire Itmp95 ;
-   wire Iin33 ;
-   wire Iin58 ;
-   wire Iin44 ;
-   wire Iin39 ;
-   wire Iin11 ;
-   wire Itmp112 ;
-   wire Iin43 ;
-   wire Iin22 ;
-   wire Iin19 ;
-   wire Itmp65 ;
-   wire Iin18 ;
-   wire Itmp73 ;
-   wire Itmp84 ;
-   wire Itmp80 ;
-   wire Iin26 ;
-   wire Itmp76 ;
-   wire Itmp101 ;
-   wire Iin10 ;
-   wire Itmp122 ;
-   wire Itmp114 ;
-   wire Itmp96 ;
-   wire Itmp93 ;
-   wire Iin41 ;
-   wire Itmp70 ;
-   wire Itmp81 ;
-   wire Iin28 ;
-   wire Iin12 ;
-   wire Itmp124 ;
-   wire Itmp110 ;
-   wire Itmp105 ;
-   wire Iin61 ;
-   wire Iin49 ;
-   wire Itmp83 ;
-   wire Iin35 ;
-   wire Itmp91 ;
-   wire Itmp88 ;
-   wire Itmp71 ;
-   wire Itmp68 ;
-   wire Iin59 ;
-   wire Itmp85 ;
-   wire Itmp77 ;
-   wire Iin13 ;
-   wire Iin0 ;
-   wire Itmp125 ;
-   wire Itmp103 ;
-   wire Itmp100 ;
-   wire Itmp98 ;
-   wire Itmp90 ;
-   wire Itmp82 ;
-   wire Iin9 ;
-   wire Iin6 ;
-   wire Itmp118 ;
-   wire Itmp108 ;
-   wire Iin55 ;
-   wire Iin24 ;
-   wire Itmp75 ;
-   wire Iin63 ;
-   wire Itmp89 ;
-   wire Iin30 ;
-   wire Iin15 ;
-   wire Itmp64 ;
-   wire Iin45 ;
-   wire Iin17 ;
-   wire Itmp107 ;
-   wire Iin40 ;
-   wire Iin29 ;
-   wire Itmp78 ;
-   wire Itmp115 ;
    wire Itmp121 ;
-   wire Itmp119 ;
-   wire Itmp102 ;
-   wire Itmp94 ;
-   wire Iin56 ;
-   wire Iin47 ;
-   wire Itmp87 ;
-   wire Itmp116 ;
-   wire Itmp113 ;
-   wire Iin62 ;
-   wire Iin42 ;
-   wire Iin32 ;
-   wire Iin7 ;
-   wire Itmp104 ;
-   wire Iin54 ;
-   wire Iin52 ;
-   wire Iin23 ;
-   wire Itmp92 ;
-   wire Iin8 ;
+   wire Itmp93 ;
    wire Iin53 ;
-   wire Iin20 ;
-   wire Iin2 ;
-   wire out ;
-   wire Itmp97 ;
-   wire Iin14 ;
-   wire Iin50 ;
-   wire Iin34 ;
-   wire Iin25 ;
-   wire Itmp67 ;
-   wire Itmp111 ;
-   wire Iin57 ;
-   wire Iin51 ;
-   wire Iin31 ;
-   wire Iin46 ;
-   wire Iin38 ;
+   wire Iin49 ;
+   wire Iin43 ;
+   wire Iin11 ;
+   wire Itmp81 ;
+   wire Itmp68 ;
+   wire Itmp65 ;
+   wire Itmp113 ;
+   wire Iin63 ;
+   wire Iin61 ;
+   wire Iin45 ;
+   wire Iin39 ;
+   wire Iin22 ;
+   wire Itmp87 ;
+   wire Itmp85 ;
+   wire Iin35 ;
+   wire Itmp103 ;
+   wire Iin56 ;
    wire Iin16 ;
-   wire Itmp123 ;
+   wire Iin4 ;
+   wire Itmp96 ;
+   wire Iin55 ;
+   wire Iin23 ;
+   wire Itmp64 ;
    wire Itmp120 ;
+   wire Itmp118 ;
+   wire Itmp86 ;
+   wire Iin25 ;
+   wire Itmp76 ;
+   wire Iin18 ;
+   wire Itmp116 ;
+   wire Iin59 ;
+   wire Itmp92 ;
+   wire Iin54 ;
+   wire Iin48 ;
+   wire Iin33 ;
+   wire Iin26 ;
+   wire Iin10 ;
+   wire Iin9 ;
+   wire Iin5 ;
+   wire Iin44 ;
+   wire Iin17 ;
+   wire Iin15 ;
+   wire Iin6 ;
+   wire out ;
+   wire Itmp125 ;
+   wire Iin42 ;
+   wire Itmp106 ;
+   wire Itmp83 ;
+   wire Iin30 ;
+   wire Iin8 ;
+   wire Itmp124 ;
+   wire Itmp117 ;
+   wire Itmp114 ;
+   wire Itmp112 ;
+   wire Iin47 ;
+   wire Itmp80 ;
+   wire Iin27 ;
+   wire Itmp108 ;
+   wire Itmp104 ;
+   wire Itmp73 ;
+   wire Itmp102 ;
+   wire Iin62 ;
+   wire Itmp84 ;
+   wire Itmp82 ;
+   wire Itmp77 ;
+   wire Iin24 ;
+   wire Itmp123 ;
+   wire Iin58 ;
+   wire Itmp72 ;
    wire Itmp99 ;
+   wire Iin29 ;
+   wire Itmp66 ;
+   wire Itmp109 ;
+   wire Itmp90 ;
+   wire Itmp89 ;
+   wire Itmp75 ;
    wire Iin3 ;
+   wire Itmp119 ;
+   wire Itmp94 ;
+   wire Itmp71 ;
+   wire Iin13 ;
+   wire Iin46 ;
+   wire Iin36 ;
+   wire Iin31 ;
+   wire Iin1 ;
+   wire Itmp110 ;
+   wire Iin7 ;
+   wire Iin57 ;
+   wire Iin2 ;
+   wire Itmp122 ;
+   wire Iin60 ;
+   wire Itmp88 ;
+   wire Iin14 ;
+   wire Itmp69 ;
+   wire Iin0 ;
+   wire Itmp111 ;
+   wire Itmp97 ;
+   wire Iin50 ;
+   wire Itmp78 ;
+   wire Itmp95 ;
+   wire Itmp91 ;
+   wire Iin40 ;
+   wire Iin37 ;
+   wire Itmp79 ;
+   wire Itmp74 ;
+   wire Iin19 ;
+   wire Itmp70 ;
+   wire Itmp105 ;
+   wire Iin20 ;
+   wire Iin12 ;
+   wire Itmp115 ;
+   wire Itmp101 ;
+   wire Itmp100 ;
+   wire Iin41 ;
+   wire Iin21 ;
+   wire Iin52 ;
+   wire Iin51 ;
+   wire Itmp107 ;
+   wire Itmp98 ;
+   wire Iin38 ;
+   wire Iin34 ;
+   wire Iin32 ;
+   wire Iin28 ;
+   wire Itmp67 ;
 
 // --- instances
 OR2_X1 Ior2s0  (.y(Itmp64 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0ortree_38_4/netlist/verilog.v

@@ -12,21 +12,21 @@ module tmpl_0_0dataflow__neuro_0_0ortree_38_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 ,
    output out;
 
 // -- signals ---
-   wire Iin0 ;
-   wire Itmp11 ;
    wire Itmp13 ;
-   wire Itmp12 ;
-   wire Iin3 ;
-   wire Iin2 ;
-   wire Iin7 ;
-   wire Itmp10 ;
-   wire Itmp8 ;
    wire Iin1 ;
-   wire Iin5 ;
+   wire Itmp8 ;
+   wire Iin2 ;
+   wire Itmp12 ;
+   wire Itmp10 ;
+   wire Itmp11 ;
+   wire Iin4 ;
+   wire Iin0 ;
+   wire Iin3 ;
    wire Iin6 ;
    wire Itmp9 ;
-   wire Iin4 ;
    wire out ;
+   wire Iin7 ;
+   wire Iin5 ;
 
 // --- instances
 OR2_X1 Ior2s0  (.y(Itmp8 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4/netlist/verilog.v

@@ -108,144 +108,144 @@ module tmpl_0_0dataflow__neuro_0_0qdi2bd_332_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Ii
    input reset_B;
 
 // -- signals ---
-   output Iout_d5 ;
-   wire Iin_d_d0_d1 ;
-   wire Iin_d_d4_d1 ;
-   wire Iin_d_d7_d0 ;
-   output Iout_d14 ;
-   output Iout_d0 ;
-   wire Iin_d_d17_d0 ;
-   wire Iin_d_d19_d1 ;
-   wire Iout_vtree_in_d12_d0 ;
-   wire Iout_vtree_in_d29_d0 ;
-   wire Iin_d_d3_d0 ;
-   wire Iin_d_d9_d1 ;
-   wire Iout_vtree_in_d5_d0 ;
-   wire Iout_vtree_in_d19_d0 ;
-   output Iout_d19 ;
-   wire Idly_cfg3 ;
-   wire Iout_vtree_in_d2_d0 ;
-   wire Iout_vtree_in_d15_d0 ;
-   wire Iout_vtree_in_d3_d0 ;
-   wire Iout_vtree_in_d24_d0 ;
-   wire Iin_d_d21_d0 ;
-   wire Iin_d_d29_d1 ;
-   wire Iin_d_d30_d1 ;
-   output Iout_d11 ;
-   output Iout_d12 ;
-   wire Iout_vtree_in_d26_d0 ;
-   wire Iin_d_d8_d0 ;
-   wire reset_B;
+   wire Idly_cfg0 ;
+   wire Iout_vtree_in_d13_d0 ;
+   wire Iout_vtree_in_d21_d0 ;
+   wire Iin_d_d7_d1 ;
+   wire Iout_vtree_in_d18_d0 ;
+   wire Iin_d_d9_d0 ;
+   output Iin_a ;
    wire Iout_vtree_in_d28_d0 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d25_d0 ;
+   wire Iout_vtree_in_d11_d0 ;
    wire Iin_d_d2_d0 ;
+   wire Iin_d_d22_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire Iout_vtree_in_d2_d0 ;
+   wire Iout_vtree_in_d25_d0 ;
+   wire Iin_d_d11_d1 ;
+   wire Iin_d_d19_d0 ;
+   wire Iout_vtree_in_d0_d0 ;
+   output Iout_d12 ;
+   wire Iin_d_d17_d1 ;
+   wire Iin_d_d26_d1 ;
+   wire Iin_d_d12_d1 ;
    wire Iin_d_d22_d1 ;
-   output Iout_d13 ;
+   wire Iin_d_d9_d1 ;
+   wire Iout_vtree_in_d8_d0 ;
+   wire Iin_d_d0_d1 ;
+   wire Iin_d_d18_d1 ;
+   wire Iin_d_d25_d1 ;
+   wire Idly_cfg1 ;
+   output Iout_d3 ;
+   output Iout_d26 ;
+   wire Iin_d_d4_d0 ;
+   output Iout_d18 ;
+   wire Iin_d_d29_d0 ;
+   wire Iout_vtree_in_d4_d0 ;
+   wire Iout_vtree_in_d5_d0 ;
+   output Iout_d7 ;
+   wire Iout_vtree_in_d26_d0 ;
+   output Iout_r ;
+   wire Iout_a ;
+   wire Iin_d_d4_d1 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d14_d0 ;
+   wire Iin_d_d31_d0 ;
+   output Iout_d11 ;
+   output Iout_d25 ;
+   output Iout_d27 ;
+   wire Iin_d_d23_d0 ;
+   output Iin_v ;
+   output Iout_d29 ;
+   wire Iout_vtree_in_d16_d0 ;
    wire Iin_d_d12_d0 ;
+   output Iout_d14 ;
+   wire Iout_vtree_in_d27_d0 ;
+   wire Iin_d_d23_d1 ;
+   wire reset_B;
+   wire Idly_in ;
+   output Iout_d4 ;
+   wire Iin_d_d30_d0 ;
+   wire Iin_d_d30_d1 ;
+   wire Iin_d_d16_d0 ;
+   wire Iin_d_d31_d1 ;
+   wire Iout_vtree_in_d12_d0 ;
+   output Iout_d16 ;
+   output Iout_d21 ;
+   wire Iin_d_d8_d1 ;
+   wire Iin_d_d26_d0 ;
+   output Iout_d0 ;
+   output Iout_d9 ;
+   wire Iout_vtree_in_d23_d0 ;
+   wire Iin_d_d1_d0 ;
+   wire Iin_d_d15_d1 ;
+   output Iout_d24 ;
+   wire Idly_cfg3 ;
+   output Iout_d17 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d28_d1 ;
+   wire Iin_d_d24_d1 ;
    output Iout_d8 ;
+   wire Iin_d_d5_d0 ;
+   wire Iout_vtree_in_d22_d0 ;
+   wire Iin_d_d10_d1 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d13_d0 ;
+   output Iout_d23 ;
+   wire Iin_d_d28_d0 ;
+   output Iout_d2 ;
+   wire Iin_d_d3_d1 ;
+   wire Iin_d_d18_d0 ;
+   wire Iin_d_d2_d1 ;
    wire Iout_vtree_in_d1_d0 ;
+   output Iout_d1 ;
+   wire Iin_d_d16_d1 ;
+   output Iout_d6 ;
+   wire Iin_d_d24_d0 ;
+   output Iout_d30 ;
+   wire Iout_vtree_in_d20_d0 ;
+   wire Idly_cfg2 ;
+   wire Iin_d_d7_d0 ;
+   wire Iin_d_d17_d0 ;
+   output Iout_d19 ;
+   wire Iin_d_d15_d0 ;
+   wire Iout_vtree_in_d3_d0 ;
+   wire Iin_d_d13_d1 ;
+   wire Iin_d_d27_d0 ;
+   output Iout_d15 ;
+   wire Iout_vtree_in_d31_d0 ;
+   wire Iout_vtree_in_d29_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d27_d1 ;
+   wire Iout_vtree_in_d19_d0 ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d20_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iout_vtree_in_d15_d0 ;
    wire Iout_vtree_in_d30_d0 ;
    wire Iin_d_d1_d1 ;
-   wire Iin_d_d30_d0 ;
-   wire Iin_d_d26_d1 ;
-   wire Iout_vtree_in_d21_d0 ;
-   output Iout_d28 ;
-   wire Iin_d_d10_d0 ;
-   wire Iin_d_d11_d0 ;
-   wire Iin_d_d25_d1 ;
-   output Iout_d4 ;
-   wire Iout_vtree_in_d4_d0 ;
-   wire Iout_vtree_in_d8_d0 ;
-   wire Iout_vtree_in_d10_d0 ;
-   wire Iin_d_d11_d1 ;
-   wire Iin_d_d12_d1 ;
-   wire Iin_d_d13_d0 ;
-   wire Iin_d_d16_d1 ;
-   wire Iin_d_d24_d0 ;
-   wire Iin_d_d31_d0 ;
-   output Iout_d20 ;
-   wire Iout_vtree_in_d23_d0 ;
-   wire Iin_d_d18_d1 ;
-   wire Idly_in ;
-   wire Iin_d_d18_d0 ;
-   output Iout_d18 ;
-   output Iout_d22 ;
-   output Iout_r ;
-   output Iout_d31 ;
-   wire Iout_vtree_in_d25_d0 ;
-   wire Iin_d_d1_d0 ;
-   output Iout_d24 ;
-   wire Iin_d_d21_d1 ;
-   wire Iout_vtree_in_d22_d0 ;
-   wire Iin_d_d13_d1 ;
-   wire Iin_d_d23_d1 ;
-   wire Iin_d_d24_d1 ;
-   wire Iout_vtree_in_d0_d0 ;
-   output Iout_d15 ;
-   output Iout_d16 ;
-   wire Iout_vtree_in_d27_d0 ;
+   wire Iin_d_d29_d1 ;
+   output Iout_d5 ;
    output Iout_d10 ;
-   output Iout_d25 ;
-   wire Idly_cfg2 ;
-   output Iin_v ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d15_d0 ;
-   wire Iin_d_d25_d0 ;
-   output Iout_d21 ;
-   output Iout_d1 ;
-   wire Iout_vtree_in_d17_d0 ;
-   wire Iin_d_d15_d1 ;
-   wire Iout_a ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d7_d1 ;
-   wire Iout_vtree_in_d31_d0 ;
-   wire Iin_d_d28_d1 ;
-   output Iout_d6 ;
-   wire Iout_vtree_in_d16_d0 ;
-   output Iout_d23 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d19_d0 ;
-   wire Iin_d_d27_d1 ;
-   wire Iout_vtree_in_d9_d0 ;
-   wire Iout_vtree_in_d11_d0 ;
-   wire Iout_vtree_in_d20_d0 ;
-   output Iout_d26 ;
-   wire Iin_d_d20_d1 ;
-   wire Iout_vtree_in_d18_d0 ;
-   wire Iin_d_d5_d0 ;
-   output Iout_d9 ;
-   wire Iin_d_d10_d1 ;
-   wire Iout_vtree_in_d7_d0 ;
-   output Iout_d29 ;
-   wire Iin_d_d27_d0 ;
-   output Iin_a ;
-   wire Iin_d_d8_d1 ;
-   wire Idly_cfg0 ;
-   wire Iin_d_d26_d0 ;
-   wire Iin_d_d31_d1 ;
-   output Iout_d27 ;
-   wire Idly_cfg1 ;
+   wire Iout_vtree_in_d10_d0 ;
    wire Iin_d_d6_d0 ;
-   wire Iin_d_d28_d0 ;
-   wire Iin_d_d29_d0 ;
+   wire Iout_vtree_in_d9_d0 ;
    wire Iout_vtree_in_d14_d0 ;
-   wire Iin_d_d3_d1 ;
-   wire Iin_d_d4_d0 ;
-   wire Iin_d_d5_d1 ;
-   output Iout_d7 ;
-   wire Iin_d_d14_d1 ;
-   wire Iin_d_d2_d1 ;
-   wire Iout_vtree_in_d13_d0 ;
-   output Iout_d17 ;
+   output Iout_d13 ;
+   wire Iout_vtree_in_d24_d0 ;
+   output Iout_d31 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d19_d1 ;
+   output Iout_d28 ;
+   wire Iout_vtree_in_d7_d0 ;
    wire Iout_vtree_in_d6_d0 ;
-   output Iout_d3 ;
-   output Iout_d30 ;
-   wire Iin_d_d0_d0 ;
-   wire Iin_d_d16_d0 ;
-   wire Iin_d_d22_d0 ;
-   wire Iin_d_d23_d0 ;
-   wire Iin_d_d17_d1 ;
-   output Iout_d2 ;
+   output Iout_d20 ;
+   wire Iout_vtree_in_d17_d0 ;
+   wire Iin_d_d5_d1 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d22 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly  (.out(Iout_r ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4/netlist/verilog.v

@@ -1,4 +1,4 @@
-module tmpl_0_0dataflow__neuro_0_0register__acells__improved_324_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d1 , Iin_a , Iout_d0_d0 , Iout_d0_d1 , Iout_d1_d0 , Iout_d1_d1 , Iout_d2_d0 , Iout_d2_d1 , Iout_d3_d0 , Iout_d3_d1 , Iout_d4_d0 , Iout_d4_d1 , Iout_d5_d0 , Iout_d5_d1 , Iout_d6_d0 , Iout_d6_d1 , Iout_d7_d0 , Iout_d7_d1 , Iout_d8_d0 , Iout_d8_d1 , Iout_d9_d0 , Iout_d9_d1 , Iout_d10_d0 , Iout_d10_d1 , Iout_d11_d0 , Iout_d11_d1 , Iout_d12_d0 , Iout_d12_d1 , Iout_d13_d0 , Iout_d13_d1 , Iout_d14_d0 , Iout_d14_d1 , Iout_d15_d0 , Iout_d15_d1 , Iout_d16_d0 , Iout_d16_d1 , Iout_d17_d0 , Iout_d17_d1 , Iout_d18_d0 , Iout_d18_d1 , Iout_d19_d0 , Iout_d19_d1 , Iout_d20_d0 , Iout_d20_d1 , Iout_d21_d0 , Iout_d21_d1 , Iout_d22_d0 , Iout_d22_d1 , Iout_d23_d0 , Iout_d23_d1 , reset_B, vdd, vss); 
+module tmpl_0_0dataflow__neuro_0_0register__acells__improved_323_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d1 , Iin_a , Iout_d0_d0 , Iout_d0_d1 , Iout_d1_d0 , Iout_d1_d1 , Iout_d2_d0 , Iout_d2_d1 , Iout_d3_d0 , Iout_d3_d1 , Iout_d4_d0 , Iout_d4_d1 , Iout_d5_d0 , Iout_d5_d1 , Iout_d6_d0 , Iout_d6_d1 , Iout_d7_d0 , Iout_d7_d1 , Iout_d8_d0 , Iout_d8_d1 , Iout_d9_d0 , Iout_d9_d1 , Iout_d10_d0 , Iout_d10_d1 , Iout_d11_d0 , Iout_d11_d1 , Iout_d12_d0 , Iout_d12_d1 , Iout_d13_d0 , Iout_d13_d1 , Iout_d14_d0 , Iout_d14_d1 , Iout_d15_d0 , Iout_d15_d1 , Iout_d16_d0 , Iout_d16_d1 , Iout_d17_d0 , Iout_d17_d1 , Iout_d18_d0 , Iout_d18_d1 , Iout_d19_d0 , Iout_d19_d1 , Iout_d20_d0 , Iout_d20_d1 , Iout_d21_d0 , Iout_d21_d1 , Iout_d22_d0 , Iout_d22_d1 , reset_B, vdd, vss); 
    input vdd;
    input vss;
    input Iin_d_d0_d0 ;
@@ -47,11 +47,7 @@ module tmpl_0_0dataflow__neuro_0_0register__acells__improved_324_4(Iin_d_d0_d0 ,
    input Iin_d_d21_d1 ;
    input Iin_d_d22_d0 ;
    input Iin_d_d22_d1 ;
-   input Iin_d_d23_d0 ;
    input Iin_d_d23_d1 ;
-   input Iin_d_d24_d1 ;
-   
-   
    
    
    
@@ -102,130 +98,126 @@ module tmpl_0_0dataflow__neuro_0_0register__acells__improved_324_4(Iin_d_d0_d0 ,
    input reset_B;
 
 // -- signals ---
-   wire Iin_d_d15_d0 ;
-   wire Iin_d_d21_d1 ;
-   wire Iin_d_d9_d1 ;
-   wire Iin_d_d7_d1 ;
-   output Iout_d20_d1 ;
-   output Iout_d12_d0 ;
-   output Iout_d1_d1 ;
-   output Iout_d4_d0 ;
-   output Iout_d3_d0 ;
-   wire Iin_d_d12_d0 ;
-   wire Iin_d_d5_d0 ;
-   wire Iin_d_d20_d1 ;
-   wire Iin_d_d11_d1 ;
    wire Iin_d_d1_d0 ;
-   output Iout_d10_d0 ;
-   output Iout_d7_d0 ;
-   wire Iin_d_d23_d0 ;
-   wire Iin_d_d8_d0 ;
-   wire Iin_d_d16_d1 ;
-   output Iout_d21_d1 ;
-   output Iout_d14_d0 ;
-   wire Iin_d_d0_d0 ;
-   output Iout_d23_d0 ;
-   output Iout_d19_d1 ;
-   output Iout_d11_d0 ;
-   wire Iin_d_d3_d0 ;
-   wire Iin_d_d24_d1 ;
-   wire Iin_d_d15_d1 ;
-   wire Iin_d_d4_d1 ;
-   output Iout_d16_d0 ;
-   output Iout_d15_d0 ;
-   output Iout_d0_d0 ;
-   wire Iin_d_d17_d0 ;
-   wire Iin_d_d2_d0 ;
-   output Iout_d4_d1 ;
-   wire Iin_d_d19_d1 ;
-   wire I_resetX0 ;
-   output Iout_d18_d1 ;
-   output Iout_d6_d1 ;
-   wire IA_flush_sr_B ;
-   output Iout_d18_d0 ;
-   output Iout_d3_d1 ;
-   output Iout_d2_d1 ;
-   wire Iin_d_d13_d1 ;
+   wire Iin_d_d17_d1 ;
    wire _enBX ;
-   output Iout_d20_d0 ;
-   output Iout_d9_d0 ;
-   wire Iin_d_d5_d1 ;
-   wire Iflush_inv_y ;
-   output Iout_d13_d0 ;
-   output Iout_d2_d0 ;
-   wire Iin_d_d4_d0 ;
+   output Iout_d21_d1 ;
+   wire Iin_d_d20_d1 ;
+   wire Iin_d_d4_d1 ;
    wire Iin_d_d3_d1 ;
-   wire _flush ;
-   output Iout_d21_d0 ;
-   output Iout_d13_d1 ;
-   output Iout_d8_d0 ;
-   wire Iin_d_d20_d0 ;
-   wire Iin_d_d14_d0 ;
-   wire Iin_d_d13_d0 ;
-   wire Iin_d_d14_d1 ;
    wire _flushBX ;
-   wire reset_B;
-   wire Iin_d_d23_d1 ;
-   wire Iin_d_d22_d1 ;
-   wire Iin_d_d12_d1 ;
-   wire Iin_d_d16_d0 ;
-   wire Iin_d_d10_d0 ;
-   wire Iin_d_d8_d1 ;
-   wire Ien_inv_y ;
-   wire Iin_d_d11_d0 ;
+   output Iout_d18_d0 ;
+   output Iout_d4_d1 ;
+   wire Iin_d_d14_d0 ;
    wire Iin_d_d18_d1 ;
+   output Iout_d9_d1 ;
    wire Iin_d_d0_d1 ;
-   output Iout_d16_d1 ;
-   output Iout_d5_d0 ;
-   output Iout_d17_d1 ;
    output Iout_d22_d1 ;
-   output Iout_d17_d0 ;
-   output Iout_d23_d1 ;
-   output Iout_d15_d1 ;
+   output Iout_d18_d1 ;
+   output Iout_d5_d1 ;
+   output Iout_d3_d0 ;
+   wire Iin_d_d2_d1 ;
+   output Iout_d19_d0 ;
+   output Iout_d12_d1 ;
+   output Iout_d9_d0 ;
+   wire Iin_d_d10_d0 ;
+   wire Iin_d_d6_d0 ;
+   wire Iin_d_d5_d0 ;
+   wire Iin_d_d19_d1 ;
+   output Iout_d8_d1 ;
    wire Iin_d_d22_d0 ;
-   wire Iin_d_d21_d0 ;
+   wire _flush ;
+   output Iout_d12_d0 ;
+   wire Iin_d_d7_d0 ;
+   output Iout_d15_d1 ;
+   output Iout_d0_d1 ;
+   wire Iin_d_d11_d0 ;
+   wire Iin_d_d6_d1 ;
+   output Iout_d20_d1 ;
+   output Iout_d17_d0 ;
+   output Iout_d16_d0 ;
+   wire Iin_d_d4_d0 ;
+   wire Iin_d_d3_d0 ;
+   wire Iin_d_d22_d1 ;
+   wire Iin_d_d11_d1 ;
    wire _out_vB ;
+   wire I_resetX0 ;
+   output Iout_d17_d1 ;
+   wire Iin_d_d15_d0 ;
+   wire Iin_d_d16_d1 ;
+   wire Iflush_inv_y ;
+   output Iout_d16_d1 ;
+   output Iout_d11_d0 ;
+   wire Iin_d_d12_d0 ;
+   output Iout_d11_d1 ;
+   output Iout_d10_d0 ;
+   output Iout_d0_d0 ;
+   wire Iin_d_d8_d0 ;
+   wire Iin_d_d15_d1 ;
    wire Iin_d_d10_d1 ;
    wire Ireset_sb_in ;
-   output Iout_d22_d0 ;
-   output Iout_d0_d1 ;
+   output Iout_d4_d0 ;
+   output Iout_d2_d0 ;
+   wire _out_v ;
+   output Iout_d5_d0 ;
    wire Iin_d_d19_d0 ;
    wire Iin_d_d18_d0 ;
-   wire Iin_d_d9_d0 ;
-   wire Iin_d_d6_d1 ;
-   wire Iin_d_d1_d1 ;
-   output Iout_d8_d1 ;
-   output Iout_d6_d0 ;
-   wire Iin_d_d2_d1 ;
-   wire _en ;
-   output Iout_d11_d1 ;
-   output Iout_d10_d1 ;
-   output Iout_d7_d1 ;
-   output Iout_d12_d1 ;
-   output Iout_d9_d1 ;
-   output Iout_d5_d1 ;
-   output Iout_d1_d0 ;
-   wire _out_v ;
-   wire Iin_d_d7_d0 ;
-   wire Iin_d_d6_d0 ;
-   wire Iin_d_d17_d1 ;
-   output Iin_a ;
+   wire Iin_d_d16_d0 ;
    output Iout_d14_d1 ;
-   output Iout_d19_d0 ;
+   output Iout_d10_d1 ;
+   wire Iin_d_d9_d0 ;
+   wire Iin_d_d8_d1 ;
+   wire IA_flush_sr_B ;
+   output Iout_d22_d0 ;
+   output Iout_d20_d0 ;
+   wire Iin_d_d2_d0 ;
+   output Iout_d21_d0 ;
+   output Iout_d14_d0 ;
+   output Iout_d2_d1 ;
+   wire Iin_d_d12_d1 ;
+   output Iout_d6_d0 ;
+   wire Iin_d_d21_d1 ;
+   wire Iin_d_d5_d1 ;
+   output Iin_a ;
+   output Iout_d19_d1 ;
+   wire Iin_d_d7_d1 ;
+   output Iout_d7_d0 ;
+   output Iout_d6_d1 ;
+   wire Iin_d_d23_d1 ;
+   output Iout_d13_d1 ;
+   wire Iin_d_d20_d0 ;
+   output Iout_d15_d0 ;
+   output Iout_d13_d0 ;
+   output Iout_d1_d0 ;
+   wire Iin_d_d21_d0 ;
+   wire Iin_d_d17_d0 ;
+   wire Iin_d_d14_d1 ;
+   wire Iin_d_d13_d1 ;
+   wire _en ;
+   wire Iin_d_d0_d0 ;
+   wire Iin_d_d1_d1 ;
+   wire reset_B;
+   wire Iin_d_d9_d1 ;
+   output Iout_d7_d1 ;
+   output Iout_d3_d1 ;
+   output Iout_d1_d1 ;
+   wire Iin_d_d13_d0 ;
+   wire Ien_inv_y ;
+   output Iout_d8_d0 ;
 
 // --- instances
 INV_X2 Iout_val_inv  (.y(_out_vB), .a(_out_v), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0vtree_324_4 Ivc  (.Iin_d0_d0 (Iout_d0_d0 ), .Iin_d0_d1 (Iout_d0_d1 ), .Iin_d1_d0 (Iout_d1_d0 ), .Iin_d1_d1 (Iout_d1_d1 ), .Iin_d2_d0 (Iout_d2_d0 ), .Iin_d2_d1 (Iout_d2_d1 ), .Iin_d3_d0 (Iout_d3_d0 ), .Iin_d3_d1 (Iout_d3_d1 ), .Iin_d4_d0 (Iout_d4_d0 ), .Iin_d4_d1 (Iout_d4_d1 ), .Iin_d5_d0 (Iout_d5_d0 ), .Iin_d5_d1 (Iout_d5_d1 ), .Iin_d6_d0 (Iout_d6_d0 ), .Iin_d6_d1 (Iout_d6_d1 ), .Iin_d7_d0 (Iout_d7_d0 ), .Iin_d7_d1 (Iout_d7_d1 ), .Iin_d8_d0 (Iout_d8_d0 ), .Iin_d8_d1 (Iout_d8_d1 ), .Iin_d9_d0 (Iout_d9_d0 ), .Iin_d9_d1 (Iout_d9_d1 ), .Iin_d10_d0 (Iout_d10_d0 ), .Iin_d10_d1 (Iout_d10_d1 ), .Iin_d11_d0 (Iout_d11_d0 ), .Iin_d11_d1 (Iout_d11_d1 ), .Iin_d12_d0 (Iout_d12_d0 ), .Iin_d12_d1 (Iout_d12_d1 ), .Iin_d13_d0 (Iout_d13_d0 ), .Iin_d13_d1 (Iout_d13_d1 ), .Iin_d14_d0 (Iout_d14_d0 ), .Iin_d14_d1 (Iout_d14_d1 ), .Iin_d15_d0 (Iout_d15_d0 ), .Iin_d15_d1 (Iout_d15_d1 ), .Iin_d16_d0 (Iout_d16_d0 ), .Iin_d16_d1 (Iout_d16_d1 ), .Iin_d17_d0 (Iout_d17_d0 ), .Iin_d17_d1 (Iout_d17_d1 ), .Iin_d18_d0 (Iout_d18_d0 ), .Iin_d18_d1 (Iout_d18_d1 ), .Iin_d19_d0 (Iout_d19_d0 ), .Iin_d19_d1 (Iout_d19_d1 ), .Iin_d20_d0 (Iout_d20_d0 ), .Iin_d20_d1 (Iout_d20_d1 ), .Iin_d21_d0 (Iout_d21_d0 ), .Iin_d21_d1 (Iout_d21_d1 ), .Iin_d22_d0 (Iout_d22_d0 ), .Iin_d22_d1 (Iout_d22_d1 ), .Iin_d23_d0 (Iout_d23_d0 ), .Iin_d23_d1 (Iout_d23_d1 ), .out(_out_v), .vdd(vdd), .vss(vss));
-A_2C1N_RB_X1 IA_flush  (.y(_flush), .c1(_en), .c2(_out_v), .n1(Iin_d_d24_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0sigbuf_348_4 Isb_enB  (.in(Ien_inv_y ), .Iout0 (_enBX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0vtree_323_4 Ivc  (.Iin_d0_d0 (Iout_d0_d0 ), .Iin_d0_d1 (Iout_d0_d1 ), .Iin_d1_d0 (Iout_d1_d0 ), .Iin_d1_d1 (Iout_d1_d1 ), .Iin_d2_d0 (Iout_d2_d0 ), .Iin_d2_d1 (Iout_d2_d1 ), .Iin_d3_d0 (Iout_d3_d0 ), .Iin_d3_d1 (Iout_d3_d1 ), .Iin_d4_d0 (Iout_d4_d0 ), .Iin_d4_d1 (Iout_d4_d1 ), .Iin_d5_d0 (Iout_d5_d0 ), .Iin_d5_d1 (Iout_d5_d1 ), .Iin_d6_d0 (Iout_d6_d0 ), .Iin_d6_d1 (Iout_d6_d1 ), .Iin_d7_d0 (Iout_d7_d0 ), .Iin_d7_d1 (Iout_d7_d1 ), .Iin_d8_d0 (Iout_d8_d0 ), .Iin_d8_d1 (Iout_d8_d1 ), .Iin_d9_d0 (Iout_d9_d0 ), .Iin_d9_d1 (Iout_d9_d1 ), .Iin_d10_d0 (Iout_d10_d0 ), .Iin_d10_d1 (Iout_d10_d1 ), .Iin_d11_d0 (Iout_d11_d0 ), .Iin_d11_d1 (Iout_d11_d1 ), .Iin_d12_d0 (Iout_d12_d0 ), .Iin_d12_d1 (Iout_d12_d1 ), .Iin_d13_d0 (Iout_d13_d0 ), .Iin_d13_d1 (Iout_d13_d1 ), .Iin_d14_d0 (Iout_d14_d0 ), .Iin_d14_d1 (Iout_d14_d1 ), .Iin_d15_d0 (Iout_d15_d0 ), .Iin_d15_d1 (Iout_d15_d1 ), .Iin_d16_d0 (Iout_d16_d0 ), .Iin_d16_d1 (Iout_d16_d1 ), .Iin_d17_d0 (Iout_d17_d0 ), .Iin_d17_d1 (Iout_d17_d1 ), .Iin_d18_d0 (Iout_d18_d0 ), .Iin_d18_d1 (Iout_d18_d1 ), .Iin_d19_d0 (Iout_d19_d0 ), .Iin_d19_d1 (Iout_d19_d1 ), .Iin_d20_d0 (Iout_d20_d0 ), .Iin_d20_d1 (Iout_d20_d1 ), .Iin_d21_d0 (Iout_d21_d0 ), .Iin_d21_d1 (Iout_d21_d1 ), .Iin_d22_d0 (Iout_d22_d0 ), .Iin_d22_d1 (Iout_d22_d1 ), .out(_out_v), .vdd(vdd), .vss(vss));
+A_2C1N_RB_X1 IA_flush  (.y(_flush), .c1(_en), .c2(_out_v), .n1(Iin_d_d23_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb_enB  (.in(Ien_inv_y ), .Iout0 (_enBX), .vdd(vdd), .vss(vss));
 INV_X1 Ien_inv  (.y(Ien_inv_y ), .a(_en), .vdd(vdd), .vss(vss));
 INV_X1 Ireset_inv  (.y(Ireset_sb_in ), .a(reset_B), .vdd(vdd), .vss(vss));
 A_1C1P_X1 IA_ack  (.y(Iin_a ), .c1(_en), .p1(_out_vB), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0sigbuf_348_4 Isb_flushB  (.in(Iflush_inv_y ), .Iout0 (_flushBX), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb_flushB  (.in(Iflush_inv_y ), .Iout0 (_flushBX), .vdd(vdd), .vss(vss));
 INV_X1 Iflush_inv  (.y(Iflush_inv_y ), .a(_flush), .vdd(vdd), .vss(vss));
-A_2C_X1 IA_en  (.y(_en), .c1(Iin_d_d24_d1 ), .c2(_out_vB), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Ireset_sb  (.in(Ireset_sb_in ), .Iout0 (I_resetX0 ), .vdd(vdd), .vss(vss));
-tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 IresetB_sb  (.in(reset_B), .Iout0 (IA_flush_sr_B ), .vdd(vdd), .vss(vss));
+A_2C_X1 IA_en  (.y(_en), .c1(Iin_d_d23_d1 ), .c2(_out_vB), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_323_4 Ireset_sb  (.in(Ireset_sb_in ), .Iout0 (I_resetX0 ), .vdd(vdd), .vss(vss));
+tmpl_0_0dataflow__neuro_0_0sigbuf_323_4 IresetB_sb  (.in(reset_B), .Iout0 (IA_flush_sr_B ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d0_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d0_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d1_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d1_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d2_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d2_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
@@ -249,7 +241,6 @@ A_2C1N_RB_X4 It_buf_func19  (.y(Iout_d19_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Ii
 A_2C1N_RB_X4 It_buf_func20  (.y(Iout_d20_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d20_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func21  (.y(Iout_d21_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d21_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
 A_2C1N_RB_X4 It_buf_func22  (.y(Iout_d22_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d22_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
-A_2C1N_RB_X4 It_buf_func23  (.y(Iout_d23_d1 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d23_d1 ), .pr_B(IA_flush_sr_B ), .sr_B(IA_flush_sr_B ), .vdd(vdd), .vss(vss));
 A_2C1N_SB_X4 If_buf_func0  (.y(Iout_d0_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d0_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_SB_X4 If_buf_func1  (.y(Iout_d1_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d1_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_SB_X4 If_buf_func2  (.y(Iout_d2_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d2_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
@@ -273,5 +264,4 @@ A_2C1N_SB_X4 If_buf_func19  (.y(Iout_d19_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Ii
 A_2C1N_SB_X4 If_buf_func20  (.y(Iout_d20_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d20_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_SB_X4 If_buf_func21  (.y(Iout_d21_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d21_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
 A_2C1N_SB_X4 If_buf_func22  (.y(Iout_d22_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d22_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
-A_2C1N_SB_X4 If_buf_func23  (.y(Iout_d23_d0 ), .c1(_flushBX), .c2(_enBX), .n1(Iin_d_d23_d0 ), .pr(I_resetX0 ), .sr(I_resetX0 ), .vdd(vdd), .vss(vss));
 endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_310_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_310_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   wire in;
    output Iout0 ;
+   wire in;
 
 // --- instances
 BUF_X3 Ibuf3  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_3120_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_3120_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X32 Ibuf32  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_3124_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_3124_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   wire in;
    output Iout0 ;
+   wire in;
 
 // --- instances
 BUF_X32 Ibuf32  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_314_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_314_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X4 Ibuf4  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_31_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_31_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X1 Ibuf1  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_323_4/netlist/verilog.v

@@ -0,0 +1,13 @@
+module tmpl_0_0dataflow__neuro_0_0sigbuf_323_4(in, Iout0 , vdd, vss); 
+   input vdd;
+   input vss;
+   input in;
+   
+
+// -- signals ---
+   wire in;
+   output Iout0 ;
+
+// --- instances
+BUF_X8 Ibuf8  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
+endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_324_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_324_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X8 Ibuf8  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_33_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_33_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   wire in;
    output Iout0 ;
+   wire in;
 
 // --- instances
 BUF_X1 Ibuf1  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_346_4/netlist/verilog.v

@@ -0,0 +1,13 @@
+module tmpl_0_0dataflow__neuro_0_0sigbuf_346_4(in, Iout0 , vdd, vss); 
+   input vdd;
+   input vss;
+   input in;
+   
+
+// -- signals ---
+   output Iout0 ;
+   wire in;
+
+// --- instances
+BUF_X12 Ibuf12  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
+endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_347_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_347_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X12 Ibuf12  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_358_4/netlist/master.tag

@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0 
+verilog.v

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_358_4/netlist/verilog.v

@@ -0,0 +1,13 @@
+module tmpl_0_0dataflow__neuro_0_0sigbuf_358_4(in, Iout0 , vdd, vss); 
+   input vdd;
+   input vss;
+   input in;
+   
+
+// -- signals ---
+   wire in;
+   output Iout0 ;
+
+// --- instances
+BUF_X16 Ibuf16  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
+endmodule

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_364_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_364_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X16 Ibuf16  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_365_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_365_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X24 Ibuf24  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_36_4/netlist/verilog.v

@@ -5,8 +5,8 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf_36_4(in, Iout0 , vdd, vss);
    
 
 // -- signals ---
-   output Iout0 ;
    wire in;
+   output Iout0 ;
 
 // --- instances
 BUF_X2 Ibuf2  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_715_4/netlist/verilog.v

@@ -33,36 +33,36 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_715_4(Iin0 , Iin1 , Iin2
    
 
 // -- signals ---
-   wire Iin10 ;
-   output Iout8 ;
-   wire Iin4 ;
+   output Iout9 ;
+   wire Iin3 ;
+   output Iout13 ;
+   output Iout6 ;
+   output Iout5 ;
+   output Iout7 ;
+   wire Iin5 ;
    wire Iin6 ;
-   output Iout2 ;
-   wire Iin13 ;
+   wire Iin2 ;
+   output Iout10 ;
+   wire Iin7 ;
+   output Iout4 ;
+   wire Iin14 ;
+   output Iout0 ;
    output Iout14 ;
    wire Iin12 ;
-   wire Iin11 ;
-   wire Iin8 ;
-   output Iout4 ;
-   wire Iin3 ;
-   wire Iin14 ;
-   output Iout9 ;
-   output Iout5 ;
-   wire Iin7 ;
-   output Iout10 ;
    output Iout3 ;
+   wire Iin11 ;
+   wire Iin10 ;
+   wire Iin0 ;
+   wire Iin13 ;
+   output Iout11 ;
+   wire Iin8 ;
+   wire Iin4 ;
    output Iout12 ;
+   wire Iin9 ;
    output Iout1 ;
    wire Iin1 ;
-   output Iout11 ;
-   output Iout7 ;
-   wire Iin2 ;
-   output Iout0 ;
-   output Iout6 ;
-   wire Iin9 ;
-   wire Iin5 ;
-   wire Iin0 ;
-   output Iout13 ;
+   output Iout8 ;
+   output Iout2 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Isb0  (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));

test/unit_tests/texel_dualcore_glue_noread/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_74_4/netlist/verilog.v

@@ -33,36 +33,36 @@ module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_74_4(Iin0 , Iin1 , Iin2
    
 
 // -- signals ---
-   output Iout2 ;
-   output Iout0 ;
-   output Iout9 ;
-   output Iout4 ;
-   wire Iin7 ;
-   output Iout1 ;
-   output Iout11 ;
-   wire Iin9 ;
-   output Iout6 ;
-   output Iout13 ;
-   wire Iin12 ;
-   output Iout5 ;
-   output Iout7 ;
-   wire Iin4 ;
-   wire Iin8 ;
-   output Iout14 ;
    wire Iin10 ;
    wire Iin5 ;
-   wire Iin3 ;
-   wire Iin2 ;
-   wire Iin1 ;
-   wire Iin0 ;
-   wire Iin11 ;
-   wire Iin13 ;
-   output Iout12 ;
-   output Iout3 ;
+   wire Iin12 ;
    wire Iin6 ;
+   output Iout2 ;
    wire Iin14 ;
-   output Iout10 ;
    output Iout8 ;
+   wire Iin8 ;
+   output Iout12 ;
+   output Iout11 ;
+   wire Iin7 ;
+   output Iout6 ;
+   wire Iin2 ;
+   wire Iin11 ;
+   wire Iin9 ;
+   output Iout5 ;
+   output Iout13 ;
+   output Iout3 ;
+   output Iout9 ;
+   wire Iin0 ;
+   output Iout4 ;
+   wire Iin13 ;
+   wire Iin1 ;
+   wire Iin4 ;
+   output Iout1 ;
+   output Iout10 ;
+   output Iout14 ;
+   wire Iin3 ;
+   output Iout7 ;
+   output Iout0 ;
 
 // --- instances
 tmpl_0_0dataflow__neuro_0_0sigbuf_34_4 Isb0  (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));