bics
/
actlib_dataflow_neuro
18
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

register added again

This commit is contained in:
Greatorex 2022-03-30 15:04:35 +02:00
parent ba17fc0d1b
commit 7db428b827
1 changed files with 18 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
dataflow_neuro/registers.act
View File

@ -136,13 +136,13 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
// WRITE // WRITE
// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active) // Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
bool _in_v_temp_write; bool _in_v_temp_write;
AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f, .y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss); AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply); delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss); INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf<nw> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply); sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
sigbuf<wl> clock_buffer[nw]; sigbuf<wl> clock_buffer[nw];
bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl]; bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
// Sending back to the ackowledge // Sending back to the acknowledge
bool _in_a_write_temp; bool _in_a_write_temp;
delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply); delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss); AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
@ -154,7 +154,6 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
ortree<nw> bitselector_f[wl]; ortree<nw> bitselector_f[wl];
AND2_X1 word_selector_t[nw*wl]; AND2_X1 word_selector_t[nw*wl];
AND2_X1 word_selector_f[nw*wl]; AND2_X1 word_selector_f[nw*wl];
bool _out_word_to_read[2*nw*wl];
buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B); buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw]; AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
// Outputting the address if the read is true // Outputting the address if the read is true
@ -186,6 +185,11 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
// Creating the different flip flop arrays // Creating the different flip flop arrays
bool _out_encoder[nw]; bool _out_encoder[nw];
DFFQ_R_X1 ff[nw*wl]; DFFQ_R_X1 ff[nw*wl];
AND2_X1 val_chck[nw*wl];
bool _val_chck_out[nw*wl];
bool _in_v_temp_buf[nw*wl];
sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
// For loop for assigning the different components // For loop for assigning the different components
pint bitval; pint bitval;
(k:nw:atree[k].supply = supply;) (k:nw:atree[k].supply = supply;)
@ -221,9 +225,13 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
word_to_read_X[word_idx].supply = supply; word_to_read_X[word_idx].supply = supply;
(bit_idx:wl: (bit_idx:wl:
// Describing all the FF and their connection // Describing all the FF and their connection
val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
val_chck[bit_idx].b = in.d.d[bit_idx].t;
val_chck[bit_idx].y = _val_chck_out[bit_idx];
val_chck[bit_idx].vdd = supply.vdd;
val_chck[bit_idx].vss = supply.vss;
ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx]; ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t; ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx]; ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
@ -231,11 +239,11 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
ff[bit_idx+word_idx*(wl)].vdd = supply.vdd; ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff[bit_idx+word_idx*(wl)].vss = supply.vss; ff[bit_idx+word_idx*(wl)].vss = supply.vss;
// READ: creating the selectors for propagating the right word // READ: creating the selectors for propagating the right word
word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+word_idx*(wl)].a; word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+word_idx*(wl)].a; word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q; word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx]; word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q_B; word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx]; word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t; bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f; bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
@ -246,7 +254,5 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
} }
}} }}