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started testing the register_w (doesn't compile)

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Michele
2022-03-04 21:13:10 +01:00
parent 8dabc59a03
commit 7fe31f0ed8
4 changed files with 66 additions and 2 deletions
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6
dataflow_neuro/registers.act
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@ -51,10 +51,12 @@ namespace tmpl {
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint log_nw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power suppy; bool reset_B,reset_mem_B){
defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
//Validation of the input
vtree val_input(.in = in,.out = _in_v_temp, .supply = supply);
Mx1of2<1+log_nw+wl> in_temp;
(i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
in.v = _in_v_temp;
// Generation of the clock pulse