started testing the register_w (doesn't compile)

This commit is contained in:
Michele 2022-03-04 21:13:10 +01:00
parent 8dabc59a03
commit 7fe31f0ed8
4 changed files with 66 additions and 2 deletions

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@ -51,10 +51,12 @@ namespace tmpl {
// - the last wl the word to write // - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw // data -> the data saved in the flip flop, sized wl x nw
export template<pint log_nw,wl,N_dly_cfg> export template<pint log_nw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power suppy; bool reset_B,reset_mem_B){ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock; bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
//Validation of the input //Validation of the input
vtree val_input(.in = in,.out = _in_v_temp, .supply = supply); Mx1of2<1+log_nw+wl> in_temp;
(i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply); sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
in.v = _in_v_temp; in.v = _in_v_temp;
// Generation of the clock pulse // Generation of the clock pulse

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@ -0,0 +1,3 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"

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@ -0,0 +1,51 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
register_rw<2,2,2> registers(.in=in,.data = data);
//Low active Reset
bool _reset_B;
power supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_B_mem = _reset_B;
}
register_test t;

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@ -0,0 +1,8 @@
watchall
system "echo '[0] start test'"
set Reset 1
set-qdi-channel-neutral "t.in" 2
cycle
status X
mode run
system "echo '[1] reset completed'"