Continued test arbiter_handshake, no results
This commit is contained in:
parent
0bdaa87cd2
commit
8057bf54d3
|
@ -517,8 +517,8 @@ namespace tmpl {
|
||||||
[keeper=0] ~a | ~_y2 -> _y1+
|
[keeper=0] ~a | ~_y2 -> _y1+
|
||||||
[keeper=0] b & _y1 -> _y2-
|
[keeper=0] b & _y1 -> _y2-
|
||||||
[keeper=0] ~b | ~_y1 -> _y2+
|
[keeper=0] ~b | ~_y1 -> _y2+
|
||||||
[keeper=0] ~_y1 | ~c => y1+
|
[keeper=0] _y1 | c => y1-
|
||||||
[keeper=0] ~_y2 | ~d => y2+
|
[keeper=0] _y2 | d => y2-
|
||||||
}
|
}
|
||||||
spec {
|
spec {
|
||||||
mk_excllo(y1, y2)
|
mk_excllo(y1, y2)
|
||||||
|
|
|
@ -344,8 +344,8 @@ namespace tmpl {
|
||||||
{
|
{
|
||||||
bool _y1_arb,_y2_arb;
|
bool _y1_arb,_y2_arb;
|
||||||
|
|
||||||
A_2C_B_X1 ack_cel1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
|
A_2C_B_X1 ack_cell1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
|
||||||
A_2C_B_X1 ack_cel2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss);
|
A_2C_B_X1 ack_cell2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss);
|
||||||
OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
|
OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
|
||||||
ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
|
ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
|
||||||
|
|
||||||
|
|
|
@ -107,6 +107,10 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
|
||||||
colour_undefined = (255,0,0)
|
colour_undefined = (255,0,0)
|
||||||
colour_high = (252, 186, 3)
|
colour_high = (252, 186, 3)
|
||||||
colour_low = (20, 184, 186)
|
colour_low = (20, 184, 186)
|
||||||
|
if argv[2] == "-color_Michele":
|
||||||
|
colour_undefined = (32,32,32)
|
||||||
|
colour_high = (98, 187, 93)
|
||||||
|
colour_low = (233, 115, 115)
|
||||||
|
|
||||||
fig = plt.figure(figsize = (num_sigs/3+4,num_times/3+4), dpi = 100)
|
fig = plt.figure(figsize = (num_sigs/3+4,num_times/3+4), dpi = 100)
|
||||||
|
|
||||||
|
|
|
@ -1,63 +1,36 @@
|
||||||
t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.in1.a t.a.arbiter._y2 t.out.a t.a._y2_arb t.a._y1_arb t.a.ack_cel2._y t.in2.a t.a.or_cell._y t.a.ack_cel1._y
|
t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.a.arbiter._y2 t.out.a t.in1.a t.a._y1_arb t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell1._y t.a.ack_cell2._y
|
||||||
0 t.in1.r : 0
|
0 t.in1.r : 0
|
||||||
0 t.out.a : 0
|
0 t.out.a : 0
|
||||||
0 t.in2.r : 0
|
0 t.in2.r : 0
|
||||||
1 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
|
1 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
|
||||||
7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
|
7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
|
||||||
t.out.r t.in1.a t.a._y2_arb t.a._y1_arb t.a.ack_cel2._y t.in2.a t.a.or_cell._y t.a.ack_cel1._y
|
10468 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
|
||||||
|
15221 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
|
||||||
|
16358 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
|
||||||
|
t.out.r t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell2._y
|
||||||
[0] reset done
|
[0] reset done
|
||||||
7092 t.in1.r : 1
|
16358 t.in1.r : 1
|
||||||
17559 t.a.arbiter._y1 : 0 [by t.in1.r:=1]
|
|
||||||
17561 t.a._y1_arb : 1 [by t.a.arbiter._y1:=0]
|
|
||||||
22314 t.a.or_cell._y : 0 [by t.a._y1_arb:=1]
|
|
||||||
23451 t.out.r : 1 [by t.a.or_cell._y:=0]
|
|
||||||
23451 t.out.a : 1
|
|
||||||
23565 t.a.ack_cel1._y : 0 [by t.out.a:=1]
|
|
||||||
88931 t.in1.a : 1 [by t.a.ack_cel1._y:=0]
|
|
||||||
90657 t.a._y2_arb : 0 [by t.in1.a:=1]
|
|
||||||
[1] test in1 done
|
|
||||||
90657 t.in1.r : 0
|
|
||||||
90657 t.out.a : 0
|
|
||||||
90672 t.a.ack_cel2._y : 1 [by t.out.a:=0]
|
|
||||||
WARNING: weak-interference `t.a._y1_arb'
|
WARNING: weak-interference `t.a._y1_arb'
|
||||||
>> cause: t.a.arbiter._y1 (val: 1)
|
>> cause: t.a.arbiter._y1 (val: 0)
|
||||||
>> time: 90696
|
>> time: 16472
|
||||||
90696 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
|
16472 t.a.arbiter._y1 : 0 [by t.in1.r:=1]
|
||||||
WARNING: weak-interference `t.a.or_cell._y'
|
81838 t.a._y1_arb : X [by t.a.arbiter._y1:=0]
|
||||||
>> cause: t.a._y1_arb (val: X)
|
WRONG ASSERT: "t.out.r" has value X and not 1.
|
||||||
>> time: 90709
|
81838 t.out.a : 1
|
||||||
90709 t.a._y1_arb : X [by t.a.arbiter._y1:=1]
|
|
||||||
WARNING: weak-interference `t.in1.a'
|
WARNING: weak-interference `t.in1.a'
|
||||||
>> cause: t.a.ack_cel1._y (val: X)
|
>> cause: t.a.ack_cell1._y (val: X)
|
||||||
>> time: 90749
|
>> time: 83564
|
||||||
90749 t.a.ack_cel1._y : X [by t.a._y1_arb:=X]
|
83564 t.a.ack_cell1._y : X [by t.out.a:=1]
|
||||||
WARNING: weak-interference `t.a._y2_arb'
|
83603 t.in1.a : X [by t.a.ack_cell1._y:=X]
|
||||||
>> cause: t.in1.a (val: X)
|
WRONG ASSERT: "t.in1.a" has value X and not 1.
|
||||||
>> time: 90769
|
[1] test in1 done
|
||||||
90769 t.in1.a : X [by t.a.ack_cel1._y:=X]
|
----------------------------------------------------------------------------------------------------
|
||||||
WARNING: weak-interference `t.out.r'
|
83603 t.in1.r : 0
|
||||||
>> cause: t.a.or_cell._y (val: X)
|
83603 t.out.a : 0
|
||||||
>> time: 91124
|
83618 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
|
||||||
91124 t.a.or_cell._y : X [by t.a._y1_arb:=X]
|
84109 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
|
||||||
91163 t.in2.a : 0 [by t.a.ack_cel2._y:=1]
|
84122 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
|
||||||
91171 t.out.r : X [by t.a.or_cell._y:=X]
|
84162 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
|
||||||
91179 t.a._y1_arb : 1 [by t.in2.a:=0]
|
WRONG ASSERT: "t.out.r" has value X and not 0.
|
||||||
96830 t.a._y2_arb : X [by t.in1.a:=X]
|
WRONG ASSERT: "t.in2.a" has value X and not 0.
|
||||||
135277 t.a.or_cell._y : 0 [by t.a._y1_arb:=1]
|
|
||||||
149001 t.out.r : 1 [by t.a.or_cell._y:=0]
|
|
||||||
t.in1.a t.a._y2_arb t.a.ack_cel1._y
|
|
||||||
WRONG ASSERT: "t.out.r" has value 1 and not 0.
|
|
||||||
WRONG ASSERT: "t.in1.a" has value X and not 0.
|
|
||||||
[2] reset done
|
[2] reset done
|
||||||
149001 t.in2.r : 1
|
|
||||||
149005 t.a.arbiter._y2 : 0 [by t.in2.r:=1]
|
|
||||||
158134 t.a._y2_arb : 1 [by t.a.arbiter._y2:=0]
|
|
||||||
158134 t.out.a : 1
|
|
||||||
158149 t.a.ack_cel2._y : 0 [by t.out.a:=1]
|
|
||||||
195080 t.in2.a : 1 [by t.a.ack_cel2._y:=0]
|
|
||||||
WARNING: unstable `t.a.ack_cel1._y'-
|
|
||||||
>> cause: t.a._y1_arb (val: 0)
|
|
||||||
>> time: 195135
|
|
||||||
195135 t.a._y1_arb : 0 [by t.in2.a:=1]
|
|
||||||
201382 t.a.ack_cel1._y : X [by t.a._y1_arb:=0]
|
|
||||||
[3] test in2 done
|
|
||||||
|
|
|
@ -3,54 +3,54 @@
|
||||||
= "Reset" "Reset"
|
= "Reset" "Reset"
|
||||||
= "t.a.in1.d.d[0]" "t.a.in1.r"
|
= "t.a.in1.d.d[0]" "t.a.in1.r"
|
||||||
= "t.a.in1.a" "t.a.arbiter.d"
|
= "t.a.in1.a" "t.a.arbiter.d"
|
||||||
= "t.a.in1.a" "t.a.ack_cel1.y"
|
= "t.a.in1.a" "t.a.ack_cell1.y"
|
||||||
= "t.a.in1.d.d[0]" "t.a.arbiter.a"
|
= "t.a.in1.d.d[0]" "t.a.arbiter.a"
|
||||||
= "t.a.in1.d.d[0]" "t.a.in1.r"
|
= "t.a.in1.d.d[0]" "t.a.in1.r"
|
||||||
~"t.a.ack_cel1.c1"&~"t.a.ack_cel1.c2"->"t.a.ack_cel1._y"+
|
~"t.a.ack_cell1.c1"&~"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"+
|
||||||
"t.a.ack_cel1.c1"&"t.a.ack_cel1.c2"->"t.a.ack_cel1._y"-
|
"t.a.ack_cell1.c1"&"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"-
|
||||||
"t.a.ack_cel1._y"->"t.a.ack_cel1.y"-
|
"t.a.ack_cell1._y"->"t.a.ack_cell1.y"-
|
||||||
~("t.a.ack_cel1._y")->"t.a.ack_cel1.y"+
|
~("t.a.ack_cell1._y")->"t.a.ack_cell1.y"+
|
||||||
~"t.a.ack_cel2.c1"&~"t.a.ack_cel2.c2"->"t.a.ack_cel2._y"+
|
|
||||||
"t.a.ack_cel2.c1"&"t.a.ack_cel2.c2"->"t.a.ack_cel2._y"-
|
|
||||||
"t.a.ack_cel2._y"->"t.a.ack_cel2.y"-
|
|
||||||
~("t.a.ack_cel2._y")->"t.a.ack_cel2.y"+
|
|
||||||
= "t.a.in2.d.d[0]" "t.a.in2.r"
|
= "t.a.in2.d.d[0]" "t.a.in2.r"
|
||||||
= "t.a.in2.a" "t.a.arbiter.c"
|
= "t.a.in2.a" "t.a.arbiter.c"
|
||||||
= "t.a.in2.a" "t.a.ack_cel2.y"
|
= "t.a.in2.a" "t.a.ack_cell2.y"
|
||||||
= "t.a.in2.d.d[0]" "t.a.arbiter.b"
|
= "t.a.in2.d.d[0]" "t.a.arbiter.b"
|
||||||
= "t.a.in2.d.d[0]" "t.a.in2.r"
|
= "t.a.in2.d.d[0]" "t.a.in2.r"
|
||||||
= "t.a.supply.vdd" "t.a.arbiter.vdd"
|
= "t.a.supply.vdd" "t.a.arbiter.vdd"
|
||||||
= "t.a.supply.vdd" "t.a.or_cell.vdd"
|
= "t.a.supply.vdd" "t.a.or_cell.vdd"
|
||||||
= "t.a.supply.vdd" "t.a.ack_cel2.vdd"
|
= "t.a.supply.vdd" "t.a.ack_cell2.vdd"
|
||||||
= "t.a.supply.vdd" "t.a.ack_cel1.vdd"
|
= "t.a.supply.vdd" "t.a.ack_cell1.vdd"
|
||||||
= "t.a.supply.vss" "t.a.arbiter.vss"
|
= "t.a.supply.vss" "t.a.arbiter.vss"
|
||||||
= "t.a.supply.vss" "t.a.or_cell.vss"
|
= "t.a.supply.vss" "t.a.or_cell.vss"
|
||||||
= "t.a.supply.vss" "t.a.ack_cel2.vss"
|
= "t.a.supply.vss" "t.a.ack_cell2.vss"
|
||||||
= "t.a.supply.vss" "t.a.ack_cel1.vss"
|
= "t.a.supply.vss" "t.a.ack_cell1.vss"
|
||||||
"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"-
|
"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"-
|
||||||
~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+
|
~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+
|
||||||
"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"-
|
"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"-
|
||||||
~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+
|
~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+
|
||||||
~"t.a.arbiter._y1"|~"t.a.arbiter.c"->"t.a.arbiter.y1"+
|
"t.a.arbiter._y1"|"t.a.arbiter.c"->"t.a.arbiter.y1"-
|
||||||
~(~"t.a.arbiter._y1"|~"t.a.arbiter.c")->"t.a.arbiter.y1"-
|
~("t.a.arbiter._y1"|"t.a.arbiter.c")->"t.a.arbiter.y1"+
|
||||||
~"t.a.arbiter._y2"|~"t.a.arbiter.d"->"t.a.arbiter.y2"+
|
"t.a.arbiter._y2"|"t.a.arbiter.d"->"t.a.arbiter.y2"-
|
||||||
~(~"t.a.arbiter._y2"|~"t.a.arbiter.d")->"t.a.arbiter.y2"-
|
~("t.a.arbiter._y2"|"t.a.arbiter.d")->"t.a.arbiter.y2"+
|
||||||
mk_excllo("t.a.arbiter._y1","t.a.arbiter._y2")
|
mk_excllo("t.a.arbiter.y1","t.a.arbiter.y2")
|
||||||
= "t.a._y1_arb" "t.a.arbiter.y1"
|
= "t.a._y1_arb" "t.a.arbiter.y1"
|
||||||
= "t.a._y1_arb" "t.a.or_cell.a"
|
= "t.a._y1_arb" "t.a.or_cell.a"
|
||||||
= "t.a._y1_arb" "t.a.ack_cel1.c2"
|
= "t.a._y1_arb" "t.a.ack_cell1.c2"
|
||||||
|
~"t.a.ack_cell2.c1"&~"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"+
|
||||||
|
"t.a.ack_cell2.c1"&"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"-
|
||||||
|
"t.a.ack_cell2._y"->"t.a.ack_cell2.y"-
|
||||||
|
~("t.a.ack_cell2._y")->"t.a.ack_cell2.y"+
|
||||||
"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"-
|
"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"-
|
||||||
~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+
|
~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+
|
||||||
"t.a.or_cell._y"->"t.a.or_cell.y"-
|
"t.a.or_cell._y"->"t.a.or_cell.y"-
|
||||||
~("t.a.or_cell._y")->"t.a.or_cell.y"+
|
~("t.a.or_cell._y")->"t.a.or_cell.y"+
|
||||||
= "t.a.out.d.d[0]" "t.a.out.r"
|
= "t.a.out.d.d[0]" "t.a.out.r"
|
||||||
= "t.a.out.a" "t.a.ack_cel2.c1"
|
= "t.a.out.a" "t.a.ack_cell2.c1"
|
||||||
= "t.a.out.a" "t.a.ack_cel1.c1"
|
= "t.a.out.a" "t.a.ack_cell1.c1"
|
||||||
= "t.a.out.d.d[0]" "t.a.or_cell.y"
|
= "t.a.out.d.d[0]" "t.a.or_cell.y"
|
||||||
= "t.a.out.d.d[0]" "t.a.out.r"
|
= "t.a.out.d.d[0]" "t.a.out.r"
|
||||||
= "t.a._y2_arb" "t.a.arbiter.y2"
|
= "t.a._y2_arb" "t.a.arbiter.y2"
|
||||||
= "t.a._y2_arb" "t.a.or_cell.b"
|
= "t.a._y2_arb" "t.a.or_cell.b"
|
||||||
= "t.a._y2_arb" "t.a.ack_cel2.c2"
|
= "t.a._y2_arb" "t.a.ack_cell2.c2"
|
||||||
= "Vdd" "t.a.supply.vdd"
|
= "Vdd" "t.a.supply.vdd"
|
||||||
= "GND" "t.a.supply.vss"
|
= "GND" "t.a.supply.vss"
|
||||||
= "t.in1.d.d[0]" "t.in1.r"
|
= "t.in1.d.d[0]" "t.in1.r"
|
||||||
|
|
|
@ -15,25 +15,15 @@ set t.out.a 1
|
||||||
cycle
|
cycle
|
||||||
assert t.in1.a 1
|
assert t.in1.a 1
|
||||||
system "echo '[1] test in1 done'"
|
system "echo '[1] test in1 done'"
|
||||||
|
system "echo '----------------------------------------------------------------------------------------------------'"
|
||||||
set t.in1.r 0
|
set t.in1.r 0
|
||||||
set t.in2.r 0
|
set t.in2.r 0
|
||||||
set t.out.a 0
|
set t.out.a 0
|
||||||
cycle
|
cycle
|
||||||
status X
|
|
||||||
mode run
|
|
||||||
assert t.out.r 0
|
assert t.out.r 0
|
||||||
assert t.in1.a 0
|
assert t.in1.a 0
|
||||||
assert t.in2.a 0
|
assert t.in2.a 0
|
||||||
system "echo '[2] reset done'"
|
system "echo '[2] reset done'"
|
||||||
|
|
||||||
set t.in2.r 1
|
|
||||||
set t.in1.r 0
|
|
||||||
set t.out.a 0
|
|
||||||
cycle
|
|
||||||
assert t.out.r 1
|
|
||||||
set t.out.a 1
|
|
||||||
cycle
|
|
||||||
assert t.in2.a 1
|
|
||||||
system "echo '[3] test in2 done'"
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue