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AND grid init

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alexmadison
2022-03-03 17:09:00 +01:00
parent da5948f493
commit 893f71db92
1 changed files with 13 additions and 3 deletions
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dataflow_neuro/coders.act
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@@ -44,7 +44,7 @@ namespace tmpl {
* Thus NxC should be something like NxC = ceil(log2(Nx)) * Thus NxC should be something like NxC = ceil(log2(Nx))
* but my guess is that we can't do logs... * but my guess is that we can't do logs...
* N_dly_cfg is the number of config bits in the ACK delay line, * N_dly_cfg is the number of config bits in the ACK delay line,
* with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells. * with all bits high corresponding to 2**N_dly_cfg -1 DLY4_X1 cells.
*/ */
export template<pint NxC, NyC, Nx, Ny, N_dly_cfg> export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny], defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
@@ -212,9 +212,19 @@ namespace tmpl {
} }
export template<pint Nx, Ny>
defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
AND2_X1 ands[Nx*Ny];
(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
(x:0..Nx-1:
(y:0..Ny-1:
ands[x + y*Nx].a = inx[x];
ands[x + y*Nx].b = iny[y];
ands[x + y*Nx].y = out[x + y*Nx];
)
)
}
} }