flipflop test updated
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parent
c30a46d6d8
commit
8dabc59a03
@ -1,9 +1,35 @@
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t.clk t.d t.q t.ff._qb t.ff._q_B t.ff.__clk t.ff._dl t.ff._clk
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t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk
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[0] start test
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[0] start test
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1 t.d : 0
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1 t.clk : 0
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7093 t.ff._mqib : 1 [by t.d:=0]
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7095 t.ff._mqi : 0 [by t.ff._mqib:=1]
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10468 t.ff._clk : 1 [by t.clk:=0]
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11605 t.ff.__clk : 0 [by t.ff._clk:=1]
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11848 t.ff._sqib : 1 [by t.ff._mqi:=0]
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11962 t.ff._sqi : 0 [by t.ff._sqib:=1]
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77214 t.q : 0 [by t.ff._sqib:=1]
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77214 Reset : 0
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78940 t._reset_B : 1 [by Reset:=0]
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[1] reset completed
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[1] reset completed
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WRONG ASSERT: "t.q" has value 1 and not 0.
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78940 t.clk : 1
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[2] setting d to 1
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78979 t.ff._clk : 0 [by t.clk:=1]
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WRONG ASSERT: "t.q" has value 1 and not 0.
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78994 t.ff.__clk : 1 [by t.ff._clk:=0]
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[3] setting clk to 1
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[2] tested d = 0, clk rise
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[4] Finished
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78994 t.clk : 0
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79485 t.ff._clk : 1 [by t.clk:=0]
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79498 t.ff.__clk : 0 [by t.ff._clk:=1]
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79498 t.d : 1
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79498 t.clk : 1
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79538 t.ff._clk : 0 [by t.clk:=1]
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79953 t.ff.__clk : 1 [by t.ff._clk:=0]
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79973 t.ff._mqib : 0 [by t.ff.__clk:=1]
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86034 t.ff._mqi : 1 [by t.ff._mqib:=0]
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86034 t.clk : 0
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86081 t.ff._clk : 1 [by t.clk:=0]
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86097 t.ff.__clk : 0 [by t.ff._clk:=1]
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130179 t.ff._sqib : 0 [by t.ff._clk:=1]
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130183 t.q : 1 [by t.ff._sqib:=0]
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143903 t.ff._sqi : 1 [by t.ff._sqib:=0]
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[3] tested d = 1, clk rise and fall
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@ -3,25 +3,21 @@
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= "Reset" "Reset"
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= "Reset" "Reset"
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"Reset"->"t._reset_B"-
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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~("Reset")->"t._reset_B"+
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"t.ff._q_B"->"t.ff.q"-
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= "t._reset_B" "t.ff.reset_B"
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~"t.ff._q_B"->"t.ff.q"+
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"t.ff.clk"->"t.ff._clk"-
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"t.ff.clk"->"t.ff._clk"-
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~"t.ff.clk"->"t.ff._clk"+
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~("t.ff.clk")->"t.ff._clk"+
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"t.ff._clk"->"t.ff.__clk"-
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"t.ff._clk"->"t.ff.__clk"-
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~"t.ff._clk"->"t.ff.__clk"+
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~("t.ff._clk")->"t.ff.__clk"+
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"t.ff.reset"->"t.ff._Ro"-
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~"t.ff.d"&~"t.ff._clk"|~"t.ff.reset_B"|~"t.ff.__clk"&~"t.ff._mqi"->"t.ff._mqib"+
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~"t.ff.reset"->"t.ff._Ro"+
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"t.ff.d"&"t.ff.__clk"|"t.ff.reset_B"&"t.ff._mqi"&"t.ff._clk"->"t.ff._mqib"-
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"t.ff.d"&"t.ff._clk"->"t.ff._dl"-
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"t.ff._mqib"->"t.ff._mqi"-
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~"t.ff.d"&~"t.ff.__clk"->"t.ff._dl"+
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~("t.ff._mqib")->"t.ff._mqi"+
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"t.ff.reset"&"t.ff._qb"->"t.ff._q_B"-
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~"t.ff._mqi"&~"t.ff.__clk"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk"->"t.ff._sqib"+
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~"t.ff.reset"|~"t.ff._qb"->"t.ff._q_B"+
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"t.ff._mqi"&"t.ff._clk"|"t.ff._sqi"&"t.ff.__clk"&"t.ff.reset_B"->"t.ff._sqib"-
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after 0 "t.ff.__clk" & ~"t.ff._Ro" -> "t.ff._dl"-
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"t.ff._sqib"->"t.ff._sqi"-
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~"t.ff._clk" & "t.ff._Ro" -> "t.ff._dl"+
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~("t.ff._sqib")->"t.ff._sqi"+
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after 0 "t.ff.__clk" & ~"t.ff.reset" -> "t.ff._qb"-
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"t.ff._sqib"->"t.ff.q"-
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~"t.ff._clk" & "t.ff.reset" -> "t.ff._qb"+
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~("t.ff._sqib")->"t.ff.q"+
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after 0 "t.ff._clk" & ~"t.ff.reset" -> "t.ff._qb"-
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~"t.ff.__clk" & "t.ff.reset" -> "t.ff._qb"+
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= "Reset" "t.ff.reset"
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= "Vdd" "t.ff.vdd"
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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= "t.q" "t.ff.q"
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@ -41,7 +41,7 @@ defproc flipflop_test (bool! q; bool? d,clk){
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}
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}
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ff.vss = GND;
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ff.vss = GND;
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ff.vdd = Vdd;
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ff.vdd = Vdd;
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ff.reset = Reset;
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ff.reset_B = _reset_B;
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}
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}
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@ -1,21 +1,28 @@
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watchall
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set t.d 0
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set t.clk 0
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set Reset 0
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cycle
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assert t.q 0
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system "echo '[0] start test'"
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system "echo '[0] start test'"
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set Reset 1
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set Reset 1
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set t.d 0
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set t.clk 0
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cycle
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cycle
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status X
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status X
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mode run
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mode run
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assert t.q 0
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set Reset 0
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cycle
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assert t.q 0
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system "echo '[1] reset completed'"
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system "echo '[1] reset completed'"
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system "echo '[2] setting d to 1'"
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set t.clk 1
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set t.clk 1
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cycle
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cycle
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assert t.q 0
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assert t.q 0
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system "echo '[3] setting clk to 1'"
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system "echo '[2] tested d = 0, clk rise'"
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set t.clk 0
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cycle
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set t.d 1
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cycle
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set t.clk 1
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set t.clk 1
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cycle
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cycle
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assert t.q 0
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set t.clk 0
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cycle
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assert t.q 1
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assert t.q 1
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system "echo '[4] Finished'"
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system "echo '[3] tested d = 1, clk rise and fall'"
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