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flipflop test updated

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This commit is contained in:
Michele 2022-03-04 21:12:52 +01:00
parent c30a46d6d8
commit 8dabc59a03
4 changed files with 62 additions and 33 deletions
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38
test/unit_tests/flipflop/run/prsim.out
View File

@ -1,9 +1,35 @@
t.clk t.d t.q t.ff._qb t.ff._q_B t.ff.__clk t.ff._dl t.ff._clk
t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk
[0] start test
1 t.d : 0
1 t.clk : 0
7093 t.ff._mqib : 1 [by t.d:=0]
7095 t.ff._mqi : 0 [by t.ff._mqib:=1]
10468 t.ff._clk : 1 [by t.clk:=0]
11605 t.ff.__clk : 0 [by t.ff._clk:=1]
11848 t.ff._sqib : 1 [by t.ff._mqi:=0]
11962 t.ff._sqi : 0 [by t.ff._sqib:=1]
77214 t.q : 0 [by t.ff._sqib:=1]
77214 Reset : 0
78940 t._reset_B : 1 [by Reset:=0]
[1] reset completed
WRONG ASSERT: "t.q" has value 1 and not 0.
[2] setting d to 1
WRONG ASSERT: "t.q" has value 1 and not 0.
[3] setting clk to 1
[4] Finished
78940 t.clk : 1
78979 t.ff._clk : 0 [by t.clk:=1]
78994 t.ff.__clk : 1 [by t.ff._clk:=0]
[2] tested d = 0, clk rise
78994 t.clk : 0
79485 t.ff._clk : 1 [by t.clk:=0]
79498 t.ff.__clk : 0 [by t.ff._clk:=1]
79498 t.d : 1
79498 t.clk : 1
79538 t.ff._clk : 0 [by t.clk:=1]
79953 t.ff.__clk : 1 [by t.ff._clk:=0]
79973 t.ff._mqib : 0 [by t.ff.__clk:=1]
86034 t.ff._mqi : 1 [by t.ff._mqib:=0]
86034 t.clk : 0
86081 t.ff._clk : 1 [by t.clk:=0]
86097 t.ff.__clk : 0 [by t.ff._clk:=1]
130179 t.ff._sqib : 0 [by t.ff._clk:=1]
130183 t.q : 1 [by t.ff._sqib:=0]
143903 t.ff._sqi : 1 [by t.ff._sqib:=0]
[3] tested d = 1, clk rise and fall

30
test/unit_tests/flipflop/run/test.prs
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@ -3,25 +3,21 @@
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
"t.ff._q_B"->"t.ff.q"-
~"t.ff._q_B"->"t.ff.q"+
= "t._reset_B" "t.ff.reset_B"
"t.ff.clk"->"t.ff._clk"-
~"t.ff.clk"->"t.ff._clk"+
~("t.ff.clk")->"t.ff._clk"+
"t.ff._clk"->"t.ff.__clk"-
~"t.ff._clk"->"t.ff.__clk"+
"t.ff.reset"->"t.ff._Ro"-
~"t.ff.reset"->"t.ff._Ro"+
"t.ff.d"&"t.ff._clk"->"t.ff._dl"-
~"t.ff.d"&~"t.ff.__clk"->"t.ff._dl"+
"t.ff.reset"&"t.ff._qb"->"t.ff._q_B"-
~"t.ff.reset"|~"t.ff._qb"->"t.ff._q_B"+
after 0 "t.ff.__clk" & ~"t.ff._Ro" -> "t.ff._dl"-
~"t.ff._clk" & "t.ff._Ro" -> "t.ff._dl"+
after 0 "t.ff.__clk" & ~"t.ff.reset" -> "t.ff._qb"-
~"t.ff._clk" & "t.ff.reset" -> "t.ff._qb"+
after 0 "t.ff._clk" & ~"t.ff.reset" -> "t.ff._qb"-
~"t.ff.__clk" & "t.ff.reset" -> "t.ff._qb"+
= "Reset" "t.ff.reset"
~("t.ff._clk")->"t.ff.__clk"+
~"t.ff.d"&~"t.ff._clk"|~"t.ff.reset_B"|~"t.ff.__clk"&~"t.ff._mqi"->"t.ff._mqib"+
"t.ff.d"&"t.ff.__clk"|"t.ff.reset_B"&"t.ff._mqi"&"t.ff._clk"->"t.ff._mqib"-
"t.ff._mqib"->"t.ff._mqi"-
~("t.ff._mqib")->"t.ff._mqi"+
~"t.ff._mqi"&~"t.ff.__clk"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk"->"t.ff._sqib"+
"t.ff._mqi"&"t.ff._clk"|"t.ff._sqi"&"t.ff.__clk"&"t.ff.reset_B"->"t.ff._sqib"-
"t.ff._sqib"->"t.ff._sqi"-
~("t.ff._sqib")->"t.ff._sqi"+
"t.ff._sqib"->"t.ff.q"-
~("t.ff._sqib")->"t.ff.q"+
= "Vdd" "t.ff.vdd"
= "GND" "t.ff.vss"
= "t.q" "t.ff.q"

2
test/unit_tests/flipflop/test.act
View File

@ -41,7 +41,7 @@ defproc flipflop_test (bool! q; bool? d,clk){
}
ff.vss = GND;
ff.vdd = Vdd;
ff.reset = Reset;
ff.reset_B = _reset_B;
}

25
test/unit_tests/flipflop/test.prsim
View File

@ -1,21 +1,28 @@
set t.d 0
set t.clk 0
set Reset 0
cycle
assert t.q 0
watchall
system "echo '[0] start test'"
set Reset 1
set t.d 0
set t.clk 0
cycle
status X
mode run
assert t.q 0
set Reset 0
cycle
assert t.q 0
system "echo '[1] reset completed'"
system "echo '[2] setting d to 1'"
set t.clk 1
cycle
assert t.q 0
system "echo '[3] setting clk to 1'"
system "echo '[2] tested d = 0, clk rise'"
set t.clk 0
cycle
set t.d 1
cycle
set t.clk 1
cycle
assert t.q 0
set t.clk 0
cycle
assert t.q 1
system "echo '[4] Finished'"
system "echo '[3] tested d = 1, clk rise and fall'"