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encoder in register works

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Michele
2022-03-05 20:33:38 +01:00
parent cf66c0e665
commit 932e967f3d
4 changed files with 306 additions and 314 deletions
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572
test/unit_tests/register_write/run/prsim.out
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32
test/unit_tests/register_write/run/test.prs
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@ -338,27 +338,27 @@
= "t.registers.in.d.d[4].d[1]" "t.registers._in_temp.d[4].d[1]"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[5].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[4].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[1].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[0].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[7].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[6].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[3].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[2].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[5].in[1]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[4].in[1]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[1].in[1]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[1]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[6].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[4].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[2].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[7].in[1]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[6].in[1]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[1]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[2].in[1]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[7].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[5].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[1].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[6].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[4].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[2].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[0].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[7].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[5].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[3].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[1].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"

2
test/unit_tests/register_write/test.prsim
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@ -31,6 +31,8 @@ assert-qdi-channel-valid "t.in" 5 3
assert t.registers._clock 1
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 0