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encoder in register works

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This commit is contained in:
Michele 2022-03-05 20:33:38 +01:00
parent cf66c0e665
commit 932e967f3d
4 changed files with 306 additions and 314 deletions
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14
dataflow_neuro/registers.act
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@ -83,9 +83,9 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
(pin_idx:log_nw: (pin_idx:log_nw:
_bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j _bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[_bitval = 1 -> [_bitval = 1 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].t; atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] _bitval = 0 -> [] _bitval = 0 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].f; atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]_bitval >= 2 -> {false : "fuck"}; []_bitval >= 2 -> {false : "fuck"};
] ]
) )
@ -98,15 +98,7 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
and_encoder[_word_idx].vss = supply.vss; and_encoder[_word_idx].vss = supply.vss;
clock_buffer[_word_idx].in = _clock_word_temp[_word_idx]; clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
clock_buffer[_word_idx].supply = supply; clock_buffer[_word_idx].supply = supply;
// Describing all the FF and their connection
(_bit_idx:wl:
ff[_bit_idx*(1+_word_idx)].clk = clock_buffer[_word_idx].out[_bit_idx];
ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
)
) )
} }
}} }}

572
test/unit_tests/register_write/run/prsim.out
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32
test/unit_tests/register_write/run/test.prs
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@ -338,27 +338,27 @@
= "t.registers.in.d.d[4].d[1]" "t.registers._in_temp.d[4].d[1]" = "t.registers.in.d.d[4].d[1]" "t.registers._in_temp.d[4].d[1]"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f" = "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t" = "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[5].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[4].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[1].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[0].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f" = "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[7].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[6].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[3].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[2].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t" = "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[5].in[1]" = "t.registers.in.d.d[2].d[0]" "t.registers.atree[6].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[4].in[1]" = "t.registers.in.d.d[2].d[0]" "t.registers.atree[4].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[1].in[1]" = "t.registers.in.d.d[2].d[0]" "t.registers.atree[2].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[1]" = "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f" = "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[7].in[1]" = "t.registers.in.d.d[2].d[1]" "t.registers.atree[7].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[6].in[1]" = "t.registers.in.d.d[2].d[1]" "t.registers.atree[5].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[1]" = "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[2].in[1]" = "t.registers.in.d.d[2].d[1]" "t.registers.atree[1].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t" = "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[6].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[4].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[2].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.atree[0].in[0]"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f" = "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[7].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[5].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[3].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.atree[1].in[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t" = "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f" = "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t" = "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"

2
test/unit_tests/register_write/test.prsim
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@ -31,6 +31,8 @@ assert-qdi-channel-valid "t.in" 5 3
assert t.registers._clock 1 assert t.registers._clock 1
assert t.registers._out_encoder[0] 1 assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0 assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
set-qdi-channel-neutral "t.in" 5 set-qdi-channel-neutral "t.in" 5
cycle cycle
assert t.registers._clock 0 assert t.registers._clock 0