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decoder 2d dly init

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alexmadison
2022-03-02 15:55:26 +01:00
parent 3bba9fefa4
commit 9c27248e12
6 changed files with 2626 additions and 99 deletions
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154
dataflow_neuro/coders.act
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@ -37,8 +37,6 @@ open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
* Nx is the x size of the decoder array
@ -48,111 +46,69 @@ namespace tmpl {
* N_dly_cfg is the number of config bits in the ACK delay line,
* with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells.
*/
// export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
// defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? dly_cfg[N_dly_cfg], reset_B; power supply) {
export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
dly_cfg[N_dly_cfg], reset_B; power supply) {
// // Buffer to recieve concat(x,y) address packet
// buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// // NEED TO BUFFER OUTPUTS FROM BUFFER I RECKON
// Buffer to recieve concat(x,y) address packet
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// NEED TO BUFFER OUTPUTS FROM BUFFER I RECKON
// // Validity trees
// vtree<NxC> vtree_x (.power = supply);
// vtree<NyC> vtree_y (.power = supply);
// (i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
// (i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
// (i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
// (i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
// Validity trees
vtree<NxC> vtree_x (.supply = supply);
vtree<NyC> vtree_y (.supply = supply);
(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
// // Delay ack line. Ack line is delayed (but not the val)
// A_2X_B_X1 C2el(.a = vtree_x.out, .b = vtree_y.out, .supply = supply);
// addr_buf.out.v = C2el.y;
// delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
// delayprog.out = addr_buf.out.a;
// // AND trees
// Delay ack line. Ack line is delayed (but not the val)
A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
addr_buf.out.v = C2el.y;
// delayprog<N_dly_cfg> dly(.in = tielow.y, .s = dly_cfg, .supply = supply);
delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
// pint bitval;
// ACK MAY HAVE BEEN DISCONNECTED HERE
// FOR TESTING PURPOSES
// !!!!!!!!!!!!!!!!
dly.out = addr_buf.out.a;
// ACK MAY HAVE BEEN DISCONNECTED HERE
// FOR TESTING PURPOSES
// !!!!!!!!!!!!!!!!
// andtree<NxC> atree_x[Nx];
// (i:0..Nx-1:
// (j:0..NxC:
// bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
// [bitval == 1 ->
// atree_x[i].in[j] = addr_buf.out.d.d[j].t
// []bitval == 0 ->
// atree_x[i].in[j] = addr_buf.out.d.d[j].f
// ]
// )
// )
// AND trees
pint bitval;
andtree<NxC> atree_x[Nx];
(k:0..Nx-1:atree_x[k].supply = supply;)
(i:0..Nx-1:
(j:0..NxC-1:
bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
[bitval = 1 ->
atree_x[i].in[j] = addr_buf.out.d.d[j].t;
[]bitval = 0 ->
atree_x[i].in[j] = addr_buf.out.d.d[j].f;
[]bitval >= 2 -> {false : "fuck"};
]
atree_x[i].out = outx[i];
)
)
// andtree<NyC> atree_y[Ny];
// (i:0..Ny-1:
// (j:0..NyC:
// bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
// [bitval == 1 ->
// atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].t
// []bitval == 0 ->
// atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].f
// ]
// )
// )
andtree<NyC> atree_y[Ny];
(k:0..Ny-1:atree_y[k].supply = supply;)
(i:0..Ny-1:
(j:0..NyC-1:
bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
[bitval = 1 ->
atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].t;
[]bitval = 0 ->
atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].f;
]
atree_y[i].out = outy[i];
)
)
// // Connect stuff to vdd/vss
// (i:0..Nx-1:atree_x[i].supply = supply)
// //control
// bool _en, _reset_BX,_reset_BXX[N];
// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
// //validity
// bool _in_v;
// vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
// BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
// //function
// bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
// A_2C1N_RB_X4 f_buf_func[N];
// A_2C1N_RB_X4 t_buf_func[N];
// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
// sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
// INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
// sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
// sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
// // check if you can also do single var to array connect a=b[N]
// // and remove them from the loop
// (i:N:
// f_buf_func[i].y=out.d.d[i].f;
// t_buf_func[i].y=out.d.d[i].t;
// f_buf_func[i].c1=_en_X_f[i];
// t_buf_func[i].c1=_en_X_t[i];
// f_buf_func[i].c2=_out_a_BX_f[i];
// t_buf_func[i].c2=_out_a_BX_t[i];
// f_buf_func[i].n1=in.d.d[i].f;
// t_buf_func[i].n1=in.d.d[i].t;
// f_buf_func[i].vdd=supply.vdd;
// t_buf_func[i].vdd=supply.vdd;
// f_buf_func[i].vss=supply.vss;
// t_buf_func[i].vss=supply.vss;
// t_buf_func[i].pr_B = _reset_BXX[i];
// t_buf_func[i].sr_B = _reset_BXX[i];
// f_buf_func[i].pr_B = _reset_BXX[i];
// f_buf_func[i].sr_B = _reset_BXX[i];
)
}