write register array compiling

dataflow_neuro/registers.act

@@ -334,7 +334,7 @@ sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
 
 
 /**
- * Register made out of A cells.
+ * A single register made out of A cells.
  * last bit is whether to read or write.
  * Currently only handles writing.
  */
@@ -360,7 +360,7 @@ buf.in.v = in.v;
 // In ack stuff
 INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
 // To stop in ack going low before en2 has been reset.
-A_1C1N_X1 in_ack_safety(.c1 = buf.in.a, .n1 = _en2, .y = in.a,
+A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
     .vdd = supply.vdd, .vss = supply.vss);
 
 // Out valid tree
@@ -372,7 +372,8 @@ A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _
     .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
 INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
 
-A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2);
+A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
+    .pr_B = reset_B, .sr_B = reset_B);
 
 // Pass to let data into the buffer
 NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
@@ -398,5 +399,85 @@ AND2_X1 gandalf_f[N];
 
 
 
+/** 
+ * Array of registers made out of A-cells
+ * params:
+ * NcW: number of bits in Words to be stored in buffers
+ * NcA: number of bits in Address
+ * M: number of registers.  M = 2^Nc_addr would be a natural choice.
+ * Input packets should be 
+ * [-addr-][-word-][r/w]
+ */
+export template<pint NcA, NcW, M>
+defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
+    bool? reset_B; power supply) {
+
+// BIG TODO
+// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
+
+// Input valid tree
+// Note that I may need to check the validity of other downstream stuff,
+// to be ultra careful about delays.
+vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
+    .supply = supply);
+
+// Address decoder
+decoder_dualrail<NcA, M> decoder(.supply = supply);
+(i:NcA:
+    decoder.in.d[i] = in.d.d[i];
+)
+
+// OrTree over acks from all registers
+ortree<M> ack_ortree(.supply = supply);
+
+// C element handling in ack
+A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
+    .vss = supply.vss, .vdd = supply.vdd); 
+
+// Write bit selector
+bool _w = in.d.d[NcA+NcW].t;
+AND2_X1 write_selectors[M];
+(i:M:
+    write_selectors[i].a = _w;
+    write_selectors[i].b = decoder.out[i];
+    write_selectors[i].vdd = supply.vdd;
+    write_selectors[i].vss = supply.vss;
+)
+
+// Registers
+registerA<NcW> registers[M];
+TIELO_X1 tielow_writebit_f[M];
+(i:M:
+    // Connect each register to word inputs.
+    (j:NcW:
+        registers[i].in.d.d[j] = in.d.d[j + NcA];
+    )
+
+    // Connect the (selected) write bit
+    registers[i].in.d.d[NcA + NcW].t = write_selectors[i].y;
+    tielow_writebit_f[i].vdd = supply.vdd;
+    tielow_writebit_f[i].vss = supply.vss;
+    registers[i].in.d.d[NcA + NcW].f = tielow_writebit_f[i].y;
+
+    // Connect to ack ortree
+    registers[i].in.a = ack_ortree.in[i];
+
+    // Connect outputs
+    data[i] = registers[i].out;
+
+    registers[i].supply = supply;
+    registers[i].reset_B = reset_B;
+)
+
+
+
+
+
+}
+
+
+
+
+
 }}