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register simulates correctly up to the fake clock generation

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Michele
2022-03-05 20:28:50 +01:00
parent 78a8f72d25
commit aa67bd6168
5 changed files with 1458 additions and 10 deletions
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9
dataflow_neuro/registers.act
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@ -55,12 +55,11 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
pint _nw = 2<<log_nw;
//Validation of the input
Mx1of2<1+log_nw+wl> in_temp;
(i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
Mx1of2<1+log_nw+wl> _in_temp;
(i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
in.v = _in_v_temp;
// Generation of the clock pulse
// Generation of the fake clock pulse
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
// Sending back to the ackowledge